arch/mips/include/asm/octeon/octeon.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004-2008 Cavium Networks
   7  */
   8 #ifndef __ASM_OCTEON_OCTEON_H
   9 #define __ASM_OCTEON_OCTEON_H
  10
  11 #include "cvmx.h"
  12
  13 extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size,
  14                                                 uint64_t alignment,
  15                                                 uint64_t min_addr,
  16                                                 uint64_t max_addr,
  17                                                 int do_locking);
  18 extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment,
  19                                   int do_locking);
  20 extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment,
  21                                         uint64_t min_addr, uint64_t max_addr,
  22                                         int do_locking);
  23 extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment,
  24                                         char *name);
  25 extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr,
  26                                               uint64_t max_addr, uint64_t align,
  27                                               char *name);
  28 extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address,
  29                                                 char *name);
  30 extern int octeon_bootmem_free_named(char *name);
  31 extern void octeon_bootmem_lock(void);
  32 extern void octeon_bootmem_unlock(void);
  33
  34 extern int octeon_is_simulation(void);
  35 extern int octeon_is_pci_host(void);
  36 extern int octeon_usb_is_ref_clk(void);
  37 extern uint64_t octeon_get_clock_rate(void);
  38 extern const char *octeon_board_type_string(void);
  39 extern const char *octeon_get_pci_interrupts(void);
  40 extern int octeon_get_southbridge_interrupt(void);
  41 extern int octeon_get_boot_coremask(void);
  42 extern int octeon_get_boot_num_arguments(void);
  43 extern const char *octeon_get_boot_argument(int arg);
  44 extern void octeon_hal_setup_reserved32(void);
  45 extern void octeon_user_io_init(void);
  46 struct octeon_cop2_state;
  47 extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
  48 extern void octeon_crypto_disable(struct octeon_cop2_state *state,
  49                                   unsigned long flags);
  50
  51 extern void octeon_init_cvmcount(void);
  52
  53 #define OCTEON_ARGV_MAX_ARGS    64
  54 #define OCTOEN_SERIAL_LEN       20
  55
  56 struct octeon_boot_descriptor {
  57         /* Start of block referenced by assembly code - do not change! */
  58         uint32_t desc_version;
  59         uint32_t desc_size;
  60         uint64_t stack_top;
  61         uint64_t heap_base;
  62         uint64_t heap_end;
  63         /* Only used by bootloader */
  64         uint64_t entry_point;
  65         uint64_t desc_vaddr;
  66         /* End of This block referenced by assembly code - do not change! */
  67         uint32_t exception_base_addr;
  68         uint32_t stack_size;
  69         uint32_t heap_size;
  70         /* Argc count for application. */
  71         uint32_t argc;
  72         uint32_t argv[OCTEON_ARGV_MAX_ARGS];
  73
  74 #define  BOOT_FLAG_INIT_CORE            (1 << 0)
  75 #define  OCTEON_BL_FLAG_DEBUG           (1 << 1)
  76 #define  OCTEON_BL_FLAG_NO_MAGIC        (1 << 2)
  77         /* If set, use uart1 for console */
  78 #define  OCTEON_BL_FLAG_CONSOLE_UART1   (1 << 3)
  79         /* If set, use PCI console */
  80 #define  OCTEON_BL_FLAG_CONSOLE_PCI     (1 << 4)
  81         /* Call exit on break on serial port */
  82 #define  OCTEON_BL_FLAG_BREAK           (1 << 5)
  83
  84         uint32_t flags;
  85         uint32_t core_mask;
  86         /* DRAM size in megabyes. */
  87         uint32_t dram_size;
  88         /* physical address of free memory descriptor block. */
  89         uint32_t phy_mem_desc_addr;
  90         /* used to pass flags from app to debugger. */
  91         uint32_t debugger_flags_base_addr;
  92         /* CPU clock speed, in hz. */
  93         uint32_t eclock_hz;
  94         /* DRAM clock speed, in hz. */
  95         uint32_t dclock_hz;
  96         /* SPI4 clock in hz. */
  97         uint32_t spi_clock_hz;
  98         uint16_t board_type;
  99         uint8_t board_rev_major;
 100         uint8_t board_rev_minor;
 101         uint16_t chip_type;
 102         uint8_t chip_rev_major;
 103         uint8_t chip_rev_minor;
 104         char board_serial_number[OCTOEN_SERIAL_LEN];
 105         uint8_t mac_addr_base[6];
 106         uint8_t mac_addr_count;
 107         uint64_t cvmx_desc_vaddr;
 108 };
 109
 110 union octeon_cvmemctl {
 111         uint64_t u64;
 112         struct {
 113                 /* RO 1 = BIST fail, 0 = BIST pass */
 114                 uint64_t tlbbist:1;
 115                 /* RO 1 = BIST fail, 0 = BIST pass */
 116                 uint64_t l1cbist:1;
 117                 /* RO 1 = BIST fail, 0 = BIST pass */
 118                 uint64_t l1dbist:1;
 119                 /* RO 1 = BIST fail, 0 = BIST pass */
 120                 uint64_t dcmbist:1;
 121                 /* RO 1 = BIST fail, 0 = BIST pass */
 122                 uint64_t ptgbist:1;
 123                 /* RO 1 = BIST fail, 0 = BIST pass */
 124                 uint64_t wbfbist:1;
 125                 /* Reserved */
 126                 uint64_t reserved:22;
 127                 /* R/W If set, marked write-buffer entries time out
 128                  * the same as as other entries; if clear, marked
 129                  * write-buffer entries use the maximum timeout. */
 130                 uint64_t dismarkwblongto:1;
 131                 /* R/W If set, a merged store does not clear the
 132                  * write-buffer entry timeout state. */
 133                 uint64_t dismrgclrwbto:1;
 134                 /* R/W Two bits that are the MSBs of the resultant
 135                  * CVMSEG LM word location for an IOBDMA. The other 8
 136                  * bits come from the SCRADDR field of the IOBDMA. */
 137                 uint64_t iobdmascrmsb:2;
 138                 /* R/W If set, SYNCWS and SYNCS only order marked
 139                  * stores; if clear, SYNCWS and SYNCS only order
 140                  * unmarked stores. SYNCWSMARKED has no effect when
 141                  * DISSYNCWS is set. */
 142                 uint64_t syncwsmarked:1;
 143                 /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as
 144                  * SYNC. */
 145                 uint64_t dissyncws:1;
 146                 /* R/W If set, no stall happens on write buffer
 147                  * full. */
 148                 uint64_t diswbfst:1;
 149                 /* R/W If set (and SX set), supervisor-level
 150                  * loads/stores can use XKPHYS addresses with
 151                  * VA<48>==0 */
 152                 uint64_t xkmemenas:1;
 153                 /* R/W If set (and UX set), user-level loads/stores
 154                  * can use XKPHYS addresses with VA<48>==0 */
 155                 uint64_t xkmemenau:1;
 156                 /* R/W If set (and SX set), supervisor-level
 157                  * loads/stores can use XKPHYS addresses with
 158                  * VA<48>==1 */
 159                 uint64_t xkioenas:1;
 160                 /* R/W If set (and UX set), user-level loads/stores
 161                  * can use XKPHYS addresses with VA<48>==1 */
 162                 uint64_t xkioenau:1;
 163                 /* R/W If set, all stores act as SYNCW (NOMERGE must
 164                  * be set when this is set) RW, reset to 0. */
 165                 uint64_t allsyncw:1;
 166                 /* R/W If set, no stores merge, and all stores reach
 167                  * the coherent bus in order. */
 168                 uint64_t nomerge:1;
 169                 /* R/W Selects the bit in the counter used for DID
 170                  * time-outs 0 = 231, 1 = 230, 2 = 229, 3 =
 171                  * 214. Actual time-out is between 1x and 2x this
 172                  * interval. For example, with DIDTTO=3, expiration
 173                  * interval is between 16K and 32K. */
 174                 uint64_t didtto:2;
 175                 /* R/W If set, the (mem) CSR clock never turns off. */
 176                 uint64_t csrckalwys:1;
 177                 /* R/W If set, mclk never turns off. */
 178                 uint64_t mclkalwys:1;
 179                 /* R/W Selects the bit in the counter used for write
 180                  * buffer flush time-outs (WBFLT+11) is the bit
 181                  * position in an internal counter used to determine
 182                  * expiration. The write buffer expires between 1x and
 183                  * 2x this interval. For example, with WBFLT = 0, a
 184                  * write buffer expires between 2K and 4K cycles after
 185                  * the write buffer entry is allocated. */
 186                 uint64_t wbfltime:3;
 187                 /* R/W If set, do not put Istream in the L2 cache. */
 188                 uint64_t istrnol2:1;
 189                 /* R/W The write buffer threshold. */
 190                 uint64_t wbthresh:4;
 191                 /* Reserved */
 192                 uint64_t reserved2:2;
 193                 /* R/W If set, CVMSEG is available for loads/stores in
 194                  * kernel/debug mode. */
 195                 uint64_t cvmsegenak:1;
 196                 /* R/W If set, CVMSEG is available for loads/stores in
 197                  * supervisor mode. */
 198                 uint64_t cvmsegenas:1;
 199                 /* R/W If set, CVMSEG is available for loads/stores in
 200                  * user mode. */
 201                 uint64_t cvmsegenau:1;
 202                 /* R/W Size of local memory in cache blocks, 54 (6912
 203                  * bytes) is max legal value. */
 204                 uint64_t lmemsz:6;
 205         } s;
 206 };
 207
 208 struct octeon_cf_data {
 209         unsigned long   base_region_bias;
 210         unsigned int    base_region;    /* The chip select region used by CF */
 211         int             is16bit;        /* 0 - 8bit, !0 - 16bit */
 212         int             dma_engine;     /* -1 for no DMA */
 213 };
 214
 215 extern void octeon_write_lcd(const char *s);
 216 extern void octeon_check_cpu_bist(void);
 217 extern int octeon_get_boot_debug_flag(void);
 218 extern int octeon_get_boot_uart(void);
 219
 220 struct uart_port;
 221 extern unsigned int octeon_serial_in(struct uart_port *, int);
 222 extern void octeon_serial_out(struct uart_port *, int, int);
 223
 224 /**
 225  * Write a 32bit value to the Octeon NPI register space
 226  *
 227  * @address: Address to write to
 228  * @val:     Value to write
 229  */
 230 static inline void octeon_npi_write32(uint64_t address, uint32_t val)
 231 {
 232         cvmx_write64_uint32(address ^ 4, val);
 233         cvmx_read64_uint32(address ^ 4);
 234 }
 235
 236
 237 /**
 238  * Read a 32bit value from the Octeon NPI register space
 239  *
 240  * @address: Address to read
 241  * Returns The result
 242  */
 243 static inline uint32_t octeon_npi_read32(uint64_t address)
 244 {
 245         return cvmx_read64_uint32(address ^ 4);
 246 }
 247
 248 extern struct cvmx_bootinfo *octeon_bootinfo;
 249
 250 #endif /* __ASM_OCTEON_OCTEON_H */