arch/mips/loongson/fuloong-2e/irq.c

   1 /*
   2  * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology
   3  * Author: Fuxin Zhang, zhangfx@lemote.com
   4  *
   5  *  This program is free software; you can redistribute  it and/or modify it
   6  *  under  the terms of  the GNU General  Public License as published by the
   7  *  Free Software Foundation;  either version 2 of the  License, or (at your
   8  *  option) any later version.
   9  */
  10 #include <linux/interrupt.h>
  11
  12 #include <asm/irq_cpu.h>
  13 #include <asm/i8259.h>
  14
  15 #include <loongson.h>
  16
  17 static void i8259_irqdispatch(void)
  18 {
  19         int irq;
  20
  21         irq = i8259_irq();
  22         if (irq >= 0)
  23                 do_IRQ(irq);
  24         else
  25                 spurious_interrupt();
  26 }
  27
  28 asmlinkage void mach_irq_dispatch(unsigned int pending)
  29 {
  30         if (pending & CAUSEF_IP7)
  31                 do_IRQ(MIPS_CPU_IRQ_BASE + 7);
  32         else if (pending & CAUSEF_IP6) /* perf counter loverflow */
  33                 do_IRQ(LOONGSON2_PERFCNT_IRQ);
  34         else if (pending & CAUSEF_IP5)
  35                 i8259_irqdispatch();
  36         else if (pending & CAUSEF_IP2)
  37                 bonito_irqdispatch();
  38         else
  39                 spurious_interrupt();
  40 }
  41
  42 static struct irqaction cascade_irqaction = {
  43         .handler = no_action,
  44         .name = "cascade",
  45 };
  46
  47 void __init set_irq_trigger_mode(void)
  48 {
  49         /* most bonito irq should be level triggered */
  50         BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR |
  51             BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES;
  52 }
  53
  54 void __init mach_init_irq(void)
  55 {
  56         /* init all controller
  57          *   0-15         ------> i8259 interrupt
  58          *   16-23        ------> mips cpu interrupt
  59          *   32-63        ------> bonito irq
  60          */
  61
  62         /* Sets the first-level interrupt dispatcher. */
  63         mips_cpu_irq_init();
  64         init_i8259_irqs();
  65         bonito_irq_init();
  66
  67         /* bonito irq at IP2 */
  68         setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction);
  69         /* 8259 irq at IP5 */
  70         setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction);
  71 }