arch/powerpc/platforms/86xx/mpc8610_hpcd.c

   1 /*
   2  * MPC8610 HPCD board specific routines
   3  *
   4  * Initial author: Xianghua Xiao <x.xiao@freescale.com>
   5  * Recode: Jason Jin <jason.jin@freescale.com>
   6  *         York Sun <yorksun@freescale.com>
   7  *
   8  * Rewrite the interrupt routing. remove the 8259PIC support,
   9  * All the integrated device in ULI use sideband interrupt.
  10  *
  11  * Copyright 2008 Freescale Semiconductor Inc.
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  */
  18
  19 #include <linux/stddef.h>
  20 #include <linux/kernel.h>
  21 #include <linux/pci.h>
  22 #include <linux/kdev_t.h>
  23 #include <linux/delay.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/of.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/time.h>
  29 #include <asm/machdep.h>
  30 #include <asm/pci-bridge.h>
  31 #include <asm/prom.h>
  32 #include <mm/mmu_decl.h>
  33 #include <asm/udbg.h>
  34
  35 #include <asm/mpic.h>
  36
  37 #include <linux/of_platform.h>
  38 #include <sysdev/fsl_pci.h>
  39 #include <sysdev/fsl_soc.h>
  40 #include <sysdev/simple_gpio.h>
  41
  42 #include "mpc86xx.h"
  43
  44 static unsigned char *pixis_bdcfg0, *pixis_arch;
  45
  46 static struct of_device_id __initdata mpc8610_ids[] = {
  47         { .compatible = "fsl,mpc8610-immr", },
  48         { .compatible = "simple-bus", },
  49         { .compatible = "gianfar", },
  50         {}
  51 };
  52
  53 static int __init mpc8610_declare_of_platform_devices(void)
  54 {
  55         /* Firstly, register PIXIS GPIOs. */
  56         simple_gpiochip_init("fsl,fpga-pixis-gpio-bank");
  57
  58         /* Without this call, the SSI device driver won't get probed. */
  59         of_platform_bus_probe(NULL, mpc8610_ids, NULL);
  60
  61         return 0;
  62 }
  63 machine_device_initcall(mpc86xx_hpcd, mpc8610_declare_of_platform_devices);
  64
  65 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
  66
  67 static u32 get_busfreq(void)
  68 {
  69         struct device_node *node;
  70
  71         u32 fs_busfreq = 0;
  72         node = of_find_node_by_type(NULL, "cpu");
  73         if (node) {
  74                 unsigned int size;
  75                 const unsigned int *prop =
  76                         of_get_property(node, "bus-frequency", &size);
  77                 if (prop)
  78                         fs_busfreq = *prop;
  79                 of_node_put(node);
  80         };
  81         return fs_busfreq;
  82 }
  83
  84 unsigned int mpc8610hpcd_get_pixel_format(unsigned int bits_per_pixel,
  85                                                 int monitor_port)
  86 {
  87         static const unsigned long pixelformat[][3] = {
  88                 {0x88882317, 0x88083218, 0x65052119},
  89                 {0x88883316, 0x88082219, 0x65053118},
  90         };
  91         unsigned int pix_fmt, arch_monitor;
  92
  93         arch_monitor = ((*pixis_arch == 0x01) && (monitor_port == 0))? 0 : 1;
  94                 /* DVI port for board version 0x01 */
  95
  96         if (bits_per_pixel == 32)
  97                 pix_fmt = pixelformat[arch_monitor][0];
  98         else if (bits_per_pixel == 24)
  99                 pix_fmt = pixelformat[arch_monitor][1];
 100         else if (bits_per_pixel == 16)
 101                 pix_fmt = pixelformat[arch_monitor][2];
 102         else
 103                 pix_fmt = pixelformat[1][0];
 104
 105         return pix_fmt;
 106 }
 107
 108 void mpc8610hpcd_set_gamma_table(int monitor_port, char *gamma_table_base)
 109 {
 110         int i;
 111         if (monitor_port == 2) {                /* dual link LVDS */
 112                 for (i = 0; i < 256*3; i++)
 113                         gamma_table_base[i] = (gamma_table_base[i] << 2) |
 114                                          ((gamma_table_base[i] >> 6) & 0x03);
 115         }
 116 }
 117
 118 #define PX_BRDCFG0_DVISEL       (1 << 3)
 119 #define PX_BRDCFG0_DLINK        (1 << 4)
 120 #define PX_BRDCFG0_DIU_MASK     (PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK)
 121
 122 void mpc8610hpcd_set_monitor_port(int monitor_port)
 123 {
 124         static const u8 bdcfg[] = {
 125                 PX_BRDCFG0_DVISEL | PX_BRDCFG0_DLINK,
 126                 PX_BRDCFG0_DLINK,
 127                 0,
 128         };
 129
 130         if (monitor_port < 3)
 131                 clrsetbits_8(pixis_bdcfg0, PX_BRDCFG0_DIU_MASK,
 132                              bdcfg[monitor_port]);
 133 }
 134
 135 void mpc8610hpcd_set_pixel_clock(unsigned int pixclock)
 136 {
 137         u32 __iomem *clkdvdr;
 138         u32 temp;
 139         /* variables for pixel clock calcs */
 140         ulong  bestval, bestfreq, speed_ccb, minpixclock, maxpixclock;
 141         ulong pixval;
 142         long err;
 143         int i;
 144
 145         clkdvdr = ioremap(get_immrbase() + 0xe0800, sizeof(u32));
 146         if (!clkdvdr) {
 147                 printk(KERN_ERR "Err: can't map clock divider register!\n");
 148                 return;
 149         }
 150
 151         /* Pixel Clock configuration */
 152         pr_debug("DIU: Bus Frequency = %d\n", get_busfreq());
 153         speed_ccb = get_busfreq();
 154
 155         /* Calculate the pixel clock with the smallest error */
 156         /* calculate the following in steps to avoid overflow */
 157         pr_debug("DIU pixclock in ps - %d\n", pixclock);
 158         temp = 1000000000/pixclock;
 159         temp *= 1000;
 160         pixclock = temp;
 161         pr_debug("DIU pixclock freq - %u\n", pixclock);
 162
 163         temp = pixclock * 5 / 100;
 164         pr_debug("deviation = %d\n", temp);
 165         minpixclock = pixclock - temp;
 166         maxpixclock = pixclock + temp;
 167         pr_debug("DIU minpixclock - %lu\n", minpixclock);
 168         pr_debug("DIU maxpixclock - %lu\n", maxpixclock);
 169         pixval = speed_ccb/pixclock;
 170         pr_debug("DIU pixval = %lu\n", pixval);
 171
 172         err = 100000000;
 173         bestval = pixval;
 174         pr_debug("DIU bestval = %lu\n", bestval);
 175
 176         bestfreq = 0;
 177         for (i = -1; i <= 1; i++) {
 178                 temp = speed_ccb / ((pixval+i) + 1);
 179                 pr_debug("DIU test pixval i= %d, pixval=%lu, temp freq. = %u\n",
 180                                                         i, pixval, temp);
 181                 if ((temp < minpixclock) || (temp > maxpixclock))
 182                         pr_debug("DIU exceeds monitor range (%lu to %lu)\n",
 183                                 minpixclock, maxpixclock);
 184                 else if (abs(temp - pixclock) < err) {
 185                   pr_debug("Entered the else if block %d\n", i);
 186                         err = abs(temp - pixclock);
 187                         bestval = pixval+i;
 188                         bestfreq = temp;
 189                 }
 190         }
 191
 192         pr_debug("DIU chose = %lx\n", bestval);
 193         pr_debug("DIU error = %ld\n NomPixClk ", err);
 194         pr_debug("DIU: Best Freq = %lx\n", bestfreq);
 195         /* Modify PXCLK in GUTS CLKDVDR */
 196         pr_debug("DIU: Current value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 197         temp = (*clkdvdr) & 0x2000FFFF;
 198         *clkdvdr = temp;                /* turn off clock */
 199         *clkdvdr = temp | 0x80000000 | (((bestval) & 0x1F) << 16);
 200         pr_debug("DIU: Modified value of CLKDVDR = 0x%08x\n", (*clkdvdr));
 201         iounmap(clkdvdr);
 202 }
 203
 204 ssize_t mpc8610hpcd_show_monitor_port(int monitor_port, char *buf)
 205 {
 206         return snprintf(buf, PAGE_SIZE,
 207                         "%c0 - DVI\n"
 208                         "%c1 - Single link LVDS\n"
 209                         "%c2 - Dual link LVDS\n",
 210                         monitor_port == 0 ? '*' : ' ',
 211                         monitor_port == 1 ? '*' : ' ',
 212                         monitor_port == 2 ? '*' : ' ');
 213 }
 214
 215 int mpc8610hpcd_set_sysfs_monitor_port(int val)
 216 {
 217         return val < 3 ? val : 0;
 218 }
 219
 220 #endif
 221
 222 static void __init mpc86xx_hpcd_setup_arch(void)
 223 {
 224         struct resource r;
 225         struct device_node *np;
 226         unsigned char *pixis;
 227
 228         if (ppc_md.progress)
 229                 ppc_md.progress("mpc86xx_hpcd_setup_arch()", 0);
 230
 231 #ifdef CONFIG_PCI
 232         for_each_node_by_type(np, "pci") {
 233                 if (of_device_is_compatible(np, "fsl,mpc8610-pci")
 234                     || of_device_is_compatible(np, "fsl,mpc8641-pcie")) {
 235                         struct resource rsrc;
 236                         of_address_to_resource(np, 0, &rsrc);
 237                         if ((rsrc.start & 0xfffff) == 0xa000)
 238                                 fsl_add_bridge(np, 1);
 239                         else
 240                                 fsl_add_bridge(np, 0);
 241                 }
 242         }
 243 #endif
 244 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 245         diu_ops.get_pixel_format        = mpc8610hpcd_get_pixel_format;
 246         diu_ops.set_gamma_table         = mpc8610hpcd_set_gamma_table;
 247         diu_ops.set_monitor_port        = mpc8610hpcd_set_monitor_port;
 248         diu_ops.set_pixel_clock         = mpc8610hpcd_set_pixel_clock;
 249         diu_ops.show_monitor_port       = mpc8610hpcd_show_monitor_port;
 250         diu_ops.set_sysfs_monitor_port  = mpc8610hpcd_set_sysfs_monitor_port;
 251 #endif
 252
 253         np = of_find_compatible_node(NULL, NULL, "fsl,fpga-pixis");
 254         if (np) {
 255                 of_address_to_resource(np, 0, &r);
 256                 of_node_put(np);
 257                 pixis = ioremap(r.start, 32);
 258                 if (!pixis) {
 259                         printk(KERN_ERR "Err: can't map FPGA cfg register!\n");
 260                         return;
 261                 }
 262                 pixis_bdcfg0 = pixis + 8;
 263                 pixis_arch = pixis + 1;
 264         } else
 265                 printk(KERN_ERR "Err: "
 266                                 "can't find device node 'fsl,fpga-pixis'\n");
 267
 268         printk("MPC86xx HPCD board from Freescale Semiconductor\n");
 269 }
 270
 271 /*
 272  * Called very early, device-tree isn't unflattened
 273  */
 274 static int __init mpc86xx_hpcd_probe(void)
 275 {
 276         unsigned long root = of_get_flat_dt_root();
 277
 278         if (of_flat_dt_is_compatible(root, "fsl,MPC8610HPCD"))
 279                 return 1;       /* Looks good */
 280
 281         return 0;
 282 }
 283
 284 static long __init mpc86xx_time_init(void)
 285 {
 286         unsigned int temp;
 287
 288         /* Set the time base to zero */
 289         mtspr(SPRN_TBWL, 0);
 290         mtspr(SPRN_TBWU, 0);
 291
 292         temp = mfspr(SPRN_HID0);
 293         temp |= HID0_TBEN;
 294         mtspr(SPRN_HID0, temp);
 295         asm volatile("isync");
 296
 297         return 0;
 298 }
 299
 300 define_machine(mpc86xx_hpcd) {
 301         .name                   = "MPC86xx HPCD",
 302         .probe                  = mpc86xx_hpcd_probe,
 303         .setup_arch             = mpc86xx_hpcd_setup_arch,
 304         .init_IRQ               = mpc86xx_init_irq,
 305         .get_irq                = mpic_get_irq,
 306         .restart                = fsl_rstcr_restart,
 307         .time_init              = mpc86xx_time_init,
 308         .calibrate_decr         = generic_calibrate_decr,
 309         .progress               = udbg_progress,
 310         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
 311 };