arch/powerpc/platforms/cell/spu_priv1_mmio.c

   1 /*
   2  * spu hypervisor abstraction for direct hardware access.
   3  *
   4  *  (C) Copyright IBM Deutschland Entwicklung GmbH 2005
   5  *  Copyright 2006 Sony Corp.
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License as published by
   9  *  the Free Software Foundation; version 2 of the License.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 #include <linux/interrupt.h>
  22 #include <linux/list.h>
  23 #include <linux/module.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/wait.h>
  27 #include <linux/mm.h>
  28 #include <linux/io.h>
  29 #include <linux/mutex.h>
  30 #include <linux/device.h>
  31 #include <linux/sched.h>
  32
  33 #include <asm/spu.h>
  34 #include <asm/spu_priv1.h>
  35 #include <asm/firmware.h>
  36 #include <asm/prom.h>
  37
  38 #include "interrupt.h"
  39 #include "spu_priv1_mmio.h"
  40
  41 static void int_mask_and(struct spu *spu, int class, u64 mask)
  42 {
  43         u64 old_mask;
  44
  45         old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
  46         out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
  47 }
  48
  49 static void int_mask_or(struct spu *spu, int class, u64 mask)
  50 {
  51         u64 old_mask;
  52
  53         old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
  54         out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
  55 }
  56
  57 static void int_mask_set(struct spu *spu, int class, u64 mask)
  58 {
  59         out_be64(&spu->priv1->int_mask_RW[class], mask);
  60 }
  61
  62 static u64 int_mask_get(struct spu *spu, int class)
  63 {
  64         return in_be64(&spu->priv1->int_mask_RW[class]);
  65 }
  66
  67 static void int_stat_clear(struct spu *spu, int class, u64 stat)
  68 {
  69         out_be64(&spu->priv1->int_stat_RW[class], stat);
  70 }
  71
  72 static u64 int_stat_get(struct spu *spu, int class)
  73 {
  74         return in_be64(&spu->priv1->int_stat_RW[class]);
  75 }
  76
  77 static void cpu_affinity_set(struct spu *spu, int cpu)
  78 {
  79         u64 target;
  80         u64 route;
  81
  82         if (nr_cpus_node(spu->node)) {
  83                 const struct cpumask *spumask = cpumask_of_node(spu->node),
  84                         *cpumask = cpumask_of_node(cpu_to_node(cpu));
  85
  86                 if (!cpumask_intersects(spumask, cpumask))
  87                         return;
  88         }
  89
  90         target = iic_get_target_id(cpu);
  91         route = target << 48 | target << 32 | target << 16;
  92         out_be64(&spu->priv1->int_route_RW, route);
  93 }
  94
  95 static u64 mfc_dar_get(struct spu *spu)
  96 {
  97         return in_be64(&spu->priv1->mfc_dar_RW);
  98 }
  99
 100 static u64 mfc_dsisr_get(struct spu *spu)
 101 {
 102         return in_be64(&spu->priv1->mfc_dsisr_RW);
 103 }
 104
 105 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
 106 {
 107         out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
 108 }
 109
 110 static void mfc_sdr_setup(struct spu *spu)
 111 {
 112         out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
 113 }
 114
 115 static void mfc_sr1_set(struct spu *spu, u64 sr1)
 116 {
 117         out_be64(&spu->priv1->mfc_sr1_RW, sr1);
 118 }
 119
 120 static u64 mfc_sr1_get(struct spu *spu)
 121 {
 122         return in_be64(&spu->priv1->mfc_sr1_RW);
 123 }
 124
 125 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
 126 {
 127         out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
 128 }
 129
 130 static u64 mfc_tclass_id_get(struct spu *spu)
 131 {
 132         return in_be64(&spu->priv1->mfc_tclass_id_RW);
 133 }
 134
 135 static void tlb_invalidate(struct spu *spu)
 136 {
 137         out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
 138 }
 139
 140 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
 141 {
 142         out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
 143 }
 144
 145 static u64 resource_allocation_groupID_get(struct spu *spu)
 146 {
 147         return in_be64(&spu->priv1->resource_allocation_groupID_RW);
 148 }
 149
 150 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
 151 {
 152         out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
 153 }
 154
 155 static u64 resource_allocation_enable_get(struct spu *spu)
 156 {
 157         return in_be64(&spu->priv1->resource_allocation_enable_RW);
 158 }
 159
 160 const struct spu_priv1_ops spu_priv1_mmio_ops =
 161 {
 162         .int_mask_and = int_mask_and,
 163         .int_mask_or = int_mask_or,
 164         .int_mask_set = int_mask_set,
 165         .int_mask_get = int_mask_get,
 166         .int_stat_clear = int_stat_clear,
 167         .int_stat_get = int_stat_get,
 168         .cpu_affinity_set = cpu_affinity_set,
 169         .mfc_dar_get = mfc_dar_get,
 170         .mfc_dsisr_get = mfc_dsisr_get,
 171         .mfc_dsisr_set = mfc_dsisr_set,
 172         .mfc_sdr_setup = mfc_sdr_setup,
 173         .mfc_sr1_set = mfc_sr1_set,
 174         .mfc_sr1_get = mfc_sr1_get,
 175         .mfc_tclass_id_set = mfc_tclass_id_set,
 176         .mfc_tclass_id_get = mfc_tclass_id_get,
 177         .tlb_invalidate = tlb_invalidate,
 178         .resource_allocation_groupID_set = resource_allocation_groupID_set,
 179         .resource_allocation_groupID_get = resource_allocation_groupID_get,
 180         .resource_allocation_enable_set = resource_allocation_enable_set,
 181         .resource_allocation_enable_get = resource_allocation_enable_get,
 182 };