arch/x86/include/asm/i387.h

   1 /*
   2  * Copyright (C) 1994 Linus Torvalds
   3  *
   4  * Pentium III FXSR, SSE support
   5  * General FPU state handling cleanups
   6  *      Gareth Hughes <gareth@valinux.com>, May 2000
   7  * x86-64 work by Andi Kleen 2002
   8  */
   9
  10 #ifndef _ASM_X86_I387_H
  11 #define _ASM_X86_I387_H
  12
  13 #include <linux/sched.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/regset.h>
  16 #include <linux/hardirq.h>
  17 #include <asm/asm.h>
  18 #include <asm/processor.h>
  19 #include <asm/sigcontext.h>
  20 #include <asm/user.h>
  21 #include <asm/uaccess.h>
  22 #include <asm/xsave.h>
  23
  24 extern unsigned int sig_xstate_size;
  25 extern void fpu_init(void);
  26 extern void mxcsr_feature_mask_init(void);
  27 extern int init_fpu(struct task_struct *child);
  28 extern asmlinkage void math_state_restore(void);
  29 extern void __math_state_restore(void);
  30 extern void init_thread_xstate(void);
  31 extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
  32
  33 extern user_regset_active_fn fpregs_active, xfpregs_active;
  34 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
  35 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
  36
  37 extern struct _fpx_sw_bytes fx_sw_reserved;
  38 #ifdef CONFIG_IA32_EMULATION
  39 extern unsigned int sig_xstate_ia32_size;
  40 extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
  41 struct _fpstate_ia32;
  42 struct _xstate_ia32;
  43 extern int save_i387_xstate_ia32(void __user *buf);
  44 extern int restore_i387_xstate_ia32(void __user *buf);
  45 #endif
  46
  47 #define X87_FSW_ES (1 << 7)     /* Exception Summary */
  48
  49 #ifdef CONFIG_X86_64
  50
  51 /* Ignore delayed exceptions from user space */
  52 static inline void tolerant_fwait(void)
  53 {
  54         asm volatile("1: fwait\n"
  55                      "2:\n"
  56                      _ASM_EXTABLE(1b, 2b));
  57 }
  58
  59 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
  60 {
  61         int err;
  62
  63         asm volatile("1:  rex64/fxrstor (%[fx])\n\t"
  64                      "2:\n"
  65                      ".section .fixup,\"ax\"\n"
  66                      "3:  movl $-1,%[err]\n"
  67                      "    jmp  2b\n"
  68                      ".previous\n"
  69                      _ASM_EXTABLE(1b, 3b)
  70                      : [err] "=r" (err)
  71 #if 0 /* See comment in fxsave() below. */
  72                      : [fx] "r" (fx), "m" (*fx), "0" (0));
  73 #else
  74                      : [fx] "cdaSDb" (fx), "m" (*fx), "0" (0));
  75 #endif
  76         return err;
  77 }
  78
  79 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
  80    is pending. Clear the x87 state here by setting it to fixed
  81    values. The kernel data segment can be sometimes 0 and sometimes
  82    new user value. Both should be ok.
  83    Use the PDA as safe address because it should be already in L1. */
  84 static inline void clear_fpu_state(struct task_struct *tsk)
  85 {
  86         struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
  87         struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
  88
  89         /*
  90          * xsave header may indicate the init state of the FP.
  91          */
  92         if ((task_thread_info(tsk)->status & TS_XSAVE) &&
  93             !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
  94                 return;
  95
  96         if (unlikely(fx->swd & X87_FSW_ES))
  97                 asm volatile("fnclex");
  98         alternative_input(ASM_NOP8 ASM_NOP2,
  99                           "    emms\n"          /* clear stack tags */
 100                           "    fildl %%gs:0",   /* load to clear state */
 101                           X86_FEATURE_FXSAVE_LEAK);
 102 }
 103
 104 static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
 105 {
 106         int err;
 107
 108         asm volatile("1:  rex64/fxsave (%[fx])\n\t"
 109                      "2:\n"
 110                      ".section .fixup,\"ax\"\n"
 111                      "3:  movl $-1,%[err]\n"
 112                      "    jmp  2b\n"
 113                      ".previous\n"
 114                      _ASM_EXTABLE(1b, 3b)
 115                      : [err] "=r" (err), "=m" (*fx)
 116 #if 0 /* See comment in fxsave() below. */
 117                      : [fx] "r" (fx), "0" (0));
 118 #else
 119                      : [fx] "cdaSDb" (fx), "0" (0));
 120 #endif
 121         if (unlikely(err) &&
 122             __clear_user(fx, sizeof(struct i387_fxsave_struct)))
 123                 err = -EFAULT;
 124         /* No need to clear here because the caller clears USED_MATH */
 125         return err;
 126 }
 127
 128 static inline void fxsave(struct task_struct *tsk)
 129 {
 130         /* Using "rex64; fxsave %0" is broken because, if the memory operand
 131            uses any extended registers for addressing, a second REX prefix
 132            will be generated (to the assembler, rex64 followed by semicolon
 133            is a separate instruction), and hence the 64-bitness is lost. */
 134 #if 0
 135         /* Using "fxsaveq %0" would be the ideal choice, but is only supported
 136            starting with gas 2.16. */
 137         __asm__ __volatile__("fxsaveq %0"
 138                              : "=m" (tsk->thread.xstate->fxsave));
 139 #elif 0
 140         /* Using, as a workaround, the properly prefixed form below isn't
 141            accepted by any binutils version so far released, complaining that
 142            the same type of prefix is used twice if an extended register is
 143            needed for addressing (fix submitted to mainline 2005-11-21). */
 144         __asm__ __volatile__("rex64/fxsave %0"
 145                              : "=m" (tsk->thread.xstate->fxsave));
 146 #else
 147         /* This, however, we can work around by forcing the compiler to select
 148            an addressing mode that doesn't require extended registers. */
 149         __asm__ __volatile__("rex64/fxsave (%1)"
 150                              : "=m" (tsk->thread.xstate->fxsave)
 151                              : "cdaSDb" (&tsk->thread.xstate->fxsave));
 152 #endif
 153 }
 154
 155 static inline void __save_init_fpu(struct task_struct *tsk)
 156 {
 157         if (task_thread_info(tsk)->status & TS_XSAVE)
 158                 xsave(tsk);
 159         else
 160                 fxsave(tsk);
 161
 162         clear_fpu_state(tsk);
 163         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 164 }
 165
 166 #else  /* CONFIG_X86_32 */
 167
 168 #ifdef CONFIG_MATH_EMULATION
 169 extern void finit_task(struct task_struct *tsk);
 170 #else
 171 static inline void finit_task(struct task_struct *tsk)
 172 {
 173 }
 174 #endif
 175
 176 static inline void tolerant_fwait(void)
 177 {
 178         asm volatile("fnclex ; fwait");
 179 }
 180
 181 /* perform fxrstor iff the processor has extended states, otherwise frstor */
 182 static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
 183 {
 184         /*
 185          * The "nop" is needed to make the instructions the same
 186          * length.
 187          */
 188         alternative_input(
 189                 "nop ; frstor %1",
 190                 "fxrstor %1",
 191                 X86_FEATURE_FXSR,
 192                 "m" (*fx));
 193
 194         return 0;
 195 }
 196
 197 /* We need a safe address that is cheap to find and that is already
 198    in L1 during context switch. The best choices are unfortunately
 199    different for UP and SMP */
 200 #ifdef CONFIG_SMP
 201 #define safe_address (__per_cpu_offset[0])
 202 #else
 203 #define safe_address (kstat_cpu(0).cpustat.user)
 204 #endif
 205
 206 /*
 207  * These must be called with preempt disabled
 208  */
 209 static inline void __save_init_fpu(struct task_struct *tsk)
 210 {
 211         if (task_thread_info(tsk)->status & TS_XSAVE) {
 212                 struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
 213                 struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
 214
 215                 xsave(tsk);
 216
 217                 /*
 218                  * xsave header may indicate the init state of the FP.
 219                  */
 220                 if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
 221                         goto end;
 222
 223                 if (unlikely(fx->swd & X87_FSW_ES))
 224                         asm volatile("fnclex");
 225
 226                 /*
 227                  * we can do a simple return here or be paranoid :)
 228                  */
 229                 goto clear_state;
 230         }
 231
 232         /* Use more nops than strictly needed in case the compiler
 233            varies code */
 234         alternative_input(
 235                 "fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
 236                 "fxsave %[fx]\n"
 237                 "bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
 238                 X86_FEATURE_FXSR,
 239                 [fx] "m" (tsk->thread.xstate->fxsave),
 240                 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
 241 clear_state:
 242         /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
 243            is pending.  Clear the x87 state here by setting it to fixed
 244            values. safe_address is a random variable that should be in L1 */
 245         alternative_input(
 246                 GENERIC_NOP8 GENERIC_NOP2,
 247                 "emms\n\t"              /* clear stack tags */
 248                 "fildl %[addr]",        /* set F?P to defined value */
 249                 X86_FEATURE_FXSAVE_LEAK,
 250                 [addr] "m" (safe_address));
 251 end:
 252         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 253 }
 254
 255 #endif  /* CONFIG_X86_64 */
 256
 257 static inline int restore_fpu_checking(struct task_struct *tsk)
 258 {
 259         if (task_thread_info(tsk)->status & TS_XSAVE)
 260                 return xrstor_checking(&tsk->thread.xstate->xsave);
 261         else
 262                 return fxrstor_checking(&tsk->thread.xstate->fxsave);
 263 }
 264
 265 /*
 266  * Signal frame handlers...
 267  */
 268 extern int save_i387_xstate(void __user *buf);
 269 extern int restore_i387_xstate(void __user *buf);
 270
 271 static inline void __unlazy_fpu(struct task_struct *tsk)
 272 {
 273         if (task_thread_info(tsk)->status & TS_USEDFPU) {
 274                 __save_init_fpu(tsk);
 275                 stts();
 276         } else
 277                 tsk->fpu_counter = 0;
 278 }
 279
 280 static inline void __clear_fpu(struct task_struct *tsk)
 281 {
 282         if (task_thread_info(tsk)->status & TS_USEDFPU) {
 283                 tolerant_fwait();
 284                 task_thread_info(tsk)->status &= ~TS_USEDFPU;
 285                 stts();
 286         }
 287 }
 288
 289 static inline void kernel_fpu_begin(void)
 290 {
 291         struct thread_info *me = current_thread_info();
 292         preempt_disable();
 293         if (me->status & TS_USEDFPU)
 294                 __save_init_fpu(me->task);
 295         else
 296                 clts();
 297 }
 298
 299 static inline void kernel_fpu_end(void)
 300 {
 301         stts();
 302         preempt_enable();
 303 }
 304
 305 static inline bool irq_fpu_usable(void)
 306 {
 307         struct pt_regs *regs;
 308
 309         return !in_interrupt() || !(regs = get_irq_regs()) || \
 310                 user_mode(regs) || (read_cr0() & X86_CR0_TS);
 311 }
 312
 313 /*
 314  * Some instructions like VIA's padlock instructions generate a spurious
 315  * DNA fault but don't modify SSE registers. And these instructions
 316  * get used from interrupt context as well. To prevent these kernel instructions
 317  * in interrupt context interacting wrongly with other user/kernel fpu usage, we
 318  * should use them only in the context of irq_ts_save/restore()
 319  */
 320 static inline int irq_ts_save(void)
 321 {
 322         /*
 323          * If in process context and not atomic, we can take a spurious DNA fault.
 324          * Otherwise, doing clts() in process context requires disabling preemption
 325          * or some heavy lifting like kernel_fpu_begin()
 326          */
 327         if (!in_atomic())
 328                 return 0;
 329
 330         if (read_cr0() & X86_CR0_TS) {
 331                 clts();
 332                 return 1;
 333         }
 334
 335         return 0;
 336 }
 337
 338 static inline void irq_ts_restore(int TS_state)
 339 {
 340         if (TS_state)
 341                 stts();
 342 }
 343
 344 #ifdef CONFIG_X86_64
 345
 346 static inline void save_init_fpu(struct task_struct *tsk)
 347 {
 348         __save_init_fpu(tsk);
 349         stts();
 350 }
 351
 352 #define unlazy_fpu      __unlazy_fpu
 353 #define clear_fpu       __clear_fpu
 354
 355 #else  /* CONFIG_X86_32 */
 356
 357 /*
 358  * These disable preemption on their own and are safe
 359  */
 360 static inline void save_init_fpu(struct task_struct *tsk)
 361 {
 362         preempt_disable();
 363         __save_init_fpu(tsk);
 364         stts();
 365         preempt_enable();
 366 }
 367
 368 static inline void unlazy_fpu(struct task_struct *tsk)
 369 {
 370         preempt_disable();
 371         __unlazy_fpu(tsk);
 372         preempt_enable();
 373 }
 374
 375 static inline void clear_fpu(struct task_struct *tsk)
 376 {
 377         preempt_disable();
 378         __clear_fpu(tsk);
 379         preempt_enable();
 380 }
 381
 382 #endif  /* CONFIG_X86_64 */
 383
 384 /*
 385  * i387 state interaction
 386  */
 387 static inline unsigned short get_fpu_cwd(struct task_struct *tsk)
 388 {
 389         if (cpu_has_fxsr) {
 390                 return tsk->thread.xstate->fxsave.cwd;
 391         } else {
 392                 return (unsigned short)tsk->thread.xstate->fsave.cwd;
 393         }
 394 }
 395
 396 static inline unsigned short get_fpu_swd(struct task_struct *tsk)
 397 {
 398         if (cpu_has_fxsr) {
 399                 return tsk->thread.xstate->fxsave.swd;
 400         } else {
 401                 return (unsigned short)tsk->thread.xstate->fsave.swd;
 402         }
 403 }
 404
 405 static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
 406 {
 407         if (cpu_has_xmm) {
 408                 return tsk->thread.xstate->fxsave.mxcsr;
 409         } else {
 410                 return MXCSR_DEFAULT;
 411         }
 412 }
 413
 414 #endif /* _ASM_X86_I387_H */