drivers/char/rio/rioboard.h

   1 /************************************************************************/
   2 /*                                                                      */
   3 /*      Title           :       RIO Host Card Hardware Definitions      */
   4 /*                                                                      */
   5 /*      Author          :       N.P.Vassallo                            */
   6 /*                                                                      */
   7 /*      Creation        :       26th April 1999                         */
   8 /*                                                                      */
   9 /*      Version         :       1.0.0                                   */
  10 /*                                                                      */
  11 /*      Copyright       :       (c) Specialix International Ltd. 1999   *
  12  *
  13  *      This program is free software; you can redistribute it and/or modify
  14  *      it under the terms of the GNU General Public License as published by
  15  *      the Free Software Foundation; either version 2 of the License, or
  16  *      (at your option) any later version.
  17  *
  18  *      This program is distributed in the hope that it will be useful,
  19  *      but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *      GNU General Public License for more details.
  22  *
  23  *      You should have received a copy of the GNU General Public License
  24  *      along with this program; if not, write to the Free Software
  25  *      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *                                                                      */
  27 /*      Description     :       Prototypes, structures and definitions  */
  28 /*                              describing the RIO board hardware       */
  29 /*                                                                      */
  30 /************************************************************************/
  31
  32 #ifndef _rioboard_h             /* If RIOBOARD.H not already defined */
  33 #define _rioboard_h    1
  34
  35 /*****************************************************************************
  36 ***********************                                ***********************
  37 ***********************   Hardware Control Registers   ***********************
  38 ***********************                                ***********************
  39 *****************************************************************************/
  40
  41 /* Hardware Registers... */
  42
  43 #define RIO_REG_BASE    0x7C00  /* Base of control registers */
  44
  45 #define RIO_CONFIG      RIO_REG_BASE + 0x0000   /* WRITE: Configuration Register */
  46 #define RIO_INTSET      RIO_REG_BASE + 0x0080   /* WRITE: Interrupt Set */
  47 #define RIO_RESET       RIO_REG_BASE + 0x0100   /* WRITE: Host Reset */
  48 #define RIO_INTRESET    RIO_REG_BASE + 0x0180   /* WRITE: Interrupt Reset */
  49
  50 #define RIO_VPD_ROM     RIO_REG_BASE + 0x0000   /* READ: Vital Product Data ROM */
  51 #define RIO_INTSTAT     RIO_REG_BASE + 0x0080   /* READ: Interrupt Status (Jet boards only) */
  52 #define RIO_RESETSTAT   RIO_REG_BASE + 0x0100   /* READ: Reset Status (Jet boards only) */
  53
  54 /* RIO_VPD_ROM definitions... */
  55 #define VPD_SLX_ID1     0x00    /* READ: Specialix Identifier #1 */
  56 #define VPD_SLX_ID2     0x01    /* READ: Specialix Identifier #2 */
  57 #define VPD_HW_REV      0x02    /* READ: Hardware Revision */
  58 #define VPD_HW_ASSEM    0x03    /* READ: Hardware Assembly Level */
  59 #define VPD_UNIQUEID4   0x04    /* READ: Unique Identifier #4 */
  60 #define VPD_UNIQUEID3   0x05    /* READ: Unique Identifier #3 */
  61 #define VPD_UNIQUEID2   0x06    /* READ: Unique Identifier #2 */
  62 #define VPD_UNIQUEID1   0x07    /* READ: Unique Identifier #1 */
  63 #define VPD_MANU_YEAR   0x08    /* READ: Year Of Manufacture (0 = 1970) */
  64 #define VPD_MANU_WEEK   0x09    /* READ: Week Of Manufacture (0 = week 1 Jan) */
  65 #define VPD_HWFEATURE1  0x0A    /* READ: Hardware Feature Byte 1 */
  66 #define VPD_HWFEATURE2  0x0B    /* READ: Hardware Feature Byte 2 */
  67 #define VPD_HWFEATURE3  0x0C    /* READ: Hardware Feature Byte 3 */
  68 #define VPD_HWFEATURE4  0x0D    /* READ: Hardware Feature Byte 4 */
  69 #define VPD_HWFEATURE5  0x0E    /* READ: Hardware Feature Byte 5 */
  70 #define VPD_OEMID       0x0F    /* READ: OEM Identifier */
  71 #define VPD_IDENT       0x10    /* READ: Identifier string (16 bytes) */
  72 #define VPD_IDENT_LEN   0x10
  73
  74 /* VPD ROM Definitions... */
  75 #define SLX_ID1         0x4D
  76 #define SLX_ID2         0x98
  77
  78 #define PRODUCT_ID(a)   ((a>>4)&0xF)    /* Use to obtain Product ID from VPD_UNIQUEID1 */
  79
  80 #define ID_SX_ISA       0x2
  81 #define ID_RIO_EISA     0x3
  82 #define ID_SX_PCI       0x5
  83 #define ID_SX_EISA      0x7
  84 #define ID_RIO_RTA16    0x9
  85 #define ID_RIO_ISA      0xA
  86 #define ID_RIO_MCA      0xB
  87 #define ID_RIO_SBUS     0xC
  88 #define ID_RIO_PCI      0xD
  89 #define ID_RIO_RTA8     0xE
  90
  91 /* Transputer bootstrap definitions... */
  92
  93 #define BOOTLOADADDR            (0x8000 - 6)
  94 #define BOOTINDICATE            (0x8000 - 2)
  95
  96 /* Firmware load position... */
  97
  98 #define FIRMWARELOADADDR        0x7C00  /* Firmware is loaded _before_ this address */
  99
 100 /*****************************************************************************
 101 *****************************                    *****************************
 102 *****************************   RIO (Rev1) ISA   *****************************
 103 *****************************                    *****************************
 104 *****************************************************************************/
 105
 106 /* Control Register Definitions... */
 107 #define RIO_ISA_IDENT   "JBJGPGGHINSMJPJR"
 108
 109 #define RIO_ISA_CFG_BOOTRAM     0x01    /* Boot from RAM, else Link */
 110 #define RIO_ISA_CFG_BUSENABLE   0x02    /* Enable processor bus */
 111 #define RIO_ISA_CFG_IRQMASK     0x30    /* Interrupt mask */
 112 #define   RIO_ISA_CFG_IRQ12     0x10    /* Interrupt Level 12 */
 113 #define   RIO_ISA_CFG_IRQ11     0x20    /* Interrupt Level 11 */
 114 #define   RIO_ISA_CFG_IRQ9      0x30    /* Interrupt Level 9 */
 115 #define RIO_ISA_CFG_LINK20      0x40    /* 20Mbps link, else 10Mbps */
 116 #define RIO_ISA_CFG_WAITSTATE0  0x80    /* 0 waitstates, else 1 */
 117
 118 /*****************************************************************************
 119 *****************************                    *****************************
 120 *****************************   RIO (Rev2) ISA   *****************************
 121 *****************************                    *****************************
 122 *****************************************************************************/
 123
 124 /* Control Register Definitions... */
 125 #define RIO_ISA2_IDENT  "JBJGPGGHINSMJPJR"
 126
 127 #define RIO_ISA2_CFG_BOOTRAM    0x01    /* Boot from RAM, else Link */
 128 #define RIO_ISA2_CFG_BUSENABLE  0x02    /* Enable processor bus */
 129 #define RIO_ISA2_CFG_INTENABLE  0x04    /* Interrupt enable, else disable */
 130 #define RIO_ISA2_CFG_16BIT      0x08    /* 16bit mode, else 8bit */
 131 #define RIO_ISA2_CFG_IRQMASK    0x30    /* Interrupt mask */
 132 #define   RIO_ISA2_CFG_IRQ15    0x00    /* Interrupt Level 15 */
 133 #define   RIO_ISA2_CFG_IRQ12    0x10    /* Interrupt Level 12 */
 134 #define   RIO_ISA2_CFG_IRQ11    0x20    /* Interrupt Level 11 */
 135 #define   RIO_ISA2_CFG_IRQ9     0x30    /* Interrupt Level 9 */
 136 #define RIO_ISA2_CFG_LINK20     0x40    /* 20Mbps link, else 10Mbps */
 137 #define RIO_ISA2_CFG_WAITSTATE0 0x80    /* 0 waitstates, else 1 */
 138
 139 /*****************************************************************************
 140 *****************************                   ******************************
 141 *****************************   RIO (Jet) ISA   ******************************
 142 *****************************                   ******************************
 143 *****************************************************************************/
 144
 145 /* Control Register Definitions... */
 146 #define RIO_ISA3_IDENT  "JET HOST BY KEV#"
 147
 148 #define RIO_ISA3_CFG_BUSENABLE  0x02    /* Enable processor bus */
 149 #define RIO_ISA3_CFG_INTENABLE  0x04    /* Interrupt enable, else disable */
 150 #define RIO_ISA32_CFG_IRQMASK   0xF30   /* Interrupt mask */
 151 #define   RIO_ISA3_CFG_IRQ15    0xF0    /* Interrupt Level 15 */
 152 #define   RIO_ISA3_CFG_IRQ12    0xC0    /* Interrupt Level 12 */
 153 #define   RIO_ISA3_CFG_IRQ11    0xB0    /* Interrupt Level 11 */
 154 #define   RIO_ISA3_CFG_IRQ10    0xA0    /* Interrupt Level 10 */
 155 #define   RIO_ISA3_CFG_IRQ9     0x90    /* Interrupt Level 9 */
 156
 157 /*****************************************************************************
 158 *********************************             ********************************
 159 *********************************   RIO MCA   ********************************
 160 *********************************             ********************************
 161 *****************************************************************************/
 162
 163 /* Control Register Definitions... */
 164 #define RIO_MCA_IDENT   "JBJGPGGHINSMJPJR"
 165
 166 #define RIO_MCA_CFG_BOOTRAM     0x01    /* Boot from RAM, else Link */
 167 #define RIO_MCA_CFG_BUSENABLE   0x02    /* Enable processor bus */
 168 #define RIO_MCA_CFG_LINK20      0x40    /* 20Mbps link, else 10Mbps */
 169
 170 /*****************************************************************************
 171 ********************************              ********************************
 172 ********************************   RIO EISA   ********************************
 173 ********************************              ********************************
 174 *****************************************************************************/
 175
 176 /* EISA Configuration Space Definitions... */
 177 #define EISA_PRODUCT_ID1        0xC80
 178 #define EISA_PRODUCT_ID2        0xC81
 179 #define EISA_PRODUCT_NUMBER     0xC82
 180 #define EISA_REVISION_NUMBER    0xC83
 181 #define EISA_CARD_ENABLE        0xC84
 182 #define EISA_VPD_UNIQUEID4      0xC88   /* READ: Unique Identifier #4 */
 183 #define EISA_VPD_UNIQUEID3      0xC8A   /* READ: Unique Identifier #3 */
 184 #define EISA_VPD_UNIQUEID2      0xC90   /* READ: Unique Identifier #2 */
 185 #define EISA_VPD_UNIQUEID1      0xC92   /* READ: Unique Identifier #1 */
 186 #define EISA_VPD_MANU_YEAR      0xC98   /* READ: Year Of Manufacture (0 = 1970) */
 187 #define EISA_VPD_MANU_WEEK      0xC9A   /* READ: Week Of Manufacture (0 = week 1 Jan) */
 188 #define EISA_MEM_ADDR_23_16     0xC00
 189 #define EISA_MEM_ADDR_31_24     0xC01
 190 #define EISA_RIO_CONFIG         0xC02   /* WRITE: Configuration Register */
 191 #define EISA_RIO_INTSET         0xC03   /* WRITE: Interrupt Set */
 192 #define EISA_RIO_INTRESET       0xC03   /* READ:  Interrupt Reset */
 193
 194 /* Control Register Definitions... */
 195 #define RIO_EISA_CFG_BOOTRAM    0x01    /* Boot from RAM, else Link */
 196 #define RIO_EISA_CFG_LINK20     0x02    /* 20Mbps link, else 10Mbps */
 197 #define RIO_EISA_CFG_BUSENABLE  0x04    /* Enable processor bus */
 198 #define RIO_EISA_CFG_PROCRUN    0x08    /* Processor running, else reset */
 199 #define RIO_EISA_CFG_IRQMASK    0xF0    /* Interrupt mask */
 200 #define   RIO_EISA_CFG_IRQ15    0xF0    /* Interrupt Level 15 */
 201 #define   RIO_EISA_CFG_IRQ14    0xE0    /* Interrupt Level 14 */
 202 #define   RIO_EISA_CFG_IRQ12    0xC0    /* Interrupt Level 12 */
 203 #define   RIO_EISA_CFG_IRQ11    0xB0    /* Interrupt Level 11 */
 204 #define   RIO_EISA_CFG_IRQ10    0xA0    /* Interrupt Level 10 */
 205 #define   RIO_EISA_CFG_IRQ9     0x90    /* Interrupt Level 9 */
 206 #define   RIO_EISA_CFG_IRQ7     0x70    /* Interrupt Level 7 */
 207 #define   RIO_EISA_CFG_IRQ6     0x60    /* Interrupt Level 6 */
 208 #define   RIO_EISA_CFG_IRQ5     0x50    /* Interrupt Level 5 */
 209 #define   RIO_EISA_CFG_IRQ4     0x40    /* Interrupt Level 4 */
 210 #define   RIO_EISA_CFG_IRQ3     0x30    /* Interrupt Level 3 */
 211
 212 /*****************************************************************************
 213 ********************************              ********************************
 214 ********************************   RIO SBus   ********************************
 215 ********************************              ********************************
 216 *****************************************************************************/
 217
 218 /* Control Register Definitions... */
 219 #define RIO_SBUS_IDENT  "JBPGK#\0\0\0\0\0\0\0\0\0\0"
 220
 221 #define RIO_SBUS_CFG_BOOTRAM    0x01    /* Boot from RAM, else Link */
 222 #define RIO_SBUS_CFG_BUSENABLE  0x02    /* Enable processor bus */
 223 #define RIO_SBUS_CFG_INTENABLE  0x04    /* Interrupt enable, else disable */
 224 #define RIO_SBUS_CFG_IRQMASK    0x38    /* Interrupt mask */
 225 #define   RIO_SBUS_CFG_IRQNONE  0x00    /* No Interrupt */
 226 #define   RIO_SBUS_CFG_IRQ7     0x38    /* Interrupt Level 7 */
 227 #define   RIO_SBUS_CFG_IRQ6     0x30    /* Interrupt Level 6 */
 228 #define   RIO_SBUS_CFG_IRQ5     0x28    /* Interrupt Level 5 */
 229 #define   RIO_SBUS_CFG_IRQ4     0x20    /* Interrupt Level 4 */
 230 #define   RIO_SBUS_CFG_IRQ3     0x18    /* Interrupt Level 3 */
 231 #define   RIO_SBUS_CFG_IRQ2     0x10    /* Interrupt Level 2 */
 232 #define   RIO_SBUS_CFG_IRQ1     0x08    /* Interrupt Level 1 */
 233 #define RIO_SBUS_CFG_LINK20     0x40    /* 20Mbps link, else 10Mbps */
 234 #define RIO_SBUS_CFG_PROC25     0x80    /* 25Mhz processor clock, else 20Mhz */
 235
 236 /*****************************************************************************
 237 *********************************             ********************************
 238 *********************************   RIO PCI   ********************************
 239 *********************************             ********************************
 240 *****************************************************************************/
 241
 242 /* Control Register Definitions... */
 243 #define RIO_PCI_IDENT   "ECDDPGJGJHJRGSK#"
 244
 245 #define RIO_PCI_CFG_BOOTRAM     0x01    /* Boot from RAM, else Link */
 246 #define RIO_PCI_CFG_BUSENABLE   0x02    /* Enable processor bus */
 247 #define RIO_PCI_CFG_INTENABLE   0x04    /* Interrupt enable, else disable */
 248 #define RIO_PCI_CFG_LINK20      0x40    /* 20Mbps link, else 10Mbps */
 249 #define RIO_PCI_CFG_PROC25      0x80    /* 25Mhz processor clock, else 20Mhz */
 250
 251 /* PCI Definitions... */
 252 #define SPX_VENDOR_ID           0x11CB  /* Assigned by the PCI SIG */
 253 #define SPX_DEVICE_ID           0x8000  /* RIO bridge boards */
 254 #define SPX_PLXDEVICE_ID        0x2000  /* PLX bridge boards */
 255 #define SPX_SUB_VENDOR_ID       SPX_VENDOR_ID   /* Same as vendor id */
 256 #define RIO_SUB_SYS_ID          0x0800  /* RIO PCI board */
 257
 258 /*****************************************************************************
 259 *****************************                   ******************************
 260 *****************************   RIO (Jet) PCI   ******************************
 261 *****************************                   ******************************
 262 *****************************************************************************/
 263
 264 /* Control Register Definitions... */
 265 #define RIO_PCI2_IDENT  "JET HOST BY KEV#"
 266
 267 #define RIO_PCI2_CFG_BUSENABLE  0x02    /* Enable processor bus */
 268 #define RIO_PCI2_CFG_INTENABLE  0x04    /* Interrupt enable, else disable */
 269
 270 /* PCI Definitions... */
 271 #define RIO2_SUB_SYS_ID         0x0100  /* RIO (Jet) PCI board */
 272
 273 #endif                                          /*_rioboard_h */
 274
 275 /* End of RIOBOARD.H */