| blob | 81308924859a2ebca4e5e45e889fe43e6f229bb8 |
1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __RS600D_H__
29 #define __RS600D_H__
31 /* Registers */
32 #define R_000040_GEN_INT_CNTL 0x000040
33 #define S_000040_DISPLAY_INT_STATUS(x) (((x) & 0x1) << 0)
34 #define G_000040_DISPLAY_INT_STATUS(x) (((x) >> 0) & 0x1)
35 #define C_000040_DISPLAY_INT_STATUS 0xFFFFFFFE
36 #define S_000040_DMA_VIPH0_INT_EN(x) (((x) & 0x1) << 12)
37 #define G_000040_DMA_VIPH0_INT_EN(x) (((x) >> 12) & 0x1)
38 #define C_000040_DMA_VIPH0_INT_EN 0xFFFFEFFF
39 #define S_000040_CRTC2_VSYNC(x) (((x) & 0x1) << 6)
40 #define G_000040_CRTC2_VSYNC(x) (((x) >> 6) & 0x1)
41 #define C_000040_CRTC2_VSYNC 0xFFFFFFBF
42 #define S_000040_SNAPSHOT2(x) (((x) & 0x1) << 7)
43 #define G_000040_SNAPSHOT2(x) (((x) >> 7) & 0x1)
44 #define C_000040_SNAPSHOT2 0xFFFFFF7F
45 #define S_000040_CRTC2_VBLANK(x) (((x) & 0x1) << 9)
46 #define G_000040_CRTC2_VBLANK(x) (((x) >> 9) & 0x1)
47 #define C_000040_CRTC2_VBLANK 0xFFFFFDFF
48 #define S_000040_FP2_DETECT(x) (((x) & 0x1) << 10)
49 #define G_000040_FP2_DETECT(x) (((x) >> 10) & 0x1)
50 #define C_000040_FP2_DETECT 0xFFFFFBFF
51 #define S_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) & 0x1) << 11)
52 #define G_000040_VSYNC_DIFF_OVER_LIMIT(x) (((x) >> 11) & 0x1)
53 #define C_000040_VSYNC_DIFF_OVER_LIMIT 0xFFFFF7FF
54 #define S_000040_DMA_VIPH1_INT_EN(x) (((x) & 0x1) << 13)
55 #define G_000040_DMA_VIPH1_INT_EN(x) (((x) >> 13) & 0x1)
56 #define C_000040_DMA_VIPH1_INT_EN 0xFFFFDFFF
57 #define S_000040_DMA_VIPH2_INT_EN(x) (((x) & 0x1) << 14)
58 #define G_000040_DMA_VIPH2_INT_EN(x) (((x) >> 14) & 0x1)
59 #define C_000040_DMA_VIPH2_INT_EN 0xFFFFBFFF
60 #define S_000040_DMA_VIPH3_INT_EN(x) (((x) & 0x1) << 15)
61 #define G_000040_DMA_VIPH3_INT_EN(x) (((x) >> 15) & 0x1)
62 #define C_000040_DMA_VIPH3_INT_EN 0xFFFF7FFF
63 #define S_000040_I2C_INT_EN(x) (((x) & 0x1) << 17)
64 #define G_000040_I2C_INT_EN(x) (((x) >> 17) & 0x1)
65 #define C_000040_I2C_INT_EN 0xFFFDFFFF
66 #define S_000040_GUI_IDLE(x) (((x) & 0x1) << 19)
67 #define G_000040_GUI_IDLE(x) (((x) >> 19) & 0x1)
68 #define C_000040_GUI_IDLE 0xFFF7FFFF
69 #define S_000040_VIPH_INT_EN(x) (((x) & 0x1) << 24)
70 #define G_000040_VIPH_INT_EN(x) (((x) >> 24) & 0x1)
71 #define C_000040_VIPH_INT_EN 0xFEFFFFFF
72 #define S_000040_SW_INT_EN(x) (((x) & 0x1) << 25)
73 #define G_000040_SW_INT_EN(x) (((x) >> 25) & 0x1)
74 #define C_000040_SW_INT_EN 0xFDFFFFFF
75 #define S_000040_GEYSERVILLE(x) (((x) & 0x1) << 27)
76 #define G_000040_GEYSERVILLE(x) (((x) >> 27) & 0x1)
77 #define C_000040_GEYSERVILLE 0xF7FFFFFF
78 #define S_000040_HDCP_AUTHORIZED_INT(x) (((x) & 0x1) << 28)
79 #define G_000040_HDCP_AUTHORIZED_INT(x) (((x) >> 28) & 0x1)
80 #define C_000040_HDCP_AUTHORIZED_INT 0xEFFFFFFF
81 #define S_000040_DVI_I2C_INT(x) (((x) & 0x1) << 29)
82 #define G_000040_DVI_I2C_INT(x) (((x) >> 29) & 0x1)
83 #define C_000040_DVI_I2C_INT 0xDFFFFFFF
84 #define S_000040_GUIDMA(x) (((x) & 0x1) << 30)
85 #define G_000040_GUIDMA(x) (((x) >> 30) & 0x1)
86 #define C_000040_GUIDMA 0xBFFFFFFF
87 #define S_000040_VIDDMA(x) (((x) & 0x1) << 31)
88 #define G_000040_VIDDMA(x) (((x) >> 31) & 0x1)
89 #define C_000040_VIDDMA 0x7FFFFFFF
90 #define R_000044_GEN_INT_STATUS 0x000044
91 #define S_000044_DISPLAY_INT_STAT(x) (((x) & 0x1) << 0)
92 #define G_000044_DISPLAY_INT_STAT(x) (((x) >> 0) & 0x1)
93 #define C_000044_DISPLAY_INT_STAT 0xFFFFFFFE
94 #define S_000044_VGA_INT_STAT(x) (((x) & 0x1) << 1)
95 #define G_000044_VGA_INT_STAT(x) (((x) >> 1) & 0x1)
96 #define C_000044_VGA_INT_STAT 0xFFFFFFFD
97 #define S_000044_CAP0_INT_ACTIVE(x) (((x) & 0x1) << 8)
98 #define G_000044_CAP0_INT_ACTIVE(x) (((x) >> 8) & 0x1)
99 #define C_000044_CAP0_INT_ACTIVE 0xFFFFFEFF
100 #define S_000044_DMA_VIPH0_INT(x) (((x) & 0x1) << 12)
101 #define G_000044_DMA_VIPH0_INT(x) (((x) >> 12) & 0x1)
102 #define C_000044_DMA_VIPH0_INT 0xFFFFEFFF
103 #define S_000044_DMA_VIPH1_INT(x) (((x) & 0x1) << 13)
104 #define G_000044_DMA_VIPH1_INT(x) (((x) >> 13) & 0x1)
105 #define C_000044_DMA_VIPH1_INT 0xFFFFDFFF
106 #define S_000044_DMA_VIPH2_INT(x) (((x) & 0x1) << 14)
107 #define G_000044_DMA_VIPH2_INT(x) (((x) >> 14) & 0x1)
108 #define C_000044_DMA_VIPH2_INT 0xFFFFBFFF
109 #define S_000044_DMA_VIPH3_INT(x) (((x) & 0x1) << 15)
110 #define G_000044_DMA_VIPH3_INT(x) (((x) >> 15) & 0x1)
111 #define C_000044_DMA_VIPH3_INT 0xFFFF7FFF
112 #define S_000044_MC_PROBE_FAULT_STAT(x) (((x) & 0x1) << 16)
113 #define G_000044_MC_PROBE_FAULT_STAT(x) (((x) >> 16) & 0x1)
114 #define C_000044_MC_PROBE_FAULT_STAT 0xFFFEFFFF
115 #define S_000044_I2C_INT(x) (((x) & 0x1) << 17)
116 #define G_000044_I2C_INT(x) (((x) >> 17) & 0x1)
117 #define C_000044_I2C_INT 0xFFFDFFFF
118 #define S_000044_SCRATCH_INT_STAT(x) (((x) & 0x1) << 18)
119 #define G_000044_SCRATCH_INT_STAT(x) (((x) >> 18) & 0x1)
120 #define C_000044_SCRATCH_INT_STAT 0xFFFBFFFF
121 #define S_000044_GUI_IDLE_STAT(x) (((x) & 0x1) << 19)
122 #define G_000044_GUI_IDLE_STAT(x) (((x) >> 19) & 0x1)
123 #define C_000044_GUI_IDLE_STAT 0xFFF7FFFF
124 #define S_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) & 0x1) << 20)
125 #define G_000044_ATI_OVERDRIVE_INT_STAT(x) (((x) >> 20) & 0x1)
126 #define C_000044_ATI_OVERDRIVE_INT_STAT 0xFFEFFFFF
127 #define S_000044_MC_PROTECTION_FAULT_STAT(x) (((x) & 0x1) << 21)
128 #define G_000044_MC_PROTECTION_FAULT_STAT(x) (((x) >> 21) & 0x1)
129 #define C_000044_MC_PROTECTION_FAULT_STAT 0xFFDFFFFF
130 #define S_000044_RBBM_READ_INT_STAT(x) (((x) & 0x1) << 22)
131 #define G_000044_RBBM_READ_INT_STAT(x) (((x) >> 22) & 0x1)
132 #define C_000044_RBBM_READ_INT_STAT 0xFFBFFFFF
133 #define S_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) & 0x1) << 23)
134 #define G_000044_CB_CONTEXT_SWITCH_STAT(x) (((x) >> 23) & 0x1)
135 #define C_000044_CB_CONTEXT_SWITCH_STAT 0xFF7FFFFF
136 #define S_000044_VIPH_INT(x) (((x) & 0x1) << 24)
137 #define G_000044_VIPH_INT(x) (((x) >> 24) & 0x1)
138 #define C_000044_VIPH_INT 0xFEFFFFFF
139 #define S_000044_SW_INT(x) (((x) & 0x1) << 25)
140 #define G_000044_SW_INT(x) (((x) >> 25) & 0x1)
141 #define C_000044_SW_INT 0xFDFFFFFF
142 #define S_000044_SW_INT_SET(x) (((x) & 0x1) << 26)
143 #define G_000044_SW_INT_SET(x) (((x) >> 26) & 0x1)
144 #define C_000044_SW_INT_SET 0xFBFFFFFF
145 #define S_000044_IDCT_INT_STAT(x) (((x) & 0x1) << 27)
146 #define G_000044_IDCT_INT_STAT(x) (((x) >> 27) & 0x1)
147 #define C_000044_IDCT_INT_STAT 0xF7FFFFFF
148 #define S_000044_GUIDMA_STAT(x) (((x) & 0x1) << 30)
149 #define G_000044_GUIDMA_STAT(x) (((x) >> 30) & 0x1)
150 #define C_000044_GUIDMA_STAT 0xBFFFFFFF
151 #define S_000044_VIDDMA_STAT(x) (((x) & 0x1) << 31)
152 #define G_000044_VIDDMA_STAT(x) (((x) >> 31) & 0x1)
153 #define C_000044_VIDDMA_STAT 0x7FFFFFFF
154 #define R_00004C_BUS_CNTL 0x00004C
155 #define S_00004C_BUS_MASTER_DIS(x) (((x) & 0x1) << 14)
156 #define G_00004C_BUS_MASTER_DIS(x) (((x) >> 14) & 0x1)
157 #define C_00004C_BUS_MASTER_DIS 0xFFFFBFFF
158 #define S_00004C_BUS_MSI_REARM(x) (((x) & 0x1) << 20)
159 #define G_00004C_BUS_MSI_REARM(x) (((x) >> 20) & 0x1)
160 #define C_00004C_BUS_MSI_REARM 0xFFEFFFFF
161 #define R_000070_MC_IND_INDEX 0x000070
162 #define S_000070_MC_IND_ADDR(x) (((x) & 0xFFFF) << 0)
163 #define G_000070_MC_IND_ADDR(x) (((x) >> 0) & 0xFFFF)
164 #define C_000070_MC_IND_ADDR 0xFFFF0000
165 #define S_000070_MC_IND_SEQ_RBS_0(x) (((x) & 0x1) << 16)
166 #define G_000070_MC_IND_SEQ_RBS_0(x) (((x) >> 16) & 0x1)
167 #define C_000070_MC_IND_SEQ_RBS_0 0xFFFEFFFF
168 #define S_000070_MC_IND_SEQ_RBS_1(x) (((x) & 0x1) << 17)
169 #define G_000070_MC_IND_SEQ_RBS_1(x) (((x) >> 17) & 0x1)
170 #define C_000070_MC_IND_SEQ_RBS_1 0xFFFDFFFF
171 #define S_000070_MC_IND_SEQ_RBS_2(x) (((x) & 0x1) << 18)
172 #define G_000070_MC_IND_SEQ_RBS_2(x) (((x) >> 18) & 0x1)
173 #define C_000070_MC_IND_SEQ_RBS_2 0xFFFBFFFF
174 #define S_000070_MC_IND_SEQ_RBS_3(x) (((x) & 0x1) << 19)
175 #define G_000070_MC_IND_SEQ_RBS_3(x) (((x) >> 19) & 0x1)
176 #define C_000070_MC_IND_SEQ_RBS_3 0xFFF7FFFF
177 #define S_000070_MC_IND_AIC_RBS(x) (((x) & 0x1) << 20)
178 #define G_000070_MC_IND_AIC_RBS(x) (((x) >> 20) & 0x1)
179 #define C_000070_MC_IND_AIC_RBS 0xFFEFFFFF
180 #define S_000070_MC_IND_CITF_ARB0(x) (((x) & 0x1) << 21)
181 #define G_000070_MC_IND_CITF_ARB0(x) (((x) >> 21) & 0x1)
182 #define C_000070_MC_IND_CITF_ARB0 0xFFDFFFFF
183 #define S_000070_MC_IND_CITF_ARB1(x) (((x) & 0x1) << 22)
184 #define G_000070_MC_IND_CITF_ARB1(x) (((x) >> 22) & 0x1)
185 #define C_000070_MC_IND_CITF_ARB1 0xFFBFFFFF
186 #define S_000070_MC_IND_WR_EN(x) (((x) & 0x1) << 23)
187 #define G_000070_MC_IND_WR_EN(x) (((x) >> 23) & 0x1)
188 #define C_000070_MC_IND_WR_EN 0xFF7FFFFF
189 #define S_000070_MC_IND_RD_INV(x) (((x) & 0x1) << 24)
190 #define G_000070_MC_IND_RD_INV(x) (((x) >> 24) & 0x1)
191 #define C_000070_MC_IND_RD_INV 0xFEFFFFFF
192 #define R_000074_MC_IND_DATA 0x000074
193 #define S_000074_MC_IND_DATA(x) (((x) & 0xFFFFFFFF) << 0)
194 #define G_000074_MC_IND_DATA(x) (((x) >> 0) & 0xFFFFFFFF)
195 #define C_000074_MC_IND_DATA 0x00000000
196 #define R_000134_HDP_FB_LOCATION 0x000134
197 #define S_000134_HDP_FB_START(x) (((x) & 0xFFFF) << 0)
198 #define G_000134_HDP_FB_START(x) (((x) >> 0) & 0xFFFF)
199 #define C_000134_HDP_FB_START 0xFFFF0000
200 #define R_0007C0_CP_STAT 0x0007C0
201 #define S_0007C0_MRU_BUSY(x) (((x) & 0x1) << 0)
202 #define G_0007C0_MRU_BUSY(x) (((x) >> 0) & 0x1)
203 #define C_0007C0_MRU_BUSY 0xFFFFFFFE
204 #define S_0007C0_MWU_BUSY(x) (((x) & 0x1) << 1)
205 #define G_0007C0_MWU_BUSY(x) (((x) >> 1) & 0x1)
206 #define C_0007C0_MWU_BUSY 0xFFFFFFFD
207 #define S_0007C0_RSIU_BUSY(x) (((x) & 0x1) << 2)
208 #define G_0007C0_RSIU_BUSY(x) (((x) >> 2) & 0x1)
209 #define C_0007C0_RSIU_BUSY 0xFFFFFFFB
210 #define S_0007C0_RCIU_BUSY(x) (((x) & 0x1) << 3)
211 #define G_0007C0_RCIU_BUSY(x) (((x) >> 3) & 0x1)
212 #define C_0007C0_RCIU_BUSY 0xFFFFFFF7
213 #define S_0007C0_CSF_PRIMARY_BUSY(x) (((x) & 0x1) << 9)
214 #define G_0007C0_CSF_PRIMARY_BUSY(x) (((x) >> 9) & 0x1)
215 #define C_0007C0_CSF_PRIMARY_BUSY 0xFFFFFDFF
216 #define S_0007C0_CSF_INDIRECT_BUSY(x) (((x) & 0x1) << 10)
217 #define G_0007C0_CSF_INDIRECT_BUSY(x) (((x) >> 10) & 0x1)
218 #define C_0007C0_CSF_INDIRECT_BUSY 0xFFFFFBFF
219 #define S_0007C0_CSQ_PRIMARY_BUSY(x) (((x) & 0x1) << 11)
220 #define G_0007C0_CSQ_PRIMARY_BUSY(x) (((x) >> 11) & 0x1)
221 #define C_0007C0_CSQ_PRIMARY_BUSY 0xFFFFF7FF
222 #define S_0007C0_CSQ_INDIRECT_BUSY(x) (((x) & 0x1) << 12)
223 #define G_0007C0_CSQ_INDIRECT_BUSY(x) (((x) >> 12) & 0x1)
224 #define C_0007C0_CSQ_INDIRECT_BUSY 0xFFFFEFFF
225 #define S_0007C0_CSI_BUSY(x) (((x) & 0x1) << 13)
226 #define G_0007C0_CSI_BUSY(x) (((x) >> 13) & 0x1)
227 #define C_0007C0_CSI_BUSY 0xFFFFDFFF
228 #define S_0007C0_CSF_INDIRECT2_BUSY(x) (((x) & 0x1) << 14)
229 #define G_0007C0_CSF_INDIRECT2_BUSY(x) (((x) >> 14) & 0x1)
230 #define C_0007C0_CSF_INDIRECT2_BUSY 0xFFFFBFFF
231 #define S_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) & 0x1) << 15)
232 #define G_0007C0_CSQ_INDIRECT2_BUSY(x) (((x) >> 15) & 0x1)
233 #define C_0007C0_CSQ_INDIRECT2_BUSY 0xFFFF7FFF
234 #define S_0007C0_GUIDMA_BUSY(x) (((x) & 0x1) << 28)
235 #define G_0007C0_GUIDMA_BUSY(x) (((x) >> 28) & 0x1)
236 #define C_0007C0_GUIDMA_BUSY 0xEFFFFFFF
237 #define S_0007C0_VIDDMA_BUSY(x) (((x) & 0x1) << 29)
238 #define G_0007C0_VIDDMA_BUSY(x) (((x) >> 29) & 0x1)
239 #define C_0007C0_VIDDMA_BUSY 0xDFFFFFFF
240 #define S_0007C0_CMDSTRM_BUSY(x) (((x) & 0x1) << 30)
241 #define G_0007C0_CMDSTRM_BUSY(x) (((x) >> 30) & 0x1)
242 #define C_0007C0_CMDSTRM_BUSY 0xBFFFFFFF
243 #define S_0007C0_CP_BUSY(x) (((x) & 0x1) << 31)
244 #define G_0007C0_CP_BUSY(x) (((x) >> 31) & 0x1)
245 #define C_0007C0_CP_BUSY 0x7FFFFFFF
246 #define R_000E40_RBBM_STATUS 0x000E40
247 #define S_000E40_CMDFIFO_AVAIL(x) (((x) & 0x7F) << 0)
248 #define G_000E40_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x7F)
249 #define C_000E40_CMDFIFO_AVAIL 0xFFFFFF80
250 #define S_000E40_HIRQ_ON_RBB(x) (((x) & 0x1) << 8)
251 #define G_000E40_HIRQ_ON_RBB(x) (((x) >> 8) & 0x1)
252 #define C_000E40_HIRQ_ON_RBB 0xFFFFFEFF
253 #define S_000E40_CPRQ_ON_RBB(x) (((x) & 0x1) << 9)
254 #define G_000E40_CPRQ_ON_RBB(x) (((x) >> 9) & 0x1)
255 #define C_000E40_CPRQ_ON_RBB 0xFFFFFDFF
256 #define S_000E40_CFRQ_ON_RBB(x) (((x) & 0x1) << 10)
257 #define G_000E40_CFRQ_ON_RBB(x) (((x) >> 10) & 0x1)
258 #define C_000E40_CFRQ_ON_RBB 0xFFFFFBFF
259 #define S_000E40_HIRQ_IN_RTBUF(x) (((x) & 0x1) << 11)
260 #define G_000E40_HIRQ_IN_RTBUF(x) (((x) >> 11) & 0x1)
261 #define C_000E40_HIRQ_IN_RTBUF 0xFFFFF7FF
262 #define S_000E40_CPRQ_IN_RTBUF(x) (((x) & 0x1) << 12)
263 #define G_000E40_CPRQ_IN_RTBUF(x) (((x) >> 12) & 0x1)
264 #define C_000E40_CPRQ_IN_RTBUF 0xFFFFEFFF
265 #define S_000E40_CFRQ_IN_RTBUF(x) (((x) & 0x1) << 13)
266 #define G_000E40_CFRQ_IN_RTBUF(x) (((x) >> 13) & 0x1)
267 #define C_000E40_CFRQ_IN_RTBUF 0xFFFFDFFF
268 #define S_000E40_CF_PIPE_BUSY(x) (((x) & 0x1) << 14)
269 #define G_000E40_CF_PIPE_BUSY(x) (((x) >> 14) & 0x1)
270 #define C_000E40_CF_PIPE_BUSY 0xFFFFBFFF
271 #define S_000E40_ENG_EV_BUSY(x) (((x) & 0x1) << 15)
272 #define G_000E40_ENG_EV_BUSY(x) (((x) >> 15) & 0x1)
273 #define C_000E40_ENG_EV_BUSY 0xFFFF7FFF
274 #define S_000E40_CP_CMDSTRM_BUSY(x) (((x) & 0x1) << 16)
275 #define G_000E40_CP_CMDSTRM_BUSY(x) (((x) >> 16) & 0x1)
276 #define C_000E40_CP_CMDSTRM_BUSY 0xFFFEFFFF
277 #define S_000E40_E2_BUSY(x) (((x) & 0x1) << 17)
278 #define G_000E40_E2_BUSY(x) (((x) >> 17) & 0x1)
279 #define C_000E40_E2_BUSY 0xFFFDFFFF
280 #define S_000E40_RB2D_BUSY(x) (((x) & 0x1) << 18)
281 #define G_000E40_RB2D_BUSY(x) (((x) >> 18) & 0x1)
282 #define C_000E40_RB2D_BUSY 0xFFFBFFFF
283 #define S_000E40_RB3D_BUSY(x) (((x) & 0x1) << 19)
284 #define G_000E40_RB3D_BUSY(x) (((x) >> 19) & 0x1)
285 #define C_000E40_RB3D_BUSY 0xFFF7FFFF
286 #define S_000E40_VAP_BUSY(x) (((x) & 0x1) << 20)
287 #define G_000E40_VAP_BUSY(x) (((x) >> 20) & 0x1)
288 #define C_000E40_VAP_BUSY 0xFFEFFFFF
289 #define S_000E40_RE_BUSY(x) (((x) & 0x1) << 21)
290 #define G_000E40_RE_BUSY(x) (((x) >> 21) & 0x1)
291 #define C_000E40_RE_BUSY 0xFFDFFFFF
292 #define S_000E40_TAM_BUSY(x) (((x) & 0x1) << 22)
293 #define G_000E40_TAM_BUSY(x) (((x) >> 22) & 0x1)
294 #define C_000E40_TAM_BUSY 0xFFBFFFFF
295 #define S_000E40_TDM_BUSY(x) (((x) & 0x1) << 23)
296 #define G_000E40_TDM_BUSY(x) (((x) >> 23) & 0x1)
297 #define C_000E40_TDM_BUSY 0xFF7FFFFF
298 #define S_000E40_PB_BUSY(x) (((x) & 0x1) << 24)
299 #define G_000E40_PB_BUSY(x) (((x) >> 24) & 0x1)
300 #define C_000E40_PB_BUSY 0xFEFFFFFF
301 #define S_000E40_TIM_BUSY(x) (((x) & 0x1) << 25)
302 #define G_000E40_TIM_BUSY(x) (((x) >> 25) & 0x1)
303 #define C_000E40_TIM_BUSY 0xFDFFFFFF
304 #define S_000E40_GA_BUSY(x) (((x) & 0x1) << 26)
305 #define G_000E40_GA_BUSY(x) (((x) >> 26) & 0x1)
306 #define C_000E40_GA_BUSY 0xFBFFFFFF
307 #define S_000E40_CBA2D_BUSY(x) (((x) & 0x1) << 27)
308 #define G_000E40_CBA2D_BUSY(x) (((x) >> 27) & 0x1)
309 #define C_000E40_CBA2D_BUSY 0xF7FFFFFF
310 #define S_000E40_GUI_ACTIVE(x) (((x) & 0x1) << 31)
311 #define G_000E40_GUI_ACTIVE(x) (((x) >> 31) & 0x1)
312 #define C_000E40_GUI_ACTIVE 0x7FFFFFFF
313 #define R_0060A4_D1CRTC_STATUS_FRAME_COUNT 0x0060A4
314 #define S_0060A4_D1CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0)
315 #define G_0060A4_D1CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF)
316 #define C_0060A4_D1CRTC_FRAME_COUNT 0xFF000000
317 #define R_006534_D1MODE_VBLANK_STATUS 0x006534
318 #define S_006534_D1MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0)
319 #define G_006534_D1MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1)
320 #define C_006534_D1MODE_VBLANK_OCCURRED 0xFFFFFFFE
321 #define S_006534_D1MODE_VBLANK_ACK(x) (((x) & 0x1) << 4)
322 #define G_006534_D1MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1)
323 #define C_006534_D1MODE_VBLANK_ACK 0xFFFFFFEF
324 #define S_006534_D1MODE_VBLANK_STAT(x) (((x) & 0x1) << 12)
325 #define G_006534_D1MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1)
326 #define C_006534_D1MODE_VBLANK_STAT 0xFFFFEFFF
327 #define S_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16)
328 #define G_006534_D1MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1)
329 #define C_006534_D1MODE_VBLANK_INTERRUPT 0xFFFEFFFF
330 #define R_006540_DxMODE_INT_MASK 0x006540
331 #define S_006540_D1MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 0)
332 #define G_006540_D1MODE_VBLANK_INT_MASK(x) (((x) >> 0) & 0x1)
333 #define C_006540_D1MODE_VBLANK_INT_MASK 0xFFFFFFFE
334 #define S_006540_D1MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 4)
335 #define G_006540_D1MODE_VLINE_INT_MASK(x) (((x) >> 4) & 0x1)
336 #define C_006540_D1MODE_VLINE_INT_MASK 0xFFFFFFEF
337 #define S_006540_D2MODE_VBLANK_INT_MASK(x) (((x) & 0x1) << 8)
338 #define G_006540_D2MODE_VBLANK_INT_MASK(x) (((x) >> 8) & 0x1)
339 #define C_006540_D2MODE_VBLANK_INT_MASK 0xFFFFFEFF
340 #define S_006540_D2MODE_VLINE_INT_MASK(x) (((x) & 0x1) << 12)
341 #define G_006540_D2MODE_VLINE_INT_MASK(x) (((x) >> 12) & 0x1)
342 #define C_006540_D2MODE_VLINE_INT_MASK 0xFFFFEFFF
343 #define S_006540_D1MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 30)
344 #define G_006540_D1MODE_VBLANK_CP_SEL(x) (((x) >> 30) & 0x1)
345 #define C_006540_D1MODE_VBLANK_CP_SEL 0xBFFFFFFF
346 #define S_006540_D2MODE_VBLANK_CP_SEL(x) (((x) & 0x1) << 31)
347 #define G_006540_D2MODE_VBLANK_CP_SEL(x) (((x) >> 31) & 0x1)
348 #define C_006540_D2MODE_VBLANK_CP_SEL 0x7FFFFFFF
349 #define R_0068A4_D2CRTC_STATUS_FRAME_COUNT 0x0068A4
350 #define S_0068A4_D2CRTC_FRAME_COUNT(x) (((x) & 0xFFFFFF) << 0)
351 #define G_0068A4_D2CRTC_FRAME_COUNT(x) (((x) >> 0) & 0xFFFFFF)
352 #define C_0068A4_D2CRTC_FRAME_COUNT 0xFF000000
353 #define R_006D34_D2MODE_VBLANK_STATUS 0x006D34
354 #define S_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) & 0x1) << 0)
355 #define G_006D34_D2MODE_VBLANK_OCCURRED(x) (((x) >> 0) & 0x1)
356 #define C_006D34_D2MODE_VBLANK_OCCURRED 0xFFFFFFFE
357 #define S_006D34_D2MODE_VBLANK_ACK(x) (((x) & 0x1) << 4)
358 #define G_006D34_D2MODE_VBLANK_ACK(x) (((x) >> 4) & 0x1)
359 #define C_006D34_D2MODE_VBLANK_ACK 0xFFFFFFEF
360 #define S_006D34_D2MODE_VBLANK_STAT(x) (((x) & 0x1) << 12)
361 #define G_006D34_D2MODE_VBLANK_STAT(x) (((x) >> 12) & 0x1)
362 #define C_006D34_D2MODE_VBLANK_STAT 0xFFFFEFFF
363 #define S_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) & 0x1) << 16)
364 #define G_006D34_D2MODE_VBLANK_INTERRUPT(x) (((x) >> 16) & 0x1)
365 #define C_006D34_D2MODE_VBLANK_INTERRUPT 0xFFFEFFFF
366 #define R_007EDC_DISP_INTERRUPT_STATUS 0x007EDC
367 #define S_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) & 0x1) << 4)
368 #define G_007EDC_LB_D1_VBLANK_INTERRUPT(x) (((x) >> 4) & 0x1)
369 #define C_007EDC_LB_D1_VBLANK_INTERRUPT 0xFFFFFFEF
370 #define S_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) & 0x1) << 5)
371 #define G_007EDC_LB_D2_VBLANK_INTERRUPT(x) (((x) >> 5) & 0x1)
372 #define C_007EDC_LB_D2_VBLANK_INTERRUPT 0xFFFFFFDF
375 /* MC registers */
376 #define R_000000_MC_STATUS 0x000000
377 #define S_000000_MC_IDLE(x) (((x) & 0x1) << 0)
378 #define G_000000_MC_IDLE(x) (((x) >> 0) & 0x1)
379 #define C_000000_MC_IDLE 0xFFFFFFFE
380 #define R_000004_MC_FB_LOCATION 0x000004
381 #define S_000004_MC_FB_START(x) (((x) & 0xFFFF) << 0)
382 #define G_000004_MC_FB_START(x) (((x) >> 0) & 0xFFFF)
383 #define C_000004_MC_FB_START 0xFFFF0000
384 #define S_000004_MC_FB_TOP(x) (((x) & 0xFFFF) << 16)
385 #define G_000004_MC_FB_TOP(x) (((x) >> 16) & 0xFFFF)
386 #define C_000004_MC_FB_TOP 0x0000FFFF
387 #define R_000005_MC_AGP_LOCATION 0x000005
388 #define S_000005_MC_AGP_START(x) (((x) & 0xFFFF) << 0)
389 #define G_000005_MC_AGP_START(x) (((x) >> 0) & 0xFFFF)
390 #define C_000005_MC_AGP_START 0xFFFF0000
391 #define S_000005_MC_AGP_TOP(x) (((x) & 0xFFFF) << 16)
392 #define G_000005_MC_AGP_TOP(x) (((x) >> 16) & 0xFFFF)
393 #define C_000005_MC_AGP_TOP 0x0000FFFF
394 #define R_000006_AGP_BASE 0x000006
395 #define S_000006_AGP_BASE_ADDR(x) (((x) & 0xFFFFFFFF) << 0)
396 #define G_000006_AGP_BASE_ADDR(x) (((x) >> 0) & 0xFFFFFFFF)
397 #define C_000006_AGP_BASE_ADDR 0x00000000
398 #define R_000007_AGP_BASE_2 0x000007
399 #define S_000007_AGP_BASE_ADDR_2(x) (((x) & 0xF) << 0)
400 #define G_000007_AGP_BASE_ADDR_2(x) (((x) >> 0) & 0xF)
401 #define C_000007_AGP_BASE_ADDR_2 0xFFFFFFF0
402 #define R_000009_MC_CNTL1 0x000009
403 #define S_000009_ENABLE_PAGE_TABLES(x) (((x) & 0x1) << 26)
404 #define G_000009_ENABLE_PAGE_TABLES(x) (((x) >> 26) & 0x1)
405 #define C_000009_ENABLE_PAGE_TABLES 0xFBFFFFFF
406 /* FIXME don't know the various field size need feedback from AMD */
407 #define R_000100_MC_PT0_CNTL 0x000100
408 #define S_000100_ENABLE_PT(x) (((x) & 0x1) << 0)
409 #define G_000100_ENABLE_PT(x) (((x) >> 0) & 0x1)
410 #define C_000100_ENABLE_PT 0xFFFFFFFE
411 #define S_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) & 0x7) << 15)
412 #define G_000100_EFFECTIVE_L2_CACHE_SIZE(x) (((x) >> 15) & 0x7)
413 #define C_000100_EFFECTIVE_L2_CACHE_SIZE 0xFFFC7FFF
414 #define S_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 0x7) << 21)
415 #define G_000100_EFFECTIVE_L2_QUEUE_SIZE(x) (((x) >> 21) & 0x7)
416 #define C_000100_EFFECTIVE_L2_QUEUE_SIZE 0xFF1FFFFF
417 #define S_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) & 0x1) << 28)
418 #define G_000100_INVALIDATE_ALL_L1_TLBS(x) (((x) >> 28) & 0x1)
419 #define C_000100_INVALIDATE_ALL_L1_TLBS 0xEFFFFFFF
420 #define S_000100_INVALIDATE_L2_CACHE(x) (((x) & 0x1) << 29)
421 #define G_000100_INVALIDATE_L2_CACHE(x) (((x) >> 29) & 0x1)
422 #define C_000100_INVALIDATE_L2_CACHE 0xDFFFFFFF
423 #define R_000102_MC_PT0_CONTEXT0_CNTL 0x000102
424 #define S_000102_ENABLE_PAGE_TABLE(x) (((x) & 0x1) << 0)
425 #define G_000102_ENABLE_PAGE_TABLE(x) (((x) >> 0) & 0x1)
426 #define C_000102_ENABLE_PAGE_TABLE 0xFFFFFFFE
427 #define S_000102_PAGE_TABLE_DEPTH(x) (((x) & 0x3) << 1)
428 #define G_000102_PAGE_TABLE_DEPTH(x) (((x) >> 1) & 0x3)
429 #define C_000102_PAGE_TABLE_DEPTH 0xFFFFFFF9
430 #define V_000102_PAGE_TABLE_FLAT 0
431 /* R600 documentation suggest that this should be a number of pages */
432 #define R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR 0x000112
433 #define R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR 0x000114
434 #define R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR 0x00011C
435 #define R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR 0x00012C
436 #define R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR 0x00013C
437 #define R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR 0x00014C
438 #define R_00016C_MC_PT0_CLIENT0_CNTL 0x00016C
439 #define S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 0)
440 #define G_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 0) & 0x1)
441 #define C_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFE
442 #define S_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) & 0x1) << 1)
443 #define G_00016C_TRANSLATION_MODE_OVERRIDE(x) (((x) >> 1) & 0x1)
444 #define C_00016C_TRANSLATION_MODE_OVERRIDE 0xFFFFFFFD
445 #define S_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) & 0x3) << 8)
446 #define G_00016C_SYSTEM_ACCESS_MODE_MASK(x) (((x) >> 8) & 0x3)
447 #define C_00016C_SYSTEM_ACCESS_MODE_MASK 0xFFFFFCFF
448 #define V_00016C_SYSTEM_ACCESS_MODE_PA_ONLY 0
449 #define V_00016C_SYSTEM_ACCESS_MODE_USE_SYS_MAP 1
450 #define V_00016C_SYSTEM_ACCESS_MODE_IN_SYS 2
451 #define V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS 3
452 #define S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) & 0x1) << 10)
453 #define G_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(x) (((x) >> 10) & 0x1)
454 #define C_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS 0xFFFFFBFF
455 #define V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH 0
456 #define V_00016C_SYSTEM_APERTURE_UNMAPPED_DEFAULT_PAGE 1
457 #define S_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) & 0x7) << 11)
458 #define G_00016C_EFFECTIVE_L1_CACHE_SIZE(x) (((x) >> 11) & 0x7)
459 #define C_00016C_EFFECTIVE_L1_CACHE_SIZE 0xFFFFC7FF
460 #define S_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) & 0x1) << 14)
461 #define G_00016C_ENABLE_FRAGMENT_PROCESSING(x) (((x) >> 14) & 0x1)
462 #define C_00016C_ENABLE_FRAGMENT_PROCESSING 0xFFFFBFFF
463 #define S_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 0x7) << 15)
464 #define G_00016C_EFFECTIVE_L1_QUEUE_SIZE(x) (((x) >> 15) & 0x7)
465 #define C_00016C_EFFECTIVE_L1_QUEUE_SIZE 0xFFFC7FFF
466 #define S_00016C_INVALIDATE_L1_TLB(x) (((x) & 0x1) << 20)
467 #define G_00016C_INVALIDATE_L1_TLB(x) (((x) >> 20) & 0x1)
468 #define C_00016C_INVALIDATE_L1_TLB 0xFFEFFFFF
470 #endif