drivers/media/dvb/frontends/cx24110.c

   1         /*
   2     cx24110 - Single Chip Satellite Channel Receiver driver module
   3
   4     Copyright (C) 2002 Peter Hettkamp <peter.hettkamp@htp-tel.de> based on
   5     work
   6     Copyright (C) 1999 Convergence Integrated Media GmbH <ralph@convergence.de>
   7
   8     This program is free software; you can redistribute it and/or modify
   9     it under the terms of the GNU General Public License as published by
  10     the Free Software Foundation; either version 2 of the License, or
  11     (at your option) any later version.
  12
  13     This program is distributed in the hope that it will be useful,
  14     but WITHOUT ANY WARRANTY; without even the implied warranty of
  15     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22
  23 */
  24
  25 #include <linux/slab.h>
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29
  30 #include "dvb_frontend.h"
  31 #include "cx24110.h"
  32
  33
  34 struct cx24110_state {
  35
  36         struct i2c_adapter* i2c;
  37
  38         const struct cx24110_config* config;
  39
  40         struct dvb_frontend frontend;
  41
  42         u32 lastber;
  43         u32 lastbler;
  44         u32 lastesn0;
  45 };
  46
  47 static int debug;
  48 #define dprintk(args...) \
  49         do { \
  50                 if (debug) printk(KERN_DEBUG "cx24110: " args); \
  51         } while (0)
  52
  53 static struct {u8 reg; u8 data;} cx24110_regdata[]=
  54                       /* Comments beginning with @ denote this value should
  55                          be the default */
  56         {{0x09,0x01}, /* SoftResetAll */
  57          {0x09,0x00}, /* release reset */
  58          {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
  59          {0x02,0x17}, /* middle byte " */
  60          {0x03,0x29}, /* LSB         " */
  61          {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
  62          {0x06,0xa5}, /* @ PLL 60MHz */
  63          {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
  64          {0x0a,0x00}, /* @ partial chip disables, do not set */
  65          {0x0b,0x01}, /* set output clock in gapped mode, start signal low
  66                          active for first byte */
  67          {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
  68          {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
  69          {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
  70                          to avoid starting the BER counter. Reset the
  71                          CRC test bit. Finite counting selected */
  72          {0x15,0xff}, /* @ size of the limited time window for RS BER
  73                          estimation. It is <value>*256 RS blocks, this
  74                          gives approx. 2.6 sec at 27.5MS/s, rate 3/4 */
  75          {0x16,0x00}, /* @ enable all RS output ports */
  76          {0x17,0x04}, /* @ time window allowed for the RS to sync */
  77          {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
  78                          for automatically */
  79                       /* leave the current code rate and normalization
  80                          registers as they are after reset... */
  81          {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
  82                          only once */
  83          {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
  84                          estimation. It is <value>*65536 channel bits, i.e.
  85                          approx. 38ms at 27.5MS/s, rate 3/4 */
  86          {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
  87                       /* leave front-end AGC parameters at default values */
  88                       /* leave decimation AGC parameters at default values */
  89          {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
  90          {0x36,0xff}, /* clear all interrupt pending flags */
  91          {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
  92          {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
  93                       /* leave the equalizer parameters on their default values */
  94                       /* leave the final AGC parameters on their default values */
  95          {0x41,0x00}, /* @ MSB of front-end derotator frequency */
  96          {0x42,0x00}, /* @ middle bytes " */
  97          {0x43,0x00}, /* @ LSB          " */
  98                       /* leave the carrier tracking loop parameters on default */
  99                       /* leave the bit timing loop parameters at gefault */
 100          {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
 101                       /* the cx24108 data sheet for symbol rates above 15MS/s */
 102          {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
 103          {0x61,0x95}, /* GPIO pins 1-4 have special function */
 104          {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
 105          {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
 106          {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
 107          {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
 108          {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
 109          {0x73,0x00}, /* @ disable several demod bypasses */
 110          {0x74,0x00}, /* @  " */
 111          {0x75,0x00}  /* @  " */
 112                       /* the remaining registers are for SEC */
 113         };
 114
 115
 116 static int cx24110_writereg (struct cx24110_state* state, int reg, int data)
 117 {
 118         u8 buf [] = { reg, data };
 119         struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };
 120         int err;
 121
 122         if ((err = i2c_transfer(state->i2c, &msg, 1)) != 1) {
 123                 dprintk ("%s: writereg error (err == %i, reg == 0x%02x,"
 124                          " data == 0x%02x)\n", __func__, err, reg, data);
 125                 return -EREMOTEIO;
 126         }
 127
 128         return 0;
 129 }
 130
 131 static int cx24110_readreg (struct cx24110_state* state, u8 reg)
 132 {
 133         int ret;
 134         u8 b0 [] = { reg };
 135         u8 b1 [] = { 0 };
 136         struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 },
 137                            { .addr = state->config->demod_address, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
 138
 139         ret = i2c_transfer(state->i2c, msg, 2);
 140
 141         if (ret != 2) return ret;
 142
 143         return b1[0];
 144 }
 145
 146 static int cx24110_set_inversion (struct cx24110_state* state, fe_spectral_inversion_t inversion)
 147 {
 148 /* fixme (low): error handling */
 149
 150         switch (inversion) {
 151         case INVERSION_OFF:
 152                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
 153                 /* AcqSpectrInvDis on. No idea why someone should want this */
 154                 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7);
 155                 /* Initial value 0 at start of acq */
 156                 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef);
 157                 /* current value 0 */
 158                 /* The cx24110 manual tells us this reg is read-only.
 159                    But what the heck... set it ayways */
 160                 break;
 161         case INVERSION_ON:
 162                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1);
 163                 /* AcqSpectrInvDis on. No idea why someone should want this */
 164                 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08);
 165                 /* Initial value 1 at start of acq */
 166                 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10);
 167                 /* current value 1 */
 168                 break;
 169         case INVERSION_AUTO:
 170                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe);
 171                 /* AcqSpectrInvDis off. Leave initial & current states as is */
 172                 break;
 173         default:
 174                 return -EINVAL;
 175         }
 176
 177         return 0;
 178 }
 179
 180 static int cx24110_set_fec (struct cx24110_state* state, fe_code_rate_t fec)
 181 {
 182 /* fixme (low): error handling */
 183
 184         static const int rate[]={-1,1,2,3,5,7,-1};
 185         static const int g1[]={-1,0x01,0x02,0x05,0x15,0x45,-1};
 186         static const int g2[]={-1,0x01,0x03,0x06,0x1a,0x7a,-1};
 187
 188         /* Well, the AutoAcq engine of the cx24106 and 24110 automatically
 189            searches all enabled viterbi rates, and can handle non-standard
 190            rates as well. */
 191
 192         if (fec>FEC_AUTO)
 193                 fec=FEC_AUTO;
 194
 195         if (fec==FEC_AUTO) { /* (re-)establish AutoAcq behaviour */
 196                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xdf);
 197                 /* clear AcqVitDis bit */
 198                 cx24110_writereg(state,0x18,0xae);
 199                 /* allow all DVB standard code rates */
 200                 cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|0x3);
 201                 /* set nominal Viterbi rate 3/4 */
 202                 cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|0x3);
 203                 /* set current Viterbi rate 3/4 */
 204                 cx24110_writereg(state,0x1a,0x05); cx24110_writereg(state,0x1b,0x06);
 205                 /* set the puncture registers for code rate 3/4 */
 206                 return 0;
 207         } else {
 208                 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x20);
 209                 /* set AcqVitDis bit */
 210                 if(rate[fec]>0) {
 211                         cx24110_writereg(state,0x05,(cx24110_readreg(state,0x05)&0xf0)|rate[fec]);
 212                         /* set nominal Viterbi rate */
 213                         cx24110_writereg(state,0x22,(cx24110_readreg(state,0x22)&0xf0)|rate[fec]);
 214                         /* set current Viterbi rate */
 215                         cx24110_writereg(state,0x1a,g1[fec]);
 216                         cx24110_writereg(state,0x1b,g2[fec]);
 217                         /* not sure if this is the right way: I always used AutoAcq mode */
 218            } else
 219                    return -EOPNOTSUPP;
 220 /* fixme (low): which is the correct return code? */
 221         };
 222         return 0;
 223 }
 224
 225 static fe_code_rate_t cx24110_get_fec (struct cx24110_state* state)
 226 {
 227         int i;
 228
 229         i=cx24110_readreg(state,0x22)&0x0f;
 230         if(!(i&0x08)) {
 231                 return FEC_1_2 + i - 1;
 232         } else {
 233 /* fixme (low): a special code rate has been selected. In theory, we need to
 234    return a denominator value, a numerator value, and a pair of puncture
 235    maps to correctly describe this mode. But this should never happen in
 236    practice, because it cannot be set by cx24110_get_fec. */
 237            return FEC_NONE;
 238         }
 239 }
 240
 241 static int cx24110_set_symbolrate (struct cx24110_state* state, u32 srate)
 242 {
 243 /* fixme (low): add error handling */
 244         u32 ratio;
 245         u32 tmp, fclk, BDRI;
 246
 247         static const u32 bands[]={5000000UL,15000000UL,90999000UL/2};
 248         int i;
 249
 250         dprintk("cx24110 debug: entering %s(%d)\n",__func__,srate);
 251         if (srate>90999000UL/2)
 252                 srate=90999000UL/2;
 253         if (srate<500000)
 254                 srate=500000;
 255
 256         for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++)
 257                 ;
 258         /* first, check which sample rate is appropriate: 45, 60 80 or 90 MHz,
 259            and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult,
 260            R06[3:0] PLLphaseDetGain */
 261         tmp=cx24110_readreg(state,0x07)&0xfc;
 262         if(srate<90999000UL/4) { /* sample rate 45MHz*/
 263                 cx24110_writereg(state,0x07,tmp);
 264                 cx24110_writereg(state,0x06,0x78);
 265                 fclk=90999000UL/2;
 266         } else if(srate<60666000UL/2) { /* sample rate 60MHz */
 267                 cx24110_writereg(state,0x07,tmp|0x1);
 268                 cx24110_writereg(state,0x06,0xa5);
 269                 fclk=60666000UL;
 270         } else if(srate<80888000UL/2) { /* sample rate 80MHz */
 271                 cx24110_writereg(state,0x07,tmp|0x2);
 272                 cx24110_writereg(state,0x06,0x87);
 273                 fclk=80888000UL;
 274         } else { /* sample rate 90MHz */
 275                 cx24110_writereg(state,0x07,tmp|0x3);
 276                 cx24110_writereg(state,0x06,0x78);
 277                 fclk=90999000UL;
 278         };
 279         dprintk("cx24110 debug: fclk %d Hz\n",fclk);
 280         /* we need to divide two integers with approx. 27 bits in 32 bit
 281            arithmetic giving a 25 bit result */
 282         /* the maximum dividend is 90999000/2, 0x02b6446c, this number is
 283            also the most complex divisor. Hence, the dividend has,
 284            assuming 32bit unsigned arithmetic, 6 clear bits on top, the
 285            divisor 2 unused bits at the bottom. Also, the quotient is
 286            always less than 1/2. Borrowed from VES1893.c, of course */
 287
 288         tmp=srate<<6;
 289         BDRI=fclk>>2;
 290         ratio=(tmp/BDRI);
 291
 292         tmp=(tmp%BDRI)<<8;
 293         ratio=(ratio<<8)+(tmp/BDRI);
 294
 295         tmp=(tmp%BDRI)<<8;
 296         ratio=(ratio<<8)+(tmp/BDRI);
 297
 298         tmp=(tmp%BDRI)<<1;
 299         ratio=(ratio<<1)+(tmp/BDRI);
 300
 301         dprintk("srate= %d (range %d, up to %d)\n", srate,i,bands[i]);
 302         dprintk("fclk = %d\n", fclk);
 303         dprintk("ratio= %08x\n", ratio);
 304
 305         cx24110_writereg(state, 0x1, (ratio>>16)&0xff);
 306         cx24110_writereg(state, 0x2, (ratio>>8)&0xff);
 307         cx24110_writereg(state, 0x3, (ratio)&0xff);
 308
 309         return 0;
 310
 311 }
 312
 313 static int _cx24110_pll_write (struct dvb_frontend* fe, u8 *buf, int len)
 314 {
 315         struct cx24110_state *state = fe->demodulator_priv;
 316
 317         if (len != 3)
 318                 return -EINVAL;
 319
 320 /* tuner data is 21 bits long, must be left-aligned in data */
 321 /* tuner cx24108 is written through a dedicated 3wire interface on the demod chip */
 322 /* FIXME (low): add error handling, avoid infinite loops if HW fails... */
 323
 324         cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */
 325         cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */
 326
 327         /* if the auto tuner writer is still busy, clear it out */
 328         while (cx24110_readreg(state,0x6d)&0x80)
 329                 cx24110_writereg(state,0x72,0);
 330
 331         /* write the topmost 8 bits */
 332         cx24110_writereg(state,0x72,buf[0]);
 333
 334         /* wait for the send to be completed */
 335         while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 336                 ;
 337
 338         /* send another 8 bytes */
 339         cx24110_writereg(state,0x72,buf[1]);
 340         while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 341                 ;
 342
 343         /* and the topmost 5 bits of this byte */
 344         cx24110_writereg(state,0x72,buf[2]);
 345         while ((cx24110_readreg(state,0x6d)&0xc0)==0x80)
 346                 ;
 347
 348         /* now strobe the enable line once */
 349         cx24110_writereg(state,0x6d,0x32);
 350         cx24110_writereg(state,0x6d,0x30);
 351
 352         return 0;
 353 }
 354
 355 static int cx24110_initfe(struct dvb_frontend* fe)
 356 {
 357         struct cx24110_state *state = fe->demodulator_priv;
 358 /* fixme (low): error handling */
 359         int i;
 360
 361         dprintk("%s: init chip\n", __func__);
 362
 363         for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) {
 364                 cx24110_writereg(state, cx24110_regdata[i].reg, cx24110_regdata[i].data);
 365         };
 366
 367         return 0;
 368 }
 369
 370 static int cx24110_set_voltage (struct dvb_frontend* fe, fe_sec_voltage_t voltage)
 371 {
 372         struct cx24110_state *state = fe->demodulator_priv;
 373
 374         switch (voltage) {
 375         case SEC_VOLTAGE_13:
 376                 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0);
 377         case SEC_VOLTAGE_18:
 378                 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40);
 379         default:
 380                 return -EINVAL;
 381         };
 382 }
 383
 384 static int cx24110_diseqc_send_burst(struct dvb_frontend* fe, fe_sec_mini_cmd_t burst)
 385 {
 386         int rv, bit;
 387         struct cx24110_state *state = fe->demodulator_priv;
 388         unsigned long timeout;
 389
 390         if (burst == SEC_MINI_A)
 391                 bit = 0x00;
 392         else if (burst == SEC_MINI_B)
 393                 bit = 0x08;
 394         else
 395                 return -EINVAL;
 396
 397         rv = cx24110_readreg(state, 0x77);
 398         if (!(rv & 0x04))
 399                 cx24110_writereg(state, 0x77, rv | 0x04);
 400
 401         rv = cx24110_readreg(state, 0x76);
 402         cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit));
 403         timeout = jiffies + msecs_to_jiffies(100);
 404         while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
 405                 ; /* wait for LNB ready */
 406
 407         return 0;
 408 }
 409
 410 static int cx24110_send_diseqc_msg(struct dvb_frontend* fe,
 411                                    struct dvb_diseqc_master_cmd *cmd)
 412 {
 413         int i, rv;
 414         struct cx24110_state *state = fe->demodulator_priv;
 415         unsigned long timeout;
 416
 417         if (cmd->msg_len < 3 || cmd->msg_len > 6)
 418                 return -EINVAL;  /* not implemented */
 419
 420         for (i = 0; i < cmd->msg_len; i++)
 421                 cx24110_writereg(state, 0x79 + i, cmd->msg[i]);
 422
 423         rv = cx24110_readreg(state, 0x77);
 424         if (rv & 0x04) {
 425                 cx24110_writereg(state, 0x77, rv & ~0x04);
 426                 msleep(30); /* reportedly fixes switching problems */
 427         }
 428
 429         rv = cx24110_readreg(state, 0x76);
 430
 431         cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3));
 432         timeout = jiffies + msecs_to_jiffies(100);
 433         while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40))
 434                 ; /* wait for LNB ready */
 435
 436         return 0;
 437 }
 438
 439 static int cx24110_read_status(struct dvb_frontend* fe, fe_status_t* status)
 440 {
 441         struct cx24110_state *state = fe->demodulator_priv;
 442
 443         int sync = cx24110_readreg (state, 0x55);
 444
 445         *status = 0;
 446
 447         if (sync & 0x10)
 448                 *status |= FE_HAS_SIGNAL;
 449
 450         if (sync & 0x08)
 451                 *status |= FE_HAS_CARRIER;
 452
 453         sync = cx24110_readreg (state, 0x08);
 454
 455         if (sync & 0x40)
 456                 *status |= FE_HAS_VITERBI;
 457
 458         if (sync & 0x20)
 459                 *status |= FE_HAS_SYNC;
 460
 461         if ((sync & 0x60) == 0x60)
 462                 *status |= FE_HAS_LOCK;
 463
 464         return 0;
 465 }
 466
 467 static int cx24110_read_ber(struct dvb_frontend* fe, u32* ber)
 468 {
 469         struct cx24110_state *state = fe->demodulator_priv;
 470
 471         /* fixme (maybe): value range is 16 bit. Scale? */
 472         if(cx24110_readreg(state,0x24)&0x10) {
 473                 /* the Viterbi error counter has finished one counting window */
 474                 cx24110_writereg(state,0x24,0x04); /* select the ber reg */
 475                 state->lastber=cx24110_readreg(state,0x25)|
 476                         (cx24110_readreg(state,0x26)<<8);
 477                 cx24110_writereg(state,0x24,0x04); /* start new count window */
 478                 cx24110_writereg(state,0x24,0x14);
 479         }
 480         *ber = state->lastber;
 481
 482         return 0;
 483 }
 484
 485 static int cx24110_read_signal_strength(struct dvb_frontend* fe, u16* signal_strength)
 486 {
 487         struct cx24110_state *state = fe->demodulator_priv;
 488
 489 /* no provision in hardware. Read the frontend AGC accumulator. No idea how to scale this, but I know it is 2s complement */
 490         u8 signal = cx24110_readreg (state, 0x27)+128;
 491         *signal_strength = (signal << 8) | signal;
 492
 493         return 0;
 494 }
 495
 496 static int cx24110_read_snr(struct dvb_frontend* fe, u16* snr)
 497 {
 498         struct cx24110_state *state = fe->demodulator_priv;
 499
 500         /* no provision in hardware. Can be computed from the Es/N0 estimator, but I don't know how. */
 501         if(cx24110_readreg(state,0x6a)&0x80) {
 502                 /* the Es/N0 error counter has finished one counting window */
 503                 state->lastesn0=cx24110_readreg(state,0x69)|
 504                         (cx24110_readreg(state,0x68)<<8);
 505                 cx24110_writereg(state,0x6a,0x84); /* start new count window */
 506         }
 507         *snr = state->lastesn0;
 508
 509         return 0;
 510 }
 511
 512 static int cx24110_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
 513 {
 514         struct cx24110_state *state = fe->demodulator_priv;
 515         u32 lastbyer;
 516
 517         if(cx24110_readreg(state,0x10)&0x40) {
 518                 /* the RS error counter has finished one counting window */
 519                 cx24110_writereg(state,0x10,0x60); /* select the byer reg */
 520                 lastbyer=cx24110_readreg(state,0x12)|
 521                         (cx24110_readreg(state,0x13)<<8)|
 522                         (cx24110_readreg(state,0x14)<<16);
 523                 cx24110_writereg(state,0x10,0x70); /* select the bler reg */
 524                 state->lastbler=cx24110_readreg(state,0x12)|
 525                         (cx24110_readreg(state,0x13)<<8)|
 526                         (cx24110_readreg(state,0x14)<<16);
 527                 cx24110_writereg(state,0x10,0x20); /* start new count window */
 528         }
 529         *ucblocks = state->lastbler;
 530
 531         return 0;
 532 }
 533
 534 static int cx24110_set_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 535 {
 536         struct cx24110_state *state = fe->demodulator_priv;
 537
 538
 539         if (fe->ops.tuner_ops.set_params) {
 540                 fe->ops.tuner_ops.set_params(fe, p);
 541                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 542         }
 543
 544         cx24110_set_inversion (state, p->inversion);
 545         cx24110_set_fec (state, p->u.qpsk.fec_inner);
 546         cx24110_set_symbolrate (state, p->u.qpsk.symbol_rate);
 547         cx24110_writereg(state,0x04,0x05); /* start aquisition */
 548
 549         return 0;
 550 }
 551
 552 static int cx24110_get_frontend(struct dvb_frontend* fe, struct dvb_frontend_parameters *p)
 553 {
 554         struct cx24110_state *state = fe->demodulator_priv;
 555         s32 afc; unsigned sclk;
 556
 557 /* cannot read back tuner settings (freq). Need to have some private storage */
 558
 559         sclk = cx24110_readreg (state, 0x07) & 0x03;
 560 /* ok, real AFC (FEDR) freq. is afc/2^24*fsamp, fsamp=45/60/80/90MHz.
 561  * Need 64 bit arithmetic. Is thiss possible in the kernel? */
 562         if (sclk==0) sclk=90999000L/2L;
 563         else if (sclk==1) sclk=60666000L;
 564         else if (sclk==2) sclk=80888000L;
 565         else sclk=90999000L;
 566         sclk>>=8;
 567         afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+
 568               ((sclk*cx24110_readreg (state, 0x45))>>8)+
 569               ((sclk*cx24110_readreg (state, 0x46))>>16);
 570
 571         p->frequency += afc;
 572         p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ?
 573                                 INVERSION_ON : INVERSION_OFF;
 574         p->u.qpsk.fec_inner = cx24110_get_fec (state);
 575
 576         return 0;
 577 }
 578
 579 static int cx24110_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
 580 {
 581         struct cx24110_state *state = fe->demodulator_priv;
 582
 583         return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10:0));
 584 }
 585
 586 static void cx24110_release(struct dvb_frontend* fe)
 587 {
 588         struct cx24110_state* state = fe->demodulator_priv;
 589         kfree(state);
 590 }
 591
 592 static struct dvb_frontend_ops cx24110_ops;
 593
 594 struct dvb_frontend* cx24110_attach(const struct cx24110_config* config,
 595                                     struct i2c_adapter* i2c)
 596 {
 597         struct cx24110_state* state = NULL;
 598         int ret;
 599
 600         /* allocate memory for the internal state */
 601         state = kzalloc(sizeof(struct cx24110_state), GFP_KERNEL);
 602         if (state == NULL) goto error;
 603
 604         /* setup the state */
 605         state->config = config;
 606         state->i2c = i2c;
 607         state->lastber = 0;
 608         state->lastbler = 0;
 609         state->lastesn0 = 0;
 610
 611         /* check if the demod is there */
 612         ret = cx24110_readreg(state, 0x00);
 613         if ((ret != 0x5a) && (ret != 0x69)) goto error;
 614
 615         /* create dvb_frontend */
 616         memcpy(&state->frontend.ops, &cx24110_ops, sizeof(struct dvb_frontend_ops));
 617         state->frontend.demodulator_priv = state;
 618         return &state->frontend;
 619
 620 error:
 621         kfree(state);
 622         return NULL;
 623 }
 624
 625 static struct dvb_frontend_ops cx24110_ops = {
 626
 627         .info = {
 628                 .name = "Conexant CX24110 DVB-S",
 629                 .type = FE_QPSK,
 630                 .frequency_min = 950000,
 631                 .frequency_max = 2150000,
 632                 .frequency_stepsize = 1011,  /* kHz for QPSK frontends */
 633                 .frequency_tolerance = 29500,
 634                 .symbol_rate_min = 1000000,
 635                 .symbol_rate_max = 45000000,
 636                 .caps = FE_CAN_INVERSION_AUTO |
 637                         FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
 638                         FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
 639                         FE_CAN_QPSK | FE_CAN_RECOVER
 640         },
 641
 642         .release = cx24110_release,
 643
 644         .init = cx24110_initfe,
 645         .write = _cx24110_pll_write,
 646         .set_frontend = cx24110_set_frontend,
 647         .get_frontend = cx24110_get_frontend,
 648         .read_status = cx24110_read_status,
 649         .read_ber = cx24110_read_ber,
 650         .read_signal_strength = cx24110_read_signal_strength,
 651         .read_snr = cx24110_read_snr,
 652         .read_ucblocks = cx24110_read_ucblocks,
 653
 654         .diseqc_send_master_cmd = cx24110_send_diseqc_msg,
 655         .set_tone = cx24110_set_tone,
 656         .set_voltage = cx24110_set_voltage,
 657         .diseqc_send_burst = cx24110_diseqc_send_burst,
 658 };
 659
 660 module_param(debug, int, 0644);
 661 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 662
 663 MODULE_DESCRIPTION("Conexant CX24110 DVB-S Demodulator driver");
 664 MODULE_AUTHOR("Peter Hettkamp");
 665 MODULE_LICENSE("GPL");
 666
 667 EXPORT_SYMBOL(cx24110_attach);