drivers/media/dvb/frontends/dibx000_common.h

   1 #ifndef DIBX000_COMMON_H
   2 #define DIBX000_COMMON_H
   3
   4 enum dibx000_i2c_interface {
   5         DIBX000_I2C_INTERFACE_TUNER = 0,
   6         DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
   7         DIBX000_I2C_INTERFACE_GPIO_3_4 = 2
   8 };
   9
  10 struct dibx000_i2c_master {
  11 #define DIB3000MC 1
  12 #define DIB7000   2
  13 #define DIB7000P  11
  14 #define DIB7000MC 12
  15 #define DIB8000   13
  16         u16 device_rev;
  17
  18         enum dibx000_i2c_interface selected_interface;
  19
  20 //      struct i2c_adapter  tuner_i2c_adap;
  21         struct i2c_adapter gated_tuner_i2c_adap;
  22
  23         struct i2c_adapter *i2c_adap;
  24         u8 i2c_addr;
  25
  26         u16 base_reg;
  27 };
  28
  29 extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
  30                                    u16 device_rev, struct i2c_adapter *i2c_adap,
  31                                    u8 i2c_addr);
  32 extern struct i2c_adapter *dibx000_get_i2c_adapter(struct dibx000_i2c_master
  33                                                    *mst,
  34                                                    enum dibx000_i2c_interface
  35                                                    intf, int gating);
  36 extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
  37 extern void dibx000_reset_i2c_master(struct dibx000_i2c_master *mst);
  38
  39 #define BAND_LBAND 0x01
  40 #define BAND_UHF   0x02
  41 #define BAND_VHF   0x04
  42 #define BAND_SBAND 0x08
  43 #define BAND_FM    0x10
  44
  45 #define BAND_OF_FREQUENCY(freq_kHz) ( (freq_kHz) <= 115000 ? BAND_FM : \
  46                                                                         (freq_kHz) <= 250000 ? BAND_VHF : \
  47                                                                         (freq_kHz) <= 863000 ? BAND_UHF : \
  48                                                                         (freq_kHz) <= 2000000 ? BAND_LBAND : BAND_SBAND )
  49
  50 struct dibx000_agc_config {
  51         /* defines the capabilities of this AGC-setting - using the BAND_-defines */
  52         u8 band_caps;
  53
  54         u16 setup;
  55
  56         u16 inv_gain;
  57         u16 time_stabiliz;
  58
  59         u8 alpha_level;
  60         u16 thlock;
  61
  62         u8 wbd_inv;
  63         u16 wbd_ref;
  64         u8 wbd_sel;
  65         u8 wbd_alpha;
  66
  67         u16 agc1_max;
  68         u16 agc1_min;
  69         u16 agc2_max;
  70         u16 agc2_min;
  71
  72         u8 agc1_pt1;
  73         u8 agc1_pt2;
  74         u8 agc1_pt3;
  75
  76         u8 agc1_slope1;
  77         u8 agc1_slope2;
  78
  79         u8 agc2_pt1;
  80         u8 agc2_pt2;
  81
  82         u8 agc2_slope1;
  83         u8 agc2_slope2;
  84
  85         u8 alpha_mant;
  86         u8 alpha_exp;
  87
  88         u8 beta_mant;
  89         u8 beta_exp;
  90
  91         u8 perform_agc_softsplit;
  92
  93         struct {
  94                 u16 min;
  95                 u16 max;
  96                 u16 min_thres;
  97                 u16 max_thres;
  98         } split;
  99 };
 100
 101 struct dibx000_bandwidth_config {
 102         u32 internal;
 103         u32 sampling;
 104
 105         u8 pll_prediv;
 106         u8 pll_ratio;
 107         u8 pll_range;
 108         u8 pll_reset;
 109         u8 pll_bypass;
 110
 111         u8 enable_refdiv;
 112         u8 bypclk_div;
 113         u8 IO_CLK_en_core;
 114         u8 ADClkSrc;
 115         u8 modulo;
 116
 117         u16 sad_cfg;
 118
 119         u32 ifreq;
 120         u32 timf;
 121
 122         u32 xtal_hz;
 123 };
 124
 125 enum dibx000_adc_states {
 126         DIBX000_SLOW_ADC_ON = 0,
 127         DIBX000_SLOW_ADC_OFF,
 128         DIBX000_ADC_ON,
 129         DIBX000_ADC_OFF,
 130         DIBX000_VBG_ENABLE,
 131         DIBX000_VBG_DISABLE,
 132 };
 133
 134 #define BANDWIDTH_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ  ? 8000 : \
 135                              (v) == BANDWIDTH_7_MHZ  ? 7000 : \
 136                              (v) == BANDWIDTH_6_MHZ  ? 6000 : 8000 )
 137
 138 #define BANDWIDTH_TO_INDEX(v) ( \
 139         (v) == 8000 ? BANDWIDTH_8_MHZ : \
 140                 (v) == 7000 ? BANDWIDTH_7_MHZ : \
 141                 (v) == 6000 ? BANDWIDTH_6_MHZ : BANDWIDTH_8_MHZ )
 142
 143 /* Chip output mode. */
 144 #define OUTMODE_HIGH_Z              0
 145 #define OUTMODE_MPEG2_PAR_GATED_CLK 1
 146 #define OUTMODE_MPEG2_PAR_CONT_CLK  2
 147 #define OUTMODE_MPEG2_SERIAL        7
 148 #define OUTMODE_DIVERSITY           4
 149 #define OUTMODE_MPEG2_FIFO          5
 150 #define OUTMODE_ANALOG_ADC          6
 151
 152 #endif