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First Support on Ginger and OMAP TI
[linux-ginger.git] / drivers / staging / otus / hal / hpmain.c
blob94f9cbbbdefce6cb1fd0a2e66377762f71f272fe
1 /*
2 * Copyright (c) 2007-2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include "../80211core/cprecomp.h"
17 #include "hpani.h"
18 #include "hpusb.h"
19 #include "otus.ini"
20
21 extern const u32_t zcFwImage[];
22 extern const u32_t zcFwImageSize;
23 extern const u32_t zcDKFwImage[];
24 extern const u32_t zcDKFwImageSize;
25 extern const u32_t zcFwImageSPI[];
26 extern const u32_t zcFwImageSPISize;
27
28 #ifdef ZM_OTUS_LINUX_PHASE_2
29 extern const u32_t zcFwBufImage[];
30 extern const u32_t zcFwBufImageSize;
31 extern const u32_t zcP2FwImage[];
32 extern const u32_t zcP2FwImageSize;
33 #endif
34 extern void zfInitCmdQueue(zdev_t* dev);
35 extern u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen,
36 u16_t src, u8_t* buf);
37 extern void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen);
38 extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
39 extern u16_t zfFlushDelayWrite(zdev_t* dev);
40 extern void zfUsbInit(zdev_t* dev);
41 extern u16_t zfFirmwareDownload(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
42 extern u16_t zfFirmwareDownloadNotJump(zdev_t* dev, u32_t* fw, u32_t len, u32_t offset);
43 extern void zfUsbFree(zdev_t* dev);
44 extern u16_t zfCwmIsExtChanBusy(u32_t ctlBusy, u32_t extBusy);
45 extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy);
46
47 /* Prototypes */
48 void zfInitRf(zdev_t* dev, u32_t frequency);
49 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40);
50 void zfInitMac(zdev_t* dev);
51
52 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset);
53 void zfInitPowerCal(zdev_t* dev);
54
55 #ifdef ZM_DRV_INIT_USB_MODE
56 void zfInitUsbMode(zdev_t* dev);
57 u16_t zfHpUsbReset(zdev_t* dev);
58 #endif
59
60 /* Bank 0 1 2 3 5 6 7 */
61 void zfSetRfRegs(zdev_t* dev, u32_t frequency);
62 /* Bank 4 */
63 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
64 u8_t extOffset);
65 /* Get param for turnoffdyn */
66 void zfGetHwTurnOffdynParam(zdev_t* dev,
67 u32_t frequency, u8_t bw40, u8_t extOffset,
68 int* delta_slope_coeff_exp,
69 int* delta_slope_coeff_man,
70 int* delta_slope_coeff_exp_shgi,
71 int* delta_slope_coeff_man_shgi);
72
73 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency);
74 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value);
75
76
77
78 #define zm_hp_priv(x) (((struct zsHpPriv*)wd->hpPrivate)->x)
79 static struct zsHpPriv zgHpPriv;
80
81 #define ZM_FIRMWARE_WLAN_ADDR 0x200000
82 #define ZM_FIRMWARE_SPI_ADDR 0x114000
83 /* 0: real chip 1: FPGA test */
84 #define ZM_FPGA_PHY 0
85
86 #define reg_write(addr, val) zfDelayWriteInternalReg(dev, addr+0x1bc000, val)
87 #define zm_min(A, B) ((A>B)? B:A)
88
89
90 /******************** Intialization ********************/
91 u16_t zfHpInit(zdev_t* dev, u32_t frequency)
92 {
93 u16_t ret;
94 zmw_get_wlan_dev(dev);
95
96 /* Initializa HAL Plus private variables */
97 wd->hpPrivate = &zgHpPriv;
98
99 ((struct zsHpPriv*)wd->hpPrivate)->halCapability = ZM_HP_CAP_11N;
100
101 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = 0;
102 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = 0;
103 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = 0;
104
105 ((struct zsHpPriv*)wd->hpPrivate)->disableDfsCh = 0;
106
107 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0] = 1;
108 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[1] = 1;
109 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
110 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
111
112 ((struct zsHpPriv*)wd->hpPrivate)->slotType = 1;
113 ((struct zsHpPriv*)wd->hpPrivate)->aggPktNum = 0x10000a;
114
115 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageIndex = 0;
116
117
118 ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq = 0;
119 #ifdef ZM_OTUS_RX_STREAM_MODE
120 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
121 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
122 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
123 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
124 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
125 #endif
126
127 ((struct zsHpPriv*)wd->hpPrivate)->enableBBHeavyClip = 1;
128 ((struct zsHpPriv*)wd->hpPrivate)->hwBBHeavyClip = 1; // force enable 8107
129 ((struct zsHpPriv*)wd->hpPrivate)->doBBHeavyClip = 0;
130 ((struct zsHpPriv*)wd->hpPrivate)->setValueHeavyClip = 0;
131
132
133 /* Initialize driver core */
134 zfInitCmdQueue(dev);
135
136 /* Initialize USB */
137 zfUsbInit(dev);
138
139 #if ZM_SW_LOOP_BACK != 1
140
141 /* TODO : [Download FW] */
142 if (wd->modeMDKEnable)
143 {
144 /* download the MDK firmware */
145 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcDKFwImage,
146 (u32_t)zcDKFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
147 {
148 /* TODO : exception handling */
149 //return 1;
150 }
151 }
152 else
153 {
154 #ifndef ZM_OTUS_LINUX_PHASE_2
155 /* download the normal firmware */
156 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
157 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
158 {
159 /* TODO : exception handling */
160 //return 1;
161 }
162 #else
163
164 // 1-PH fw: ReadMac() store some global variable
165 if ((ret = zfFirmwareDownloadNotJump(dev, (u32_t*)zcFwBufImage,
166 (u32_t)zcFwBufImageSize, 0x102800)) != ZM_SUCCESS)
167 {
168 DbgPrint("Dl zcFwBufImage failed!");
169 }
170
171 zfwSleep(dev, 1000);
172
173 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
174 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
175 {
176 DbgPrint("Dl zcFwBufImage failed!");
177 }
178 #endif
179 }
180 #endif
181
182 #ifdef ZM_DRV_INIT_USB_MODE
183 /* Init USB Mode */
184 zfInitUsbMode(dev);
185
186 /* Do the USB Reset */
187 zfHpUsbReset(dev);
188 #endif
189
190 /* Register setting */
191 /* ZM_DRIVER_MODEL_TYPE_MDK
192 * 1=>for MDK, disable init RF, PHY, and MAC,
193 * 0=>normal init
194 */
195 //#if ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1))
196 #if ZM_SW_LOOP_BACK != 1
197 if(!wd->modeMDKEnable)
198 {
199 /* Init MAC */
200 zfInitMac(dev);
201
202 #if ZM_FW_LOOP_BACK != 1
203 /* Init PHY */
204 zfInitPhy(dev, frequency, 0);
205
206 /* Init RF */
207 zfInitRf(dev, frequency);
208
209 #if ZM_FPGA_PHY == 0
210 /* BringUp issue */
211 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
212 //zfFlushDelayWrite(dev);
213 #endif
214
215 #endif /* end of ZM_FW_LOOP_BACK != 1 */
216 }
217 #endif /* end of ((ZM_SW_LOOP_BACK != 1) && (ZM_DRIVER_MODEL_TYPE_MDK !=1)) */
218
219 zfHpEchoCommand(dev, 0xAABBCCDD);
220
221 return 0;
222 }
223
224
225 u16_t zfHpReinit(zdev_t* dev, u32_t frequency)
226 {
227 u16_t ret;
228 zmw_get_wlan_dev(dev);
229
230 ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 1;
231
232 ((struct zsHpPriv*)wd->hpPrivate)->strongRSSI = 0;
233 ((struct zsHpPriv*)wd->hpPrivate)->rxStrongRSSI = 0;
234
235 #ifdef ZM_OTUS_RX_STREAM_MODE
236 if (((struct zsHpPriv*)wd->hpPrivate)->remainBuf != NULL)
237 {
238 zfwBufFree(dev, ((struct zsHpPriv*)wd->hpPrivate)->remainBuf, 0);
239 }
240 ((struct zsHpPriv*)wd->hpPrivate)->remainBuf = NULL;
241 ((struct zsHpPriv*)wd->hpPrivate)->usbRxRemainLen = 0;
242 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPktLen = 0;
243 ((struct zsHpPriv*)wd->hpPrivate)->usbRxPadLen = 0;
244 ((struct zsHpPriv*)wd->hpPrivate)->usbRxTransferLen = 0;
245 #endif
246
247 zfInitCmdQueue(dev);
248 zfCoreReinit(dev);
249
250 #ifndef ZM_OTUS_LINUX_PHASE_2
251 /* Download firmware */
252 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
253 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
254 {
255 /* TODO : exception handling */
256 //return 1;
257 }
258 #else
259 if ((ret = zfFirmwareDownload(dev, (u32_t*)zcP2FwImage,
260 (u32_t)zcP2FwImageSize, ZM_FIRMWARE_WLAN_ADDR)) != ZM_SUCCESS)
261 {
262 /* TODO : exception handling */
263 //return 1;
264 }
265 #endif
266
267 #ifdef ZM_DRV_INIT_USB_MODE
268 /* Init USB Mode */
269 zfInitUsbMode(dev);
270
271 /* Do the USB Reset */
272 zfHpUsbReset(dev);
273 #endif
274
275 /* Init MAC */
276 zfInitMac(dev);
277
278 /* Init PHY */
279 zfInitPhy(dev, frequency, 0);
280 /* Init RF */
281 zfInitRf(dev, frequency);
282
283 #if ZM_FPGA_PHY == 0
284 /* BringUp issue */
285 //zfDelayWriteInternalReg(dev, 0x9800+0x1bc000, 0x10000007);
286 //zfFlushDelayWrite(dev);
287 #endif
288
289 zfHpEchoCommand(dev, 0xAABBCCDD);
290
291 return 0;
292 }
293
294
295 u16_t zfHpRelease(zdev_t* dev)
296 {
297 /* Free USB resource */
298 zfUsbFree(dev);
299
300 return 0;
301 }
302
303 /* MDK mode setting for dontRetransmit */
304 void zfHpConfigFM(zdev_t* dev, u32_t RxMaxSize, u32_t DontRetransmit)
305 {
306 u32_t cmd[3];
307 u16_t ret;
308
309 cmd[0] = 8 | (ZM_CMD_CONFIG << 8);
310 cmd[1] = RxMaxSize; /* zgRxMaxSize */
311 cmd[2] = DontRetransmit; /* zgDontRetransmit */
312
313 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, 0);
314 }
315
316 const u8_t zcXpdToPd[16] =
317 {
318 /* 0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8, 0x9, 0xA, 0xB, 0xC, 0xD, 0xE, 0xF */
319 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2, 0x2, 0x3, 0x7, 0x2, 0xB, 0x2, 0x2, 0x2
320 };
321
322 /******************** RF and PHY ********************/
323
324 void zfInitPhy(zdev_t* dev, u32_t frequency, u8_t bw40)
325 {
326 u16_t i, j, k;
327 u16_t entries;
328 u16_t modesIndex = 0;
329 u16_t freqIndex = 0;
330 u32_t tmp, tmp1;
331 struct zsHpPriv* hpPriv;
332
333 u32_t eepromBoardData[15][6] = {
334 /* Register A-20 A-20/40 G-20/40 G-20 G-Turbo */
335 {0x9964, 0, 0, 0, 0, 0},
336 {0x9960, 0, 0, 0, 0, 0},
337 {0xb960, 0, 0, 0, 0, 0},
338 {0x9844, 0, 0, 0, 0, 0},
339 {0x9850, 0, 0, 0, 0, 0},
340 {0x9834, 0, 0, 0, 0, 0},
341 {0x9828, 0, 0, 0, 0, 0},
342 {0xc864, 0, 0, 0, 0, 0},
343 {0x9848, 0, 0, 0, 0, 0},
344 {0xb848, 0, 0, 0, 0, 0},
345 {0xa20c, 0, 0, 0, 0, 0},
346 {0xc20c, 0, 0, 0, 0, 0},
347 {0x9920, 0, 0, 0, 0, 0},
348 {0xb920, 0, 0, 0, 0, 0},
349 {0xa258, 0, 0, 0, 0, 0},
350 };
351
352 zmw_get_wlan_dev(dev);
353 hpPriv=wd->hpPrivate;
354
355 /* #1 Save the initial value of the related RIFS register settings */
356 //((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy++;
357
358 /*
359 * Setup the indices for the next set of register array writes
360 * PHY mode is static20 / 2040
361 * Frequency is 2.4GHz (B) / 5GHz (A)
362 */
363 if ( frequency > ZM_CH_G_14 )
364 {
365 /* 5GHz */
366 freqIndex = 1;
367 if (bw40)
368 {
369 modesIndex = 2;
370 zm_debug_msg0("init ar5416Modes in 2: A-20/40");
371 }
372 else
373 {
374 modesIndex = 1;
375 zm_debug_msg0("init ar5416Modes in 1: A-20");
376 }
377 }
378 else
379 {
380 /* 2.4GHz */
381 freqIndex = 2;
382 if (bw40)
383 {
384 modesIndex = 3;
385 zm_debug_msg0("init ar5416Modes in 3: G-20/40");
386 }
387 else
388 {
389 modesIndex = 4;
390 zm_debug_msg0("init ar5416Modes in 4: G-20");
391 }
392 }
393
394
395 #if ZM_FPGA_PHY == 1
396 /* Starting External Hainan Register Initialization */
397 /* TODO: */
398
399 zfwSleep(dev, 10);
400 #endif
401
402 /*
403 *Set correct Baseband to analog shift setting to access analog chips.
404 */
405 //reg_write(PHY_BASE, 0x00000007);
406 // reg_write(0x9800, 0x00000007);
407
408 /*
409 * Write addac shifts
410 */
411 // do this in firmware
412
413
414
415 /* Zeroize board data */
416 for (j=0; j<15; j++)
417 {
418 for (k=1; k<=4; k++)
419 {
420 eepromBoardData[j][k] = 0;
421 }
422 }
423 /*
424 * Register setting by mode
425 */
426
427 entries = sizeof(ar5416Modes) / sizeof(*ar5416Modes);
428 zm_msg1_scan(ZM_LV_2, "Modes register setting entries=", entries);
429 for (i=0; i<entries; i++)
430 {
431 #if 0
432 if ( ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit && (ar5416Modes[i][0] == 0xa27c) )
433 {
434 /* Force disable CR671 bit20 / 7823 */
435 /* The bug has to do with the polarity of the pdadc offset calibration. There */
436 /* is an initial calibration that is OK, and there is a continuous */
437 /* calibration that updates the pddac with the wrong polarity. Fortunately */
438 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
439
440 reg_write(ar5416Modes[i][0], (ar5416Modes[i][modesIndex]& 0xffefffff) );
441 ((struct zsHpPriv*)wd->hpPrivate)->hwNotFirstInit = 1;
442 }
443 else
444 {
445 #endif
446 /* FirstTime Init or not 0xa27c(CR671) */
447 reg_write(ar5416Modes[i][0], ar5416Modes[i][modesIndex]);
448 // }
449 /* Initialize board data */
450 for (j=0; j<15; j++)
451 {
452 if (ar5416Modes[i][0] == eepromBoardData[j][0])
453 {
454 for (k=1; k<=4; k++)
455 {
456 eepromBoardData[j][k] = ar5416Modes[i][k];
457 }
458 }
459 }
460 /* #1 Save the initial value of the related RIFS register settings */
461 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
462 {
463 switch(ar5416Modes[i][0])
464 {
465 case 0x9850 :
466 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = ar5416Modes[i][modesIndex];
467 break;
468 case 0x985c :
469 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = ar5416Modes[i][modesIndex];
470 break;
471 case 0x9860 :
472 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = ar5416Modes[i][modesIndex];
473 break;
474 case 0x9918 :
475 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = ar5416Modes[i][modesIndex];
476 break;
477 case 0x99ec :
478 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = ar5416Modes[i][modesIndex];
479 break;
480 case 0xa388 :
481 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = ar5416Modes[i][modesIndex];
482 default :
483 break;
484 }
485 }
486 }
487 #if 0
488 zfFlushDelayWrite(dev);
489
490 /*
491 * Common Register setting
492 */
493 entries = sizeof(ar5416Common) / sizeof(*ar5416Common);
494 for (i=0; i<entries; i++)
495 {
496 reg_write(ar5416Common[i][0], ar5416Common[i][1]);
497 }
498 zfFlushDelayWrite(dev);
499
500 /*
501 * RF Gain setting by freqIndex
502 */
503 entries = sizeof(ar5416BB_RfGain) / sizeof(*ar5416BB_RfGain);
504 for (i=0; i<entries; i++)
505 {
506 reg_write(ar5416BB_RfGain[i][0], ar5416BB_RfGain[i][freqIndex]);
507 }
508 zfFlushDelayWrite(dev);
509
510 /*
511 * Moved ar5416InitChainMask() here to ensure the swap bit is set before
512 * the pdadc table is written. Swap must occur before any radio dependent
513 * replicated register access. The pdadc curve addressing in particular
514 * depends on the consistent setting of the swap bit.
515 */
516 //ar5416InitChainMask(pDev);
517
518 /* Setup the transmit power values. */
519 // TODO
520 #endif
521
522 /* Update 5G board data */
523 //Ant control common
524 tmp = hpPriv->eepromImage[0x100+0x144*2/4];
525 eepromBoardData[0][1] = tmp;
526 eepromBoardData[0][2] = tmp;
527 //Ant control chain 0
528 tmp = hpPriv->eepromImage[0x100+0x140*2/4];
529 eepromBoardData[1][1] = tmp;
530 eepromBoardData[1][2] = tmp;
531 //Ant control chain 2
532 tmp = hpPriv->eepromImage[0x100+0x142*2/4];
533 eepromBoardData[2][1] = tmp;
534 eepromBoardData[2][2] = tmp;
535 //SwSettle
536 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
537 tmp = (tmp >> 16) & 0x7f;
538 eepromBoardData[3][1] &= (~((u32_t)0x3f80));
539 eepromBoardData[3][1] |= (tmp << 7);
540 #if 0
541 //swSettleHt40
542 tmp = hpPriv->eepromImage[0x100+0x158*2/4];
543 tmp = (tmp) & 0x7f;
544 eepromBoardData[3][2] &= (~((u32_t)0x3f80));
545 eepromBoardData[3][2] |= (tmp << 7);
546 #endif
547 //adcDesired, pdaDesired
548 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
549 tmp = (tmp >> 24);
550 tmp1 = hpPriv->eepromImage[0x100+0x14a*2/4];
551 tmp1 = tmp1 & 0xff;
552 tmp = tmp + (tmp1<<8);
553 eepromBoardData[4][1] &= (~((u32_t)0xffff));
554 eepromBoardData[4][1] |= tmp;
555 eepromBoardData[4][2] &= (~((u32_t)0xffff));
556 eepromBoardData[4][2] |= tmp;
557 //TxEndToXpaOff, TxFrameToXpaOn
558 tmp = hpPriv->eepromImage[0x100+0x14a*2/4];
559 tmp = (tmp >> 24) & 0xff;
560 tmp1 = hpPriv->eepromImage[0x100+0x14c*2/4];
561 tmp1 = (tmp1 >> 8) & 0xff;
562 tmp = (tmp<<24) + (tmp<<16) + (tmp1<<8) + tmp1;
563 eepromBoardData[5][1] = tmp;
564 eepromBoardData[5][2] = tmp;
565 //TxEnaToRxOm
566 tmp = hpPriv->eepromImage[0x100+0x14c*2/4] & 0xff;
567 eepromBoardData[6][1] &= (~((u32_t)0xff0000));
568 eepromBoardData[6][1] |= (tmp<<16);
569 eepromBoardData[6][2] &= (~((u32_t)0xff0000));
570 eepromBoardData[6][2] |= (tmp<<16);
571 //Thresh62
572 tmp = hpPriv->eepromImage[0x100+0x14c*2/4];
573 tmp = (tmp >> 16) & 0x7f;
574 eepromBoardData[7][1] &= (~((u32_t)0x7f000));
575 eepromBoardData[7][1] |= (tmp<<12);
576 eepromBoardData[7][2] &= (~((u32_t)0x7f000));
577 eepromBoardData[7][2] |= (tmp<<12);
578 //TxRxAtten chain_0
579 tmp = hpPriv->eepromImage[0x100+0x146*2/4];
580 tmp = (tmp >> 24) & 0x3f;
581 eepromBoardData[8][1] &= (~((u32_t)0x3f000));
582 eepromBoardData[8][1] |= (tmp<<12);
583 eepromBoardData[8][2] &= (~((u32_t)0x3f000));
584 eepromBoardData[8][2] |= (tmp<<12);
585 //TxRxAtten chain_2
586 tmp = hpPriv->eepromImage[0x100+0x148*2/4] & 0x3f;
587 eepromBoardData[9][1] &= (~((u32_t)0x3f000));
588 eepromBoardData[9][1] |= (tmp<<12);
589 eepromBoardData[9][2] &= (~((u32_t)0x3f000));
590 eepromBoardData[9][2] |= (tmp<<12);
591 //TxRxMargin chain_0
592 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
593 tmp = (tmp >> 8) & 0x3f;
594 eepromBoardData[10][1] &= (~((u32_t)0xfc0000));
595 eepromBoardData[10][1] |= (tmp<<18);
596 eepromBoardData[10][2] &= (~((u32_t)0xfc0000));
597 eepromBoardData[10][2] |= (tmp<<18);
598 //TxRxMargin chain_2
599 tmp = hpPriv->eepromImage[0x100+0x148*2/4];
600 tmp = (tmp >> 16) & 0x3f;
601 eepromBoardData[11][1] &= (~((u32_t)0xfc0000));
602 eepromBoardData[11][1] |= (tmp<<18);
603 eepromBoardData[11][2] &= (~((u32_t)0xfc0000));
604 eepromBoardData[11][2] |= (tmp<<18);
605 //iqCall chain_0, iqCallQ chain_0
606 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
607 tmp = (tmp >> 24) & 0x3f;
608 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
609 tmp1 = (tmp1 >> 8) & 0x1f;
610 tmp = (tmp<<5) + tmp1;
611 eepromBoardData[12][1] &= (~((u32_t)0x7ff));
612 eepromBoardData[12][1] |= (tmp);
613 eepromBoardData[12][2] &= (~((u32_t)0x7ff));
614 eepromBoardData[12][2] |= (tmp);
615 //iqCall chain_2, iqCallQ chain_2
616 tmp = hpPriv->eepromImage[0x100+0x150*2/4];
617 tmp = tmp & 0x3f;
618 tmp1 = hpPriv->eepromImage[0x100+0x150*2/4];
619 tmp1 = (tmp1 >> 16) & 0x1f;
620 tmp = (tmp<<5) + tmp1;
621 eepromBoardData[13][1] &= (~((u32_t)0x7ff));
622 eepromBoardData[13][1] |= (tmp);
623 eepromBoardData[13][2] &= (~((u32_t)0x7ff));
624 eepromBoardData[13][2] |= (tmp);
625 //bsw_Margin chain_0
626 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
627 tmp = (tmp >> 16) & 0xf;
628 eepromBoardData[10][1] &= (~((u32_t)0x3c00));
629 eepromBoardData[10][1] |= (tmp << 10);
630 eepromBoardData[10][2] &= (~((u32_t)0x3c00));
631 eepromBoardData[10][2] |= (tmp << 10);
632 //xpd gain mask
633 tmp = hpPriv->eepromImage[0x100+0x14e*2/4];
634 tmp = (tmp >> 8) & 0xf;
635 eepromBoardData[14][1] &= (~((u32_t)0xf0000));
636 eepromBoardData[14][1] |= (zcXpdToPd[tmp] << 16);
637 eepromBoardData[14][2] &= (~((u32_t)0xf0000));
638 eepromBoardData[14][2] |= (zcXpdToPd[tmp] << 16);
639 #if 0
640 //bsw_Atten chain_0
641 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
642 tmp = (tmp) & 0x1f;
643 eepromBoardData[10][1] &= (~((u32_t)0x1f));
644 eepromBoardData[10][1] |= (tmp);
645 eepromBoardData[10][2] &= (~((u32_t)0x1f));
646 eepromBoardData[10][2] |= (tmp);
647 //bsw_Margin chain_2
648 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
649 tmp = (tmp >> 24) & 0xf;
650 eepromBoardData[11][1] &= (~((u32_t)0x3c00));
651 eepromBoardData[11][1] |= (tmp << 10);
652 eepromBoardData[11][2] &= (~((u32_t)0x3c00));
653 eepromBoardData[11][2] |= (tmp << 10);
654 //bsw_Atten chain_2
655 tmp = hpPriv->eepromImage[0x100+0x156*2/4];
656 tmp = (tmp >> 8) & 0x1f;
657 eepromBoardData[11][1] &= (~((u32_t)0x1f));
658 eepromBoardData[11][1] |= (tmp);
659 eepromBoardData[11][2] &= (~((u32_t)0x1f));
660 eepromBoardData[11][2] |= (tmp);
661 #endif
662
663 /* Update 2.4G board data */
664 //Ant control common
665 tmp = hpPriv->eepromImage[0x100+0x170*2/4];
666 tmp = tmp >> 24;
667 tmp1 = hpPriv->eepromImage[0x100+0x172*2/4];
668 tmp = tmp + (tmp1 << 8);
669 eepromBoardData[0][3] = tmp;
670 eepromBoardData[0][4] = tmp;
671 //Ant control chain 0
672 tmp = hpPriv->eepromImage[0x100+0x16c*2/4];
673 tmp = tmp >> 24;
674 tmp1 = hpPriv->eepromImage[0x100+0x16e*2/4];
675 tmp = tmp + (tmp1 << 8);
676 eepromBoardData[1][3] = tmp;
677 eepromBoardData[1][4] = tmp;
678 //Ant control chain 2
679 tmp = hpPriv->eepromImage[0x100+0x16e*2/4];
680 tmp = tmp >> 24;
681 tmp1 = hpPriv->eepromImage[0x100+0x170*2/4];
682 tmp = tmp + (tmp1 << 8);
683 eepromBoardData[2][3] = tmp;
684 eepromBoardData[2][4] = tmp;
685 //SwSettle
686 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
687 tmp = (tmp >> 8) & 0x7f;
688 eepromBoardData[3][4] &= (~((u32_t)0x3f80));
689 eepromBoardData[3][4] |= (tmp << 7);
690 #if 0
691 //swSettleHt40
692 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
693 tmp = (tmp >> 24) & 0x7f;
694 eepromBoardData[3][3] &= (~((u32_t)0x3f80));
695 eepromBoardData[3][3] |= (tmp << 7);
696 #endif
697 //adcDesired, pdaDesired
698 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
699 tmp = (tmp >> 16) & 0xff;
700 tmp1 = hpPriv->eepromImage[0x100+0x176*2/4];
701 tmp1 = tmp1 >> 24;
702 tmp = tmp + (tmp1<<8);
703 eepromBoardData[4][3] &= (~((u32_t)0xffff));
704 eepromBoardData[4][3] |= tmp;
705 eepromBoardData[4][4] &= (~((u32_t)0xffff));
706 eepromBoardData[4][4] |= tmp;
707 //TxEndToXpaOff, TxFrameToXpaOn
708 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
709 tmp = (tmp >> 16) & 0xff;
710 tmp1 = hpPriv->eepromImage[0x100+0x17a*2/4];
711 tmp1 = tmp1 & 0xff;
712 tmp = (tmp << 24) + (tmp << 16) + (tmp1 << 8) + tmp1;
713 eepromBoardData[5][3] = tmp;
714 eepromBoardData[5][4] = tmp;
715 //TxEnaToRxOm
716 tmp = hpPriv->eepromImage[0x100+0x178*2/4];
717 tmp = (tmp >> 24);
718 eepromBoardData[6][3] &= (~((u32_t)0xff0000));
719 eepromBoardData[6][3] |= (tmp<<16);
720 eepromBoardData[6][4] &= (~((u32_t)0xff0000));
721 eepromBoardData[6][4] |= (tmp<<16);
722 //Thresh62
723 tmp = hpPriv->eepromImage[0x100+0x17a*2/4];
724 tmp = (tmp >> 8) & 0x7f;
725 eepromBoardData[7][3] &= (~((u32_t)0x7f000));
726 eepromBoardData[7][3] |= (tmp<<12);
727 eepromBoardData[7][4] &= (~((u32_t)0x7f000));
728 eepromBoardData[7][4] |= (tmp<<12);
729 //TxRxAtten chain_0
730 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
731 tmp = (tmp >> 16) & 0x3f;
732 eepromBoardData[8][3] &= (~((u32_t)0x3f000));
733 eepromBoardData[8][3] |= (tmp<<12);
734 eepromBoardData[8][4] &= (~((u32_t)0x3f000));
735 eepromBoardData[8][4] |= (tmp<<12);
736 //TxRxAtten chain_2
737 tmp = hpPriv->eepromImage[0x100+0x174*2/4];
738 tmp = (tmp >> 24) & 0x3f;
739 eepromBoardData[9][3] &= (~((u32_t)0x3f000));
740 eepromBoardData[9][3] |= (tmp<<12);
741 eepromBoardData[9][4] &= (~((u32_t)0x3f000));
742 eepromBoardData[9][4] |= (tmp<<12);
743 //TxRxMargin chain_0
744 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
745 tmp = (tmp) & 0x3f;
746 eepromBoardData[10][3] &= (~((u32_t)0xfc0000));
747 eepromBoardData[10][3] |= (tmp<<18);
748 eepromBoardData[10][4] &= (~((u32_t)0xfc0000));
749 eepromBoardData[10][4] |= (tmp<<18);
750 //TxRxMargin chain_2
751 tmp = hpPriv->eepromImage[0x100+0x176*2/4];
752 tmp = (tmp >> 8) & 0x3f;
753 eepromBoardData[11][3] &= (~((u32_t)0xfc0000));
754 eepromBoardData[11][3] |= (tmp<<18);
755 eepromBoardData[11][4] &= (~((u32_t)0xfc0000));
756 eepromBoardData[11][4] |= (tmp<<18);
757 //iqCall chain_0, iqCallQ chain_0
758 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
759 tmp = (tmp >> 16) & 0x3f;
760 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
761 tmp1 = (tmp1) & 0x1f;
762 tmp = (tmp<<5) + tmp1;
763 eepromBoardData[12][3] &= (~((u32_t)0x7ff));
764 eepromBoardData[12][3] |= (tmp);
765 eepromBoardData[12][4] &= (~((u32_t)0x7ff));
766 eepromBoardData[12][4] |= (tmp);
767 //iqCall chain_2, iqCallQ chain_2
768 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
769 tmp = (tmp>>24) & 0x3f;
770 tmp1 = hpPriv->eepromImage[0x100+0x17e*2/4];
771 tmp1 = (tmp1 >> 8) & 0x1f;
772 tmp = (tmp<<5) + tmp1;
773 eepromBoardData[13][3] &= (~((u32_t)0x7ff));
774 eepromBoardData[13][3] |= (tmp);
775 eepromBoardData[13][4] &= (~((u32_t)0x7ff));
776 eepromBoardData[13][4] |= (tmp);
777 //xpd gain mask
778 tmp = hpPriv->eepromImage[0x100+0x17c*2/4];
779 tmp = tmp & 0xf;
780 DbgPrint("xpd=0x%x, pd=0x%x\n", tmp, zcXpdToPd[tmp]);
781 eepromBoardData[14][3] &= (~((u32_t)0xf0000));
782 eepromBoardData[14][3] |= (zcXpdToPd[tmp] << 16);
783 eepromBoardData[14][4] &= (~((u32_t)0xf0000));
784 eepromBoardData[14][4] |= (zcXpdToPd[tmp] << 16);
785 #if 0
786 //bsw_Margin chain_0
787 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
788 tmp = (tmp >> 8) & 0xf;
789 eepromBoardData[10][3] &= (~((u32_t)0x3c00));
790 eepromBoardData[10][3] |= (tmp << 10);
791 eepromBoardData[10][4] &= (~((u32_t)0x3c00));
792 eepromBoardData[10][4] |= (tmp << 10);
793 //bsw_Atten chain_0
794 tmp = hpPriv->eepromImage[0x100+0x182*2/4];
795 tmp = (tmp>>24) & 0x1f;
796 eepromBoardData[10][3] &= (~((u32_t)0x1f));
797 eepromBoardData[10][3] |= (tmp);
798 eepromBoardData[10][4] &= (~((u32_t)0x1f));
799 eepromBoardData[10][4] |= (tmp);
800 //bsw_Margin chain_2
801 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
802 tmp = (tmp >> 16) & 0xf;
803 eepromBoardData[11][3] &= (~((u32_t)0x3c00));
804 eepromBoardData[11][3] |= (tmp << 10);
805 eepromBoardData[11][4] &= (~((u32_t)0x3c00));
806 eepromBoardData[11][4] |= (tmp << 10);
807 //bsw_Atten chain_2
808 tmp = hpPriv->eepromImage[0x100+0x184*2/4];
809 tmp = (tmp) & 0x1f;
810 eepromBoardData[11][3] &= (~((u32_t)0x1f));
811 eepromBoardData[11][3] |= (tmp);
812 eepromBoardData[11][4] &= (~((u32_t)0x1f));
813 eepromBoardData[11][4] |= (tmp);
814 #endif
815
816 #if 0
817 for (j=0; j<14; j++)
818 {
819 DbgPrint("%04x, %08x, %08x, %08x, %08x\n", eepromBoardData[j][0], eepromBoardData[j][1], eepromBoardData[j][2], eepromBoardData[j][3], eepromBoardData[j][4]);
820 }
821 #endif
822
823 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
824 {
825 /* Update board data to registers */
826 for (j=0; j<15; j++)
827 {
828 reg_write(eepromBoardData[j][0], eepromBoardData[j][modesIndex]);
829
830 /* #1 Save the initial value of the related RIFS register settings */
831 //if( ((struct zsHpPriv*)wd->hpPrivate)->isInitialPhy == 1 )
832 {
833 switch(eepromBoardData[j][0])
834 {
835 case 0x9850 :
836 ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize = eepromBoardData[j][modesIndex];
837 break;
838 case 0x985c :
839 ((struct zsHpPriv*)wd->hpPrivate)->initAGC = eepromBoardData[j][modesIndex];
840 break;
841 case 0x9860 :
842 ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl = eepromBoardData[j][modesIndex];
843 break;
844 case 0x9918 :
845 ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay = eepromBoardData[j][modesIndex];
846 break;
847 case 0x99ec :
848 ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams = eepromBoardData[j][modesIndex];
849 break;
850 case 0xa388 :
851 ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl = eepromBoardData[j][modesIndex];
852 default :
853 break;
854 }
855 }
856 }
857 } /* if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE */
858
859
860 /* Bringup issue : force tx gain */
861 //reg_write(0xa258, 0x0cc65381);
862 //reg_write(0xa274, 0x0a1a7c15);
863 zfInitPowerCal(dev);
864
865 if(frequency > ZM_CH_G_14)
866 {
867 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5143);
868 }
869 else
870 {
871 zfDelayWriteInternalReg(dev, 0x1d4014, 0x5163);
872 }
873
874 zfFlushDelayWrite(dev);
875 }
876
877
878 void zfInitRf(zdev_t* dev, u32_t frequency)
879 {
880 u32_t cmd[8];
881 u16_t ret;
882 int delta_slope_coeff_exp;
883 int delta_slope_coeff_man;
884 int delta_slope_coeff_exp_shgi;
885 int delta_slope_coeff_man_shgi;
886
887 zmw_get_wlan_dev(dev);
888
889 zm_debug_msg1(" initRf frequency = ", frequency);
890
891 if (frequency == 0)
892 {
893 frequency = 2412;
894 }
895
896 /* Bank 0 1 2 3 5 6 7 */
897 zfSetRfRegs(dev, frequency);
898 /* Bank 4 */
899 zfSetBank4AndPowerTable(dev, frequency, 0, 0);
900
901 /* stroe frequency */
902 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
903
904 zfGetHwTurnOffdynParam(dev,
905 frequency, 0, 0,
906 &delta_slope_coeff_exp,
907 &delta_slope_coeff_man,
908 &delta_slope_coeff_exp_shgi,
909 &delta_slope_coeff_man_shgi);
910
911 /* related functions */
912 frequency = frequency*1000;
913 cmd[0] = 28 | (ZM_CMD_RF_INIT << 8);
914 cmd[1] = frequency;
915 cmd[2] = 0;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
916 cmd[3] = 1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
917 cmd[4] = delta_slope_coeff_exp;
918 cmd[5] = delta_slope_coeff_man;
919 cmd[6] = delta_slope_coeff_exp_shgi;
920 cmd[7] = delta_slope_coeff_man_shgi;
921
922 ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, 0);
923
924 // delay temporarily, wait for new PHY and RF
925 zfwSleep(dev, 1000);
926 }
927
928 int tn(int exp)
929 {
930 int i;
931 int tmp = 1;
932 for(i=0; i<exp; i++)
933 tmp = tmp*2;
934
935 return tmp;
936 }
937
938 /*int zfFloor(double indata)
939 {
940 if(indata<0)
941 return (int)indata-1;
942 else
943 return (int)indata;
944 }
945 */
946 u32_t reverse_bits(u32_t chan_sel)
947 {
948 /* reverse_bits */
949 u32_t chansel = 0;
950 u8_t i;
951
952 for (i=0; i<8; i++)
953 chansel |= ((chan_sel>>(7-i) & 0x1) << i);
954 return chansel;
955 }
956
957 /* Bank 0 1 2 3 5 6 7 */
958 void zfSetRfRegs(zdev_t* dev, u32_t frequency)
959 {
960 u16_t entries;
961 u16_t freqIndex = 0;
962 u16_t i;
963
964 //zmw_get_wlan_dev(dev);
965
966 if ( frequency > ZM_CH_G_14 )
967 {
968 /* 5G */
969 freqIndex = 1;
970 zm_msg0_scan(ZM_LV_2, "Set to 5GHz");
971
972 }
973 else
974 {
975 /* 2.4G */
976 freqIndex = 2;
977 zm_msg0_scan(ZM_LV_2, "Set to 2.4GHz");
978 }
979
980 #if 1
981 entries = sizeof(otusBank) / sizeof(*otusBank);
982 for (i=0; i<entries; i++)
983 {
984 reg_write(otusBank[i][0], otusBank[i][freqIndex]);
985 }
986 #else
987 /* Bank0 */
988 entries = sizeof(ar5416Bank0) / sizeof(*ar5416Bank0);
989 for (i=0; i<entries; i++)
990 {
991 reg_write(ar5416Bank0[i][0], ar5416Bank0[i][1]);
992 }
993 /* Bank1 */
994 entries = sizeof(ar5416Bank1) / sizeof(*ar5416Bank1);
995 for (i=0; i<entries; i++)
996 {
997 reg_write(ar5416Bank1[i][0], ar5416Bank1[i][1]);
998 }
999 /* Bank2 */
1000 entries = sizeof(ar5416Bank2) / sizeof(*ar5416Bank2);
1001 for (i=0; i<entries; i++)
1002 {
1003 reg_write(ar5416Bank2[i][0], ar5416Bank2[i][1]);
1004 }
1005 /* Bank3 */
1006 entries = sizeof(ar5416Bank3) / sizeof(*ar5416Bank3);
1007 for (i=0; i<entries; i++)
1008 {
1009 reg_write(ar5416Bank3[i][0], ar5416Bank3[i][freqIndex]);
1010 }
1011 /* Bank5 */
1012 reg_write (0x98b0, 0x00000013);
1013 reg_write (0x98e4, 0x00000002);
1014 /* Bank6 */
1015 entries = sizeof(ar5416Bank6) / sizeof(*ar5416Bank6);
1016 for (i=0; i<entries; i++)
1017 {
1018 reg_write(ar5416Bank6[i][0], ar5416Bank6[i][freqIndex]);
1019 }
1020 /* Bank7 */
1021 entries = sizeof(ar5416Bank7) / sizeof(*ar5416Bank7);
1022 for (i=0; i<entries; i++)
1023 {
1024 reg_write(ar5416Bank7[i][0], ar5416Bank7[i][1]);
1025 }
1026 #endif
1027
1028 zfFlushDelayWrite(dev);
1029 }
1030
1031 /* Bank 4 */
1032 void zfSetBank4AndPowerTable(zdev_t* dev, u32_t frequency, u8_t bw40,
1033 u8_t extOffset)
1034 {
1035 u32_t chup = 1;
1036 u32_t bmode_LF_synth_freq = 0;
1037 u32_t amode_refsel_1 = 0;
1038 u32_t amode_refsel_0 = 1;
1039 u32_t addr2 = 1;
1040 u32_t addr1 = 0;
1041 u32_t addr0 = 0;
1042
1043 u32_t d1;
1044 u32_t d0;
1045 u32_t tmp_0;
1046 u32_t tmp_1;
1047 u32_t data0;
1048 u32_t data1;
1049
1050 u8_t chansel;
1051 u8_t chan_sel;
1052 u32_t temp_chan_sel;
1053
1054 u16_t i;
1055
1056 zmw_get_wlan_dev(dev);
1057
1058
1059 /* if enable 802.11h, need to record curent channel index in channel array */
1060 if (wd->sta.DFSEnable)
1061 {
1062 for (i = 0; i < wd->regulationTable.allowChannelCnt; i++)
1063 {
1064 if (wd->regulationTable.allowChannel[i].channel == frequency)
1065 break;
1066 }
1067 wd->regulationTable.CurChIndex = i;
1068 }
1069
1070 if (bw40 == 1)
1071 {
1072 if (extOffset == 1)
1073 {
1074 frequency += 10;
1075 }
1076 else
1077 {
1078 frequency -= 10;
1079 }
1080
1081 }
1082
1083
1084 if ( frequency > 3000 )
1085 {
1086 if ( frequency % 10 )
1087 {
1088 /* 5M */
1089 chan_sel = (u8_t)((frequency - 4800)/5);
1090 chan_sel = (u8_t)(chan_sel & 0xff);
1091 chansel = (u8_t)reverse_bits(chan_sel);
1092 }
1093 else
1094 {
1095 /* 10M : improve Tx EVM */
1096 chan_sel = (u8_t)((frequency - 4800)/10);
1097 chan_sel = (u8_t)(chan_sel & 0xff)<<1;
1098 chansel = (u8_t)reverse_bits(chan_sel);
1099
1100 amode_refsel_1 = 1;
1101 amode_refsel_0 = 0;
1102 }
1103 }
1104 else
1105 {
1106 //temp_chan_sel = (((frequency - 672)*2) - 3040)/10;
1107 if (frequency == 2484)
1108 {
1109 temp_chan_sel = 10 + (frequency - 2274)/5 ;
1110 bmode_LF_synth_freq = 1;
1111 }
1112 else
1113 {
1114 temp_chan_sel = 16 + (frequency - 2272)/5 ;
1115 bmode_LF_synth_freq = 0;
1116 }
1117 chan_sel = (u8_t)(temp_chan_sel << 2) & 0xff;
1118 chansel = (u8_t)reverse_bits(chan_sel);
1119 }
1120
1121 d1 = chansel; //# 8 bits of chan
1122 d0 = addr0<<7 | addr1<<6 | addr2<<5
1123 | amode_refsel_0<<3 | amode_refsel_1<<2
1124 | bmode_LF_synth_freq<<1 | chup;
1125
1126 tmp_0 = d0 & 0x1f; //# 5-1
1127 tmp_1 = d1 & 0x1f; //# 5-1
1128 data0 = tmp_1<<5 | tmp_0;
1129
1130 tmp_0 = d0>>5 & 0x7; //# 8-6
1131 tmp_1 = d1>>5 & 0x7; //# 8-6
1132 data1 = tmp_1<<5 | tmp_0;
1133
1134 /* Bank4 */
1135 reg_write (0x9800+(0x2c<<2), data0);
1136 reg_write (0x9800+(0x3a<<2), data1);
1137 //zm_debug_msg1("0x9800+(0x2c<<2 = ", data0);
1138 //zm_debug_msg1("0x9800+(0x3a<<2 = ", data1);
1139
1140
1141 zfFlushDelayWrite(dev);
1142
1143 zfwSleep(dev, 10);
1144
1145 return;
1146 }
1147
1148
1149 struct zsPhyFreqPara
1150 {
1151 u32_t coeff_exp;
1152 u32_t coeff_man;
1153 u32_t coeff_exp_shgi;
1154 u32_t coeff_man_shgi;
1155 };
1156
1157 struct zsPhyFreqTable
1158 {
1159 u32_t frequency;
1160 struct zsPhyFreqPara FpgaDynamicHT;
1161 struct zsPhyFreqPara FpgaStaticHT;
1162 struct zsPhyFreqPara ChipST20Mhz;
1163 struct zsPhyFreqPara Chip2040Mhz;
1164 struct zsPhyFreqPara Chip2040ExtAbove;
1165 };
1166
1167 const struct zsPhyFreqTable zgPhyFreqCoeff[] =
1168 {
1169 /*Index freq FPGA DYNAMIC_HT2040_EN FPGA STATIC_HT20 Real Chip static20MHz Real Chip 2040MHz Real Chip 2040Mhz */
1170 /* fclk = 10.8 21.6 40 ext below 40 ext above 40 */
1171 /* 0 */ {2412, {5, 23476, 5, 21128}, {4, 23476, 4, 21128}, {3, 21737, 3, 19563}, {3, 21827, 3, 19644}, {3, 21647, 3, 19482}},
1172 /* 1 */ {2417, {5, 23427, 5, 21084}, {4, 23427, 4, 21084}, {3, 21692, 3, 19523}, {3, 21782, 3, 19604}, {3, 21602, 3, 19442}},
1173 /* 2 */ {2422, {5, 23379, 5, 21041}, {4, 23379, 4, 21041}, {3, 21647, 3, 19482}, {3, 21737, 3, 19563}, {3, 21558, 3, 19402}},
1174 /* 3 */ {2427, {5, 23330, 5, 20997}, {4, 23330, 4, 20997}, {3, 21602, 3, 19442}, {3, 21692, 3, 19523}, {3, 21514, 3, 19362}},
1175 /* 4 */ {2432, {5, 23283, 5, 20954}, {4, 23283, 4, 20954}, {3, 21558, 3, 19402}, {3, 21647, 3, 19482}, {3, 21470, 3, 19323}},
1176 /* 5 */ {2437, {5, 23235, 5, 20911}, {4, 23235, 4, 20911}, {3, 21514, 3, 19362}, {3, 21602, 3, 19442}, {3, 21426, 3, 19283}},
1177 /* 6 */ {2442, {5, 23187, 5, 20868}, {4, 23187, 4, 20868}, {3, 21470, 3, 19323}, {3, 21558, 3, 19402}, {3, 21382, 3, 19244}},
1178 /* 7 */ {2447, {5, 23140, 5, 20826}, {4, 23140, 4, 20826}, {3, 21426, 3, 19283}, {3, 21514, 3, 19362}, {3, 21339, 3, 19205}},
1179 /* 8 */ {2452, {5, 23093, 5, 20783}, {4, 23093, 4, 20783}, {3, 21382, 3, 19244}, {3, 21470, 3, 19323}, {3, 21295, 3, 19166}},
1180 /* 9 */ {2457, {5, 23046, 5, 20741}, {4, 23046, 4, 20741}, {3, 21339, 3, 19205}, {3, 21426, 3, 19283}, {3, 21252, 3, 19127}},
1181 /* 10 */ {2462, {5, 22999, 5, 20699}, {4, 22999, 4, 20699}, {3, 21295, 3, 19166}, {3, 21382, 3, 19244}, {3, 21209, 3, 19088}},
1182 /* 11 */ {2467, {5, 22952, 5, 20657}, {4, 22952, 4, 20657}, {3, 21252, 3, 19127}, {3, 21339, 3, 19205}, {3, 21166, 3, 19050}},
1183 /* 12 */ {2472, {5, 22906, 5, 20615}, {4, 22906, 4, 20615}, {3, 21209, 3, 19088}, {3, 21295, 3, 19166}, {3, 21124, 3, 19011}},
1184 /* 13 */ {2484, {5, 22795, 5, 20516}, {4, 22795, 4, 20516}, {3, 21107, 3, 18996}, {3, 21192, 3, 19073}, {3, 21022, 3, 18920}},
1185 /* 14 */ {4920, {6, 23018, 6, 20716}, {5, 23018, 5, 20716}, {4, 21313, 4, 19181}, {4, 21356, 4, 19220}, {4, 21269, 4, 19142}},
1186 /* 15 */ {4940, {6, 22924, 6, 20632}, {5, 22924, 5, 20632}, {4, 21226, 4, 19104}, {4, 21269, 4, 19142}, {4, 21183, 4, 19065}},
1187 /* 16 */ {4960, {6, 22832, 6, 20549}, {5, 22832, 5, 20549}, {4, 21141, 4, 19027}, {4, 21183, 4, 19065}, {4, 21098, 4, 18988}},
1188 /* 17 */ {4980, {6, 22740, 6, 20466}, {5, 22740, 5, 20466}, {4, 21056, 4, 18950}, {4, 21098, 4, 18988}, {4, 21014, 4, 18912}},
1189 /* 18 */ {5040, {6, 22469, 6, 20223}, {5, 22469, 5, 20223}, {4, 20805, 4, 18725}, {4, 20846, 4, 18762}, {4, 20764, 4, 18687}},
1190 /* 19 */ {5060, {6, 22381, 6, 20143}, {5, 22381, 5, 20143}, {4, 20723, 4, 18651}, {4, 20764, 4, 18687}, {4, 20682, 4, 18614}},
1191 /* 20 */ {5080, {6, 22293, 6, 20063}, {5, 22293, 5, 20063}, {4, 20641, 4, 18577}, {4, 20682, 4, 18614}, {4, 20601, 4, 18541}},
1192 /* 21 */ {5180, {6, 21862, 6, 19676}, {5, 21862, 5, 19676}, {4, 20243, 4, 18219}, {4, 20282, 4, 18254}, {4, 20204, 4, 18183}},
1193 /* 22 */ {5200, {6, 21778, 6, 19600}, {5, 21778, 5, 19600}, {4, 20165, 4, 18148}, {4, 20204, 4, 18183}, {4, 20126, 4, 18114}},
1194 /* 23 */ {5220, {6, 21695, 6, 19525}, {5, 21695, 5, 19525}, {4, 20088, 4, 18079}, {4, 20126, 4, 18114}, {4, 20049, 4, 18044}},
1195 /* 24 */ {5240, {6, 21612, 6, 19451}, {5, 21612, 5, 19451}, {4, 20011, 4, 18010}, {4, 20049, 4, 18044}, {4, 19973, 4, 17976}},
1196 /* 25 */ {5260, {6, 21530, 6, 19377}, {5, 21530, 5, 19377}, {4, 19935, 4, 17941}, {4, 19973, 4, 17976}, {4, 19897, 4, 17907}},
1197 /* 26 */ {5280, {6, 21448, 6, 19303}, {5, 21448, 5, 19303}, {4, 19859, 4, 17873}, {4, 19897, 4, 17907}, {4, 19822, 4, 17840}},
1198 /* 27 */ {5300, {6, 21367, 6, 19230}, {5, 21367, 5, 19230}, {4, 19784, 4, 17806}, {4, 19822, 4, 17840}, {4, 19747, 4, 17772}},
1199 /* 28 */ {5320, {6, 21287, 6, 19158}, {5, 21287, 5, 19158}, {4, 19710, 4, 17739}, {4, 19747, 4, 17772}, {4, 19673, 4, 17706}},
1200 /* 29 */ {5500, {6, 20590, 6, 18531}, {5, 20590, 5, 18531}, {4, 19065, 4, 17159}, {4, 19100, 4, 17190}, {4, 19030, 4, 17127}},
1201 /* 30 */ {5520, {6, 20516, 6, 18464}, {5, 20516, 5, 18464}, {4, 18996, 4, 17096}, {4, 19030, 4, 17127}, {4, 18962, 4, 17065}},
1202 /* 31 */ {5540, {6, 20442, 6, 18397}, {5, 20442, 5, 18397}, {4, 18927, 4, 17035}, {4, 18962, 4, 17065}, {4, 18893, 4, 17004}},
1203 /* 32 */ {5560, {6, 20368, 6, 18331}, {5, 20368, 5, 18331}, {4, 18859, 4, 16973}, {4, 18893, 4, 17004}, {4, 18825, 4, 16943}},
1204 /* 33 */ {5580, {6, 20295, 6, 18266}, {5, 20295, 5, 18266}, {4, 18792, 4, 16913}, {4, 18825, 4, 16943}, {4, 18758, 4, 16882}},
1205 /* 34 */ {5600, {6, 20223, 6, 18200}, {5, 20223, 5, 18200}, {4, 18725, 4, 16852}, {4, 18758, 4, 16882}, {4, 18691, 4, 16822}},
1206 /* 35 */ {5620, {6, 20151, 6, 18136}, {5, 20151, 5, 18136}, {4, 18658, 4, 16792}, {4, 18691, 4, 16822}, {4, 18625, 4, 16762}},
1207 /* 36 */ {5640, {6, 20079, 6, 18071}, {5, 20079, 5, 18071}, {4, 18592, 4, 16733}, {4, 18625, 4, 16762}, {4, 18559, 4, 16703}},
1208 /* 37 */ {5660, {6, 20008, 6, 18007}, {5, 20008, 5, 18007}, {4, 18526, 4, 16673}, {4, 18559, 4, 16703}, {4, 18493, 4, 16644}},
1209 /* 38 */ {5680, {6, 19938, 6, 17944}, {5, 19938, 5, 17944}, {4, 18461, 4, 16615}, {4, 18493, 4, 16644}, {4, 18428, 4, 16586}},
1210 /* 39 */ {5700, {6, 19868, 6, 17881}, {5, 19868, 5, 17881}, {4, 18396, 4, 16556}, {4, 18428, 4, 16586}, {4, 18364, 4, 16527}},
1211 /* 40 */ {5745, {6, 19712, 6, 17741}, {5, 19712, 5, 17741}, {4, 18252, 4, 16427}, {4, 18284, 4, 16455}, {4, 18220, 4, 16398}},
1212 /* 41 */ {5765, {6, 19644, 6, 17679}, {5, 19644, 5, 17679}, {4, 18189, 5, 32740}, {4, 18220, 4, 16398}, {4, 18157, 5, 32683}},
1213 /* 42 */ {5785, {6, 19576, 6, 17618}, {5, 19576, 5, 17618}, {4, 18126, 5, 32626}, {4, 18157, 5, 32683}, {4, 18094, 5, 32570}},
1214 /* 43 */ {5805, {6, 19508, 6, 17558}, {5, 19508, 5, 17558}, {4, 18063, 5, 32514}, {4, 18094, 5, 32570}, {4, 18032, 5, 32458}},
1215 /* 44 */ {5825, {6, 19441, 6, 17497}, {5, 19441, 5, 17497}, {4, 18001, 5, 32402}, {4, 18032, 5, 32458}, {4, 17970, 5, 32347}},
1216 /* 45 */ {5170, {6, 21904, 6, 19714}, {5, 21904, 5, 19714}, {4, 20282, 4, 18254}, {4, 20321, 4, 18289}, {4, 20243, 4, 18219}},
1217 /* 46 */ {5190, {6, 21820, 6, 19638}, {5, 21820, 5, 19638}, {4, 20204, 4, 18183}, {4, 20243, 4, 18219}, {4, 20165, 4, 18148}},
1218 /* 47 */ {5210, {6, 21736, 6, 19563}, {5, 21736, 5, 19563}, {4, 20126, 4, 18114}, {4, 20165, 4, 18148}, {4, 20088, 4, 18079}},
1219 /* 48 */ {5230, {6, 21653, 6, 19488}, {5, 21653, 5, 19488}, {4, 20049, 4, 18044}, {4, 20088, 4, 18079}, {4, 20011, 4, 18010}}
1220 };
1221 /* to reduce search time, please modify this define if you add or delete channel in table */
1222 #define First5GChannelIndex 14
1223
1224 void zfGetHwTurnOffdynParam(zdev_t* dev,
1225 u32_t frequency, u8_t bw40, u8_t extOffset,
1226 int* delta_slope_coeff_exp,
1227 int* delta_slope_coeff_man,
1228 int* delta_slope_coeff_exp_shgi,
1229 int* delta_slope_coeff_man_shgi)
1230 {
1231 /* Get param for turnoffdyn */
1232 u16_t i, arraySize;
1233
1234 //zmw_get_wlan_dev(dev);
1235
1236 arraySize = sizeof(zgPhyFreqCoeff)/sizeof(struct zsPhyFreqTable);
1237 if (frequency < 3000)
1238 {
1239 /* 2.4GHz Channel */
1240 for (i = 0; i < First5GChannelIndex; i++)
1241 {
1242 if (frequency == zgPhyFreqCoeff[i].frequency)
1243 break;
1244 }
1245
1246 if (i < First5GChannelIndex)
1247 {
1248 }
1249 else
1250 {
1251 zm_msg1_scan(ZM_LV_0, "Unsupported 2.4G frequency = ", frequency);
1252 return;
1253 }
1254 }
1255 else
1256 {
1257 /* 5GHz Channel */
1258 for (i = First5GChannelIndex; i < arraySize; i++)
1259 {
1260 if (frequency == zgPhyFreqCoeff[i].frequency)
1261 break;
1262 }
1263
1264 if (i < arraySize)
1265 {
1266 }
1267 else
1268 {
1269 zm_msg1_scan(ZM_LV_0, "Unsupported 5G frequency = ", frequency);
1270 return;
1271 }
1272 }
1273
1274 /* FPGA DYNAMIC_HT2040_EN fclk = 10.8 */
1275 /* FPGA STATIC_HT20_ fclk = 21.6 */
1276 /* Real Chip fclk = 40 */
1277 #if ZM_FPGA_PHY == 1
1278 //fclk = 10.8;
1279 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp;
1280 *delta_slope_coeff_man = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man;
1281 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_exp_shgi;
1282 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].FpgaDynamicHT.coeff_man_shgi;
1283 #else
1284 //fclk = 40;
1285 if (bw40)
1286 {
1287 /* ht2040 */
1288 if (extOffset == 1) {
1289 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp;
1290 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man;
1291 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_exp_shgi;
1292 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040ExtAbove.coeff_man_shgi;
1293 }
1294 else {
1295 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp;
1296 *delta_slope_coeff_man = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man;
1297 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_exp_shgi;
1298 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].Chip2040Mhz.coeff_man_shgi;
1299 }
1300 }
1301 else
1302 {
1303 /* static 20 */
1304 *delta_slope_coeff_exp = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp;
1305 *delta_slope_coeff_man = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man;
1306 *delta_slope_coeff_exp_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_exp_shgi;
1307 *delta_slope_coeff_man_shgi = zgPhyFreqCoeff[i].ChipST20Mhz.coeff_man_shgi;
1308 }
1309 #endif
1310 }
1311
1312 /* Main routin frequency setting function */
1313 /* If 2.4G/5G switch, PHY need resetting BB and RF for band switch */
1314 /* Do the setting switch in zfSendFrequencyCmd() */
1315 void zfHpSetFrequencyEx(zdev_t* dev, u32_t frequency, u8_t bw40,
1316 u8_t extOffset, u8_t initRF)
1317 {
1318 u32_t cmd[9];
1319 u32_t cmdB[3];
1320 u16_t ret;
1321 u8_t old_band;
1322 u8_t new_band;
1323 u32_t checkLoopCount;
1324 u32_t tmpValue;
1325
1326 int delta_slope_coeff_exp;
1327 int delta_slope_coeff_man;
1328 int delta_slope_coeff_exp_shgi;
1329 int delta_slope_coeff_man_shgi;
1330 struct zsHpPriv* hpPriv;
1331
1332 zmw_get_wlan_dev(dev);
1333 hpPriv = wd->hpPrivate;
1334
1335 zm_msg1_scan(ZM_LV_1, "Frequency = ", frequency);
1336 zm_msg1_scan(ZM_LV_1, "bw40 = ", bw40);
1337 zm_msg1_scan(ZM_LV_1, "extOffset = ", extOffset);
1338
1339 if ( hpPriv->coldResetNeedFreq )
1340 {
1341 hpPriv->coldResetNeedFreq = 0;
1342 initRF = 2;
1343 zm_debug_msg0("zfHpSetFrequencyEx: Do ColdReset ");
1344 }
1345 if ( hpPriv->isSiteSurvey == 2 )
1346 {
1347 /* wait time for AGC and noise calibration : not in sitesurvey and connected */
1348 checkLoopCount = 2000; /* 2000*100 = 200ms */
1349 }
1350 else
1351 {
1352 /* wait time for AGC and noise calibration : in sitesurvey */
1353 checkLoopCount = 1000; /* 1000*100 = 100ms */
1354 }
1355
1356 hpPriv->latestFrequency = frequency;
1357 hpPriv->latestBw40 = bw40;
1358 hpPriv->latestExtOffset = extOffset;
1359
1360 if ((hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_GENERAL) ||
1361 (hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK))
1362 {
1363 if ( frequency <= ZM_CH_G_14 )
1364 {
1365 /* workaround for 11g Ad Hoc beacon distribution */
1366 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 0x7f0007);
1367 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, 0x1c04901c);
1368 }
1369 }
1370
1371 /* AHB, DAC, ADC clock selection by static20/ht2040 */
1372 zfSelAdcClk(dev, bw40, frequency);
1373
1374 /* clear bb_heavy_clip_enable */
1375 reg_write(0x99e0, 0x200);
1376 zfFlushDelayWrite(dev);
1377
1378 /* Set CTS/RTS rate */
1379 if ( frequency > ZM_CH_G_14 )
1380 {
1381 //zfHpSetRTSCTSRate(dev, 0x10b010b); /* OFDM 6M */
1382 new_band = 1;
1383 }
1384 else
1385 {
1386 //zfHpSetRTSCTSRate(dev, 0x30003); /* CCK 11M */
1387 new_band = 0;
1388 }
1389
1390 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency > ZM_CH_G_14)
1391 old_band = 1;
1392 else
1393 old_band = 0;
1394
1395 //Workaround for 2.4GHz only device
1396 if ((hpPriv->OpFlags & 0x1) == 0)
1397 {
1398 if ((((struct zsHpPriv*)wd->hpPrivate)->hwFrequency == ZM_CH_G_1) && (frequency == ZM_CH_G_2))
1399 {
1400 /* Force to do band switching */
1401 old_band = 1;
1402 }
1403 }
1404
1405 /* Notify channel switch to firmware */
1406 /* TX/RX must be stopped by now */
1407 cmd[0] = 0 | (ZM_CMD_FREQ_STRAT << 8);
1408 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, 0);
1409
1410 if ((initRF != 0) || (new_band != old_band)
1411 || (((struct zsHpPriv*)wd->hpPrivate)->hwBw40 != bw40))
1412 {
1413 /* band switch */
1414 zm_msg0_scan(ZM_LV_1, "=====band switch=====");
1415
1416 if (initRF == 2 )
1417 {
1418 //Cold reset BB/ADDA
1419 zfDelayWriteInternalReg(dev, 0x1d4004, 0x800);
1420 zfFlushDelayWrite(dev);
1421 zm_msg0_scan(ZM_LV_1, "Do cold reset BB/ADDA");
1422 }
1423 else
1424 {
1425 //Warm reset BB/ADDA
1426 zfDelayWriteInternalReg(dev, 0x1d4004, 0x400);
1427 zfFlushDelayWrite(dev);
1428 }
1429
1430 /* reset workaround state to default */
1431 hpPriv->rxStrongRSSI = 0;
1432 hpPriv->strongRSSI = 0;
1433
1434 zfDelayWriteInternalReg(dev, 0x1d4004, 0x0);
1435 zfFlushDelayWrite(dev);
1436
1437 zfInitPhy(dev, frequency, bw40);
1438
1439 // zfiCheckRifs(dev);
1440
1441 /* Bank 0 1 2 3 5 6 7 */
1442 zfSetRfRegs(dev, frequency);
1443 /* Bank 4 */
1444 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1445
1446 cmd[0] = 32 | (ZM_CMD_RF_INIT << 8);
1447 }
1448 else //((new_band == old_band) && !initRF)
1449 {
1450 /* same band */
1451
1452 /* Force disable CR671 bit20 / 7823 */
1453 /* The bug has to do with the polarity of the pdadc offset calibration. There */
1454 /* is an initial calibration that is OK, and there is a continuous */
1455 /* calibration that updates the pddac with the wrong polarity. Fortunately */
1456 /* the second loop can be disabled with a bit called en_pd_dc_offset_thr. */
1457 #if 0
1458 cmdB[0] = 8 | (ZM_CMD_BITAND << 8);;
1459 cmdB[1] = (0xa27c + 0x1bc000);
1460 cmdB[2] = 0xffefffff;
1461 ret = zfIssueCmd(dev, cmdB, 12, ZM_OID_INTERNAL_WRITE, 0);
1462 #endif
1463
1464 /* Bank 4 */
1465 zfSetBank4AndPowerTable(dev, frequency, bw40, extOffset);
1466
1467
1468 cmd[0] = 32 | (ZM_CMD_FREQUENCY << 8);
1469 }
1470
1471 /* Compatibility for new layout UB83 */
1472 /* Setting code at CR1 here move from the func:zfHwHTEnable() in firmware */
1473 if (((struct zsHpPriv*)wd->hpPrivate)->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
1474 {
1475 /* UB83 : one stream */
1476 tmpValue = 0;
1477 }
1478 else
1479 {
1480 /* UB81, UB82 : two stream */
1481 tmpValue = 0x100;
1482 }
1483
1484 if (1) //if (((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE == 1)
1485 {
1486 if (bw40 == 1)
1487 {
1488 if (extOffset == 1) {
1489 reg_write(0x9804, tmpValue | 0x2d4); //3d4 for real
1490 }
1491 else {
1492 reg_write(0x9804, tmpValue | 0x2c4); //3c4 for real
1493 }
1494 //# Dyn HT2040.Refer to Reg 1.
1495 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1496 //#[c]:allow short GI for HT40 packets; enable HT detection.
1497 //#[4]:enable 20/40 MHz channel detection.
1498 }
1499 else
1500 {
1501 reg_write(0x9804, tmpValue | 0x240);
1502 //# Static HT20
1503 //#[3]:single length (4us) 1st HT long training symbol; use Walsh spatial spreading for 2 chains 2 streams TX
1504 //#[4]:Otus don't allow short GI for HT20 packets yet; enable HT detection.
1505 //#[0]:disable 20/40 MHz channel detection.
1506 }
1507 }
1508 else
1509 {
1510 reg_write(0x9804, 0x0);
1511 //# Legacy;# Direct Mapping for each chain.
1512 //#Be modified by Oligo to add dynanic for legacy.
1513 if (bw40 == 1)
1514 {
1515 reg_write(0x9804, 0x4); //# Dyn Legacy .Refer to reg 1.
1516 }
1517 else
1518 {
1519 reg_write(0x9804, 0x0); //# Static Legacy
1520 }
1521 }
1522 zfFlushDelayWrite(dev);
1523 /* end of ub83 compatibility */
1524
1525 /* Set Power, TPC, Gain table... */
1526 zfSetPowerCalTable(dev, frequency, bw40, extOffset);
1527
1528
1529 /* store frequency */
1530 ((struct zsHpPriv*)wd->hpPrivate)->hwFrequency = (u16_t)frequency;
1531 ((struct zsHpPriv*)wd->hpPrivate)->hwBw40 = bw40;
1532 ((struct zsHpPriv*)wd->hpPrivate)->hwExtOffset = extOffset;
1533
1534 zfGetHwTurnOffdynParam(dev,
1535 frequency, bw40, extOffset,
1536 &delta_slope_coeff_exp,
1537 &delta_slope_coeff_man,
1538 &delta_slope_coeff_exp_shgi,
1539 &delta_slope_coeff_man_shgi);
1540
1541 /* related functions */
1542 frequency = frequency*1000;
1543 /* len[36] : type[0x30] : seq[?] */
1544 // cmd[0] = 28 | (ZM_CMD_FREQUENCY << 8);
1545 cmd[1] = frequency;
1546 cmd[2] = bw40;//((struct zsHpPriv*)wd->hpPrivate)->hw_DYNAMIC_HT2040_EN;
1547 cmd[3] = (extOffset<<2)|0x1;//((wd->ExtOffset << 2) | ((struct zsHpPriv*)wd->hpPrivate)->hw_HT_ENABLE);
1548 cmd[4] = delta_slope_coeff_exp;
1549 cmd[5] = delta_slope_coeff_man;
1550 cmd[6] = delta_slope_coeff_exp_shgi;
1551 cmd[7] = delta_slope_coeff_man_shgi;
1552 cmd[8] = checkLoopCount;
1553
1554 ret = zfIssueCmd(dev, cmd, 36, ZM_CMD_SET_FREQUENCY, 0);
1555
1556 // delay temporarily, wait for new PHY and RF
1557 //zfwSleep(dev, 1000);
1558 }
1559
1560
1561 /******************** Key ********************/
1562
1563 u16_t zfHpResetKeyCache(zdev_t* dev)
1564 {
1565 u8_t i;
1566 u32_t key[4] = {0, 0, 0, 0};
1567 struct zsHpPriv* hpPriv;
1568
1569 zmw_get_wlan_dev(dev);
1570 hpPriv=wd->hpPrivate;
1571
1572 for(i=0;i<4;i++)
1573 {
1574 zfHpSetDefaultKey(dev, i, ZM_WEP64, key, NULL);
1575 }
1576 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, 0x00);
1577 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, 0x00);
1578 zfFlushDelayWrite(dev);
1579
1580 hpPriv->camRollCallTable = (u64_t) 0;
1581
1582 return 0;
1583 }
1584
1585
1586 /************************************************************************/
1587 /* */
1588 /* FUNCTION DESCRIPTION zfSetKey */
1589 /* Set key. */
1590 /* */
1591 /* INPUTS */
1592 /* dev : device pointer */
1593 /* */
1594 /* OUTPUTS */
1595 /* 0 : success */
1596 /* other : fail */
1597 /* */
1598 /* AUTHOR */
1599 /* Stephen Chen ZyDAS Technology Corporation 2006.1 */
1600 /* */
1601 /************************************************************************/
1602 /* ! please use zfCoreSetKey() in 80211Core for SetKey */
1603 u32_t zfHpSetKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t type,
1604 u16_t* mac, u32_t* key)
1605 {
1606 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1607 u16_t ret;
1608 u16_t i;
1609 struct zsHpPriv* hpPriv;
1610
1611 zmw_get_wlan_dev(dev);
1612 hpPriv=wd->hpPrivate;
1613
1614 #if 0 /* remove to zfCoreSetKey() */
1615 zmw_declare_for_critical_section();
1616
1617 zmw_enter_critical_section(dev);
1618 wd->sta.flagKeyChanging++;
1619 zm_debug_msg1(" zfHpSetKey++++ ", wd->sta.flagKeyChanging);
1620 zmw_leave_critical_section(dev);
1621 #endif
1622
1623 cmd[0] = 0x0000281C;
1624 cmd[1] = ((u32_t)keyId<<16) + (u32_t)user;
1625 cmd[2] = ((u32_t)mac[0]<<16) + (u32_t)type;
1626 cmd[3] = ((u32_t)mac[2]<<16) + ((u32_t)mac[1]);
1627
1628 for (i=0; i<4; i++)
1629 {
1630 cmd[4+i] = key[i];
1631 }
1632
1633 if (user < 64)
1634 {
1635 hpPriv->camRollCallTable |= ((u64_t) 1) << user;
1636 }
1637
1638 //ret = zfIssueCmd(dev, cmd, 32, ZM_OID_INTERNAL_WRITE, NULL);
1639 ret = zfIssueCmd(dev, cmd, 32, ZM_CMD_SET_KEY, NULL);
1640 return ret;
1641 }
1642
1643
1644 u32_t zfHpSetApPairwiseKey(zdev_t* dev, u16_t* staMacAddr, u8_t type,
1645 u32_t* key, u32_t* micKey, u16_t staAid)
1646 {
1647 if ((staAid!=0) && (staAid<64))
1648 {
1649 zfHpSetKey(dev, (staAid-1), 0, type, staMacAddr, key);
1650 if ((type == ZM_TKIP)
1651 #ifdef ZM_ENABLE_CENC
1652 || (type == ZM_CENC)
1653 #endif //ZM_ENABLE_CENC
1654 )
1655 zfHpSetKey(dev, (staAid-1), 1, type, staMacAddr, micKey);
1656 return 0;
1657 }
1658 return 1;
1659 }
1660
1661 u32_t zfHpSetApGroupKey(zdev_t* dev, u16_t* apMacAddr, u8_t type,
1662 u32_t* key, u32_t* micKey, u16_t vapId)
1663 {
1664 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 0, type, apMacAddr, key); // 6D18 modify from 0 to 1 ??
1665 if ((type == ZM_TKIP)
1666 #ifdef ZM_ENABLE_CENC
1667 || (type == ZM_CENC)
1668 #endif //ZM_ENABLE_CENC
1669 )
1670 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT - 1 - vapId, 1, type, apMacAddr, micKey);
1671 return 0;
1672 }
1673
1674 u32_t zfHpSetDefaultKey(zdev_t* dev, u8_t keyId, u8_t type, u32_t* key, u32_t* micKey)
1675 {
1676 u16_t macAddr[3] = {0, 0, 0};
1677
1678 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1679 struct zsHpPriv* hpPriv;
1680
1681 zmw_get_wlan_dev(dev);
1682 hpPriv = wd->hpPrivate;
1683
1684 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1685 { /* If not wpa2psk , use traditional */
1686 /* Because the bug of chip , defaultkey should follow the key map rule in register 700 */
1687 if ( keyId == 0 )
1688 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1689 else
1690 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, key);
1691 }
1692 else
1693 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1694 #else
1695 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 0, type, macAddr, key);
1696 #endif
1697 if ((type == ZM_TKIP)
1698
1699 #ifdef ZM_ENABLE_CENC
1700 || (type == ZM_CENC)
1701 #endif //ZM_ENABLE_CENC
1702 )
1703 {
1704 zfHpSetKey(dev, ZM_USER_KEY_DEFAULT+keyId, 1, type, macAddr, micKey);
1705 }
1706
1707 return 0;
1708 }
1709
1710 u32_t zfHpSetPerUserKey(zdev_t* dev, u8_t user, u8_t keyId, u8_t* mac, u8_t type, u32_t* key, u32_t* micKey)
1711 {
1712 #ifdef ZM_ENABLE_IBSS_WPA2PSK
1713 struct zsHpPriv* hpPriv;
1714
1715 zmw_get_wlan_dev(dev);
1716 hpPriv = wd->hpPrivate;
1717
1718 if ( hpPriv->dot11Mode == ZM_HAL_80211_MODE_IBSS_WPA2PSK )
1719 { /* If not wpa2psk , use traditional */
1720 if(keyId)
1721 { /* Set Group Key */
1722 zfHpSetKey(dev, user, 1, type, (u16_t *)mac, key);
1723 }
1724 else if(keyId == 0)
1725 { /* Set Pairwise Key */
1726 zfHpSetKey(dev, user, 0, type, (u16_t *)mac, key);
1727 }
1728 }
1729 else
1730 {
1731 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1732 }
1733 #else
1734 zfHpSetKey(dev, user, keyId, type, (u16_t *)mac, key);
1735 #endif
1736
1737 if ((type == ZM_TKIP)
1738 #ifdef ZM_ENABLE_CENC
1739 || (type == ZM_CENC)
1740 #endif //ZM_ENABLE_CENC
1741 )
1742 {
1743 zfHpSetKey(dev, user, keyId + 1, type, (u16_t *)mac, micKey);
1744 }
1745 return 0;
1746 }
1747
1748 /************************************************************************/
1749 /* */
1750 /* FUNCTION DESCRIPTION zfHpRemoveKey */
1751 /* Remove key. */
1752 /* */
1753 /* INPUTS */
1754 /* dev : device pointer */
1755 /* */
1756 /* OUTPUTS */
1757 /* 0 : success */
1758 /* other : fail */
1759 /* */
1760 /* AUTHOR */
1761 /* Yuan-Gu Wei ZyDAS Technology Corporation 2006.6 */
1762 /* */
1763 /************************************************************************/
1764 u16_t zfHpRemoveKey(zdev_t* dev, u16_t user)
1765 {
1766 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1767 u16_t ret = 0;
1768
1769 cmd[0] = 0x00002904;
1770 cmd[1] = (u32_t)user;
1771
1772 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
1773 return ret;
1774 }
1775
1776
1777
1778 /******************** DMA ********************/
1779 u16_t zfHpStartRecv(zdev_t* dev)
1780 {
1781 zfDelayWriteInternalReg(dev, 0x1c3d30, 0x100);
1782 zfFlushDelayWrite(dev);
1783
1784 return 0;
1785 }
1786
1787 u16_t zfHpStopRecv(zdev_t* dev)
1788 {
1789 return 0;
1790 }
1791
1792
1793 /******************** MAC ********************/
1794 void zfInitMac(zdev_t* dev)
1795 {
1796 /* ACK extension register */
1797 // jhlee temp : change value 0x2c -> 0x40
1798 // honda resolve short preamble problem : 0x40 -> 0x75
1799 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_EXTENSION, 0x40); // 0x28 -> 0x2c 6522:yflee
1800
1801 /* TxQ0/1/2/3 Retry MAX=2 => transmit 3 times and degrade rate for retry */
1802 /* PB42 AP crash issue: */
1803 /* Workaround the crash issue by CTS/RTS, set retry max to zero for */
1804 /* workaround tx underrun which enable CTS/RTS */
1805 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RETRY_MAX, 0); // 0x11111 => 0
1806
1807 /* use hardware MIC check */
1808 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1809
1810 /* Set Rx threshold to 1600 */
1811 #if ZM_LARGEPAYLOAD_TEST == 1
1812 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc4000);
1813 #else
1814 #ifndef ZM_DISABLE_AMSDU8K_SUPPORT
1815 /* The maximum A-MSDU length is 3839/7935 */
1816 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc1f80);
1817 #else
1818 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_THRESHOLD, 0xc0f80);
1819 #endif
1820 #endif
1821
1822 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
1823 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RX_PE_DELAY, 0x70);
1824 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
1825 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
1826
1827 /* CF-END mode */
1828 zfDelayWriteInternalReg(dev, 0x1c3b2c, 0x19000000);
1829
1830 //NAV protects ACK only (in TXOP)
1831 zfDelayWriteInternalReg(dev, 0x1c3b38, 0x201);
1832
1833
1834 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
1835 /* OTUS set AM to 0x1 */
1836 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_HT1, 0x8000170);
1837
1838 /* TODO : wep backoff protection 0x63c */
1839 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BACKOFF_PROTECT, 0x105);
1840
1841 /* AGG test code*/
1842 /* Aggregation MAX number and timeout */
1843 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x10000a);
1844 /* Filter any control frames, BAR is bit 24 */
1845 zfDelayWriteInternalReg(dev, 0x1c368c, 0x0500ffff);
1846 /* Enable deaggregator */
1847 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1848
1849 /* Basic rate */
1850 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, 0x150f);
1851 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MANDATORY_RATE, 0x150f);
1852 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, 0x10b01bb);
1853
1854 /* MIMO resposne control */
1855 zfDelayWriteInternalReg(dev, 0x1c3694, 0x4003C1E);/* bit 26~28 otus-AM */
1856
1857 /* Enable LED0 and LED1 */
1858 zfDelayWriteInternalReg(dev, 0x1d0100, 0x3);
1859 zfDelayWriteInternalReg(dev, 0x1d0104, 0x3);
1860
1861 /* switch MAC to OTUS interface */
1862 zfDelayWriteInternalReg(dev, 0x1c3600, 0x3);
1863
1864 /* RXMAC A-MPDU length threshold */
1865 zfDelayWriteInternalReg(dev, 0x1c3c50, 0xffff);
1866
1867 /* Phy register read timeout */
1868 zfDelayWriteInternalReg(dev, 0x1c3680, 0xf00008);
1869
1870 /* Disable Rx TimeOut : workaround for BB.
1871 * OTUS would interrupt the rx frame that sent by OWL TxUnderRun
1872 * because OTUS rx timeout behavior, then OTUS would not ack the BA for
1873 * this AMPDU from OWL.
1874 * Fix by Perry Hwang. 2007/05/10.
1875 * 0x1c362c : Rx timeout value : bit 27~16
1876 */
1877 zfDelayWriteInternalReg(dev, 0x1c362c, 0x0);
1878
1879 //Set USB Rx stream mode MAX packet number to 2
1880 // Max packet number = *0x1e1110 + 1
1881 zfDelayWriteInternalReg(dev, 0x1e1110, 0x4);
1882 //Set USB Rx stream mode timeout to 10us
1883 zfDelayWriteInternalReg(dev, 0x1e1114, 0x80);
1884
1885 //Set CPU clock frequency to 88/80MHz
1886 zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
1887
1888 //Set WLAN DMA interrupt mode : generate int per packet
1889 zfDelayWriteInternalReg(dev, 0x1c3d7c, 0x110011);
1890
1891 /* 7807 */
1892 /* enable func : Reset FIFO1 and FIFO2 when queue-gnt is low */
1893 /* 0x1c3bb0 Bit2 */
1894 /* Disable SwReset in firmware for TxHang, enable reset FIFO func. */
1895 zfDelayWriteInternalReg(dev, 0x1c3bb0, 0x4);
1896
1897 /* Disables the CF_END frame */
1898 zfDelayWriteInternalReg(dev, ZM_MAC_REG_TXOP_NOT_ENOUGH_INDICATION, 0x141E0F48);
1899
1900 /* Disable the SW Decrypt*/
1901 zfDelayWriteInternalReg(dev, 0x1c3678, 0x70);
1902 zfFlushDelayWrite(dev);
1903 //---------------------
1904
1905 /* Set TxQs CWMIN, CWMAX, AIFS and TXO to WME STA default. */
1906 zfUpdateDefaultQosParameter(dev, 0);
1907
1908 //zfSelAdcClk(dev, 0);
1909
1910 return;
1911 }
1912
1913
1914 u16_t zfHpSetSnifferMode(zdev_t* dev, u16_t on)
1915 {
1916 if (on != 0)
1917 {
1918 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000001);
1919 }
1920 else
1921 {
1922 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SNIFFER, 0x2000000);
1923 }
1924 zfFlushDelayWrite(dev);
1925 return 0;
1926 }
1927
1928
1929 u16_t zfHpSetApStaMode(zdev_t* dev, u8_t mode)
1930 {
1931 struct zsHpPriv* hpPriv;
1932
1933 zmw_get_wlan_dev(dev);
1934 hpPriv = wd->hpPrivate;
1935 hpPriv->dot11Mode = mode;
1936
1937 switch(mode)
1938 {
1939 case ZM_HAL_80211_MODE_AP:
1940 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000a1);
1941 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1942 break;
1943
1944 case ZM_HAL_80211_MODE_STA:
1945 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000002);
1946 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1947 break;
1948
1949 case ZM_HAL_80211_MODE_IBSS_GENERAL:
1950 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f000000);
1951 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x1);
1952 break;
1953
1954 case ZM_HAL_80211_MODE_IBSS_WPA2PSK:
1955 zfDelayWriteInternalReg(dev, 0x1c3700, 0x0f0000e0);
1956 zfDelayWriteInternalReg(dev, 0x1c3c40, 0x41); // for multiple ( > 2 ) stations IBSS network
1957 break;
1958
1959 default:
1960 goto skip;
1961 }
1962
1963 zfFlushDelayWrite(dev);
1964
1965 skip:
1966 return 0;
1967 }
1968
1969
1970 u16_t zfHpSetBssid(zdev_t* dev, u8_t* bssidSrc)
1971 {
1972 u32_t address;
1973 u16_t *bssid = (u16_t *)bssidSrc;
1974
1975 address = bssid[0] + (((u32_t)bssid[1]) << 16);
1976 zfDelayWriteInternalReg(dev, 0x1c3618, address);
1977
1978 address = (u32_t)bssid[2];
1979 zfDelayWriteInternalReg(dev, 0x1c361C, address);
1980 zfFlushDelayWrite(dev);
1981 return 0;
1982 }
1983
1984
1985 /************************************************************************/
1986 /* */
1987 /* FUNCTION DESCRIPTION zfHpUpdateQosParameter */
1988 /* Update TxQs CWMIN, CWMAX, AIFS and TXOP. */
1989 /* */
1990 /* INPUTS */
1991 /* dev : device pointer */
1992 /* cwminTbl : CWMIN parameter for TxQs */
1993 /* cwmaxTbl : CWMAX parameter for TxQs */
1994 /* aifsTbl: AIFS parameter for TxQs */
1995 /* txopTbl : TXOP parameter for TxQs */
1996 /* */
1997 /* OUTPUTS */
1998 /* none */
1999 /* */
2000 /* AUTHOR */
2001 /* Stephen ZyDAS Technology Corporation 2006.6 */
2002 /* */
2003 /************************************************************************/
2004 u8_t zfHpUpdateQosParameter(zdev_t* dev, u16_t* cwminTbl, u16_t* cwmaxTbl,
2005 u16_t* aifsTbl, u16_t* txopTbl)
2006 {
2007 struct zsHpPriv* hpPriv;
2008
2009 zmw_get_wlan_dev(dev);
2010 hpPriv = wd->hpPrivate;
2011
2012 zm_msg0_mm(ZM_LV_0, "zfHalUpdateQosParameter()");
2013
2014 /* Note : Do not change cwmin for Q0 in Ad Hoc mode */
2015 /* otherwise driver will fail in Wifi beacon distribution */
2016 if (hpPriv->dot11Mode == ZM_HAL_80211_MODE_STA)
2017 {
2018 #if 0 //Restore CWmin to improve down link throughput
2019 //cheating in BE traffic
2020 if (wd->sta.EnableHT == 1)
2021 {
2022 //cheating in BE traffic
2023 cwminTbl[0] = 7;//15;
2024 }
2025 #endif
2026 cwmaxTbl[0] = 127;//1023;
2027 aifsTbl[0] = 2*9+10;//3 * 9 + 10;
2028 }
2029
2030 /* CWMIN and CWMAX */
2031 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, cwminTbl[0]
2032 + ((u32_t)cwmaxTbl[0]<<16));
2033 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_CW, cwminTbl[1]
2034 + ((u32_t)cwmaxTbl[1]<<16));
2035 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC2_CW, cwminTbl[2]
2036 + ((u32_t)cwmaxTbl[2]<<16));
2037 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_CW, cwminTbl[3]
2038 + ((u32_t)cwmaxTbl[3]<<16));
2039 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC4_CW, cwminTbl[4]
2040 + ((u32_t)cwmaxTbl[4]<<16));
2041
2042 /* AIFS */
2043 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_AIFS, aifsTbl[0]
2044 +((u32_t)aifsTbl[0]<<12)+((u32_t)aifsTbl[0]<<24));
2045 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_AIFS, (aifsTbl[0]>>8)
2046 +((u32_t)aifsTbl[0]<<4)+((u32_t)aifsTbl[0]<<16));
2047
2048 /* TXOP */
2049 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, txopTbl[0]
2050 + ((u32_t)txopTbl[1]<<16));
2051 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC3_AC2_TXOP, txopTbl[2]
2052 + ((u32_t)txopTbl[3]<<16));
2053
2054 zfFlushDelayWrite(dev);
2055
2056 hpPriv->txop[0] = txopTbl[0];
2057 hpPriv->txop[1] = txopTbl[1];
2058 hpPriv->txop[2] = txopTbl[2];
2059 hpPriv->txop[3] = txopTbl[3];
2060 hpPriv->cwmin[0] = cwminTbl[0];
2061 hpPriv->cwmax[0] = cwmaxTbl[0];
2062 hpPriv->cwmin[1] = cwminTbl[1];
2063 hpPriv->cwmax[1] = cwmaxTbl[1];
2064
2065 return 0;
2066 }
2067
2068
2069 void zfHpSetAtimWindow(zdev_t* dev, u16_t atimWin)
2070 {
2071 zm_msg1_mm(ZM_LV_0, "Set ATIM window to ", atimWin);
2072 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ATIM_WINDOW, atimWin);
2073 zfFlushDelayWrite(dev);
2074 }
2075
2076
2077 void zfHpSetBasicRateSet(zdev_t* dev, u16_t bRateBasic, u16_t gRateBasic)
2078 {
2079 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BASIC_RATE, bRateBasic
2080 | ((u16_t)gRateBasic<<8));
2081 zfFlushDelayWrite(dev);
2082 }
2083
2084
2085 /* HT40 send by OFDM 6M */
2086 /* otherwise use reg 0x638 */
2087 void zfHpSetRTSCTSRate(zdev_t* dev, u32_t rate)
2088 {
2089 zfDelayWriteInternalReg(dev, ZM_MAC_REG_RTS_CTS_RATE, rate);
2090 zfFlushDelayWrite(dev);
2091 }
2092
2093 void zfHpSetMacAddress(zdev_t* dev, u16_t* macAddr, u16_t macAddrId)
2094 {
2095 if (macAddrId == 0)
2096 {
2097 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
2098 (((u32_t)macAddr[1])<<16) | macAddr[0]);
2099 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H, macAddr[2]);
2100 }
2101 else if (macAddrId <= 7)
2102 {
2103 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8),
2104 macAddr[0] + ((u32_t)macAddr[1]<<16));
2105 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ACK_TABLE+((macAddrId-1)*8)+4,
2106 macAddr[2]);
2107 }
2108 zfFlushDelayWrite(dev);
2109 }
2110
2111 void zfHpSetMulticastList(zdev_t* dev, u8_t size, u8_t* pList, u8_t bAllMulticast)
2112 {
2113 struct zsMulticastAddr* pMacList = (struct zsMulticastAddr*) pList;
2114 u8_t i;
2115 u32_t value;
2116 u32_t swRegMulHashValueH, swRegMulHashValueL;
2117
2118 swRegMulHashValueH = 0x80000000;
2119 swRegMulHashValueL = 0;
2120
2121 if ( bAllMulticast )
2122 {
2123 swRegMulHashValueH = swRegMulHashValueL = ~0;
2124 }
2125 else
2126 {
2127 for(i=0; i<size; i++)
2128 {
2129 value = pMacList[i].addr[5] >> 2;
2130
2131 if ( value < 32 )
2132 {
2133 swRegMulHashValueL |= (1 << value);
2134 }
2135 else
2136 {
2137 swRegMulHashValueH |= (1 << (value-32));
2138 }
2139 }
2140 }
2141
2142 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_L,
2143 swRegMulHashValueL);
2144 zfDelayWriteInternalReg(dev, ZM_MAC_REG_GROUP_HASH_TBL_H,
2145 swRegMulHashValueH);
2146 zfFlushDelayWrite(dev);
2147 return;
2148 }
2149
2150 /******************** Beacon ********************/
2151 void zfHpEnableBeacon(zdev_t* dev, u16_t mode, u16_t bcnInterval, u16_t dtim, u8_t enableAtim)
2152 {
2153 u32_t value;
2154
2155 zmw_get_wlan_dev(dev);
2156
2157 /* Beacon Ready */
2158 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_CTRL, 0);
2159 /* Beacon DMA buffer address */
2160 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2161
2162 value = bcnInterval;
2163
2164 value |= (((u32_t) dtim) << 16);
2165
2166 if (mode == ZM_MODE_AP)
2167 {
2168
2169 value |= 0x1000000;
2170 }
2171 else if (mode == ZM_MODE_IBSS)
2172 {
2173 value |= 0x2000000;
2174
2175 if ( enableAtim )
2176 {
2177 value |= 0x4000000;
2178 }
2179 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 1;
2180 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnInterval = value;
2181 }
2182 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
2183
2184 /* Beacon period and beacon enable */
2185 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, value);
2186 zfFlushDelayWrite(dev);
2187 }
2188
2189 void zfHpDisableBeacon(zdev_t* dev)
2190 {
2191 zmw_get_wlan_dev(dev);
2192
2193 ((struct zsHpPriv*)wd->hpPrivate)->ibssBcnEnabled = 0;
2194
2195 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
2196 zfFlushDelayWrite(dev);
2197 }
2198
2199 void zfHpLedCtrl(zdev_t* dev, u16_t ledId, u8_t mode)
2200 {
2201 u16_t state;
2202 zmw_get_wlan_dev(dev);
2203
2204 //zm_debug_msg1("LED ID=", ledId);
2205 //zm_debug_msg1("LED mode=", mode);
2206 if (ledId < 2)
2207 {
2208 if (((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] != mode)
2209 {
2210 ((struct zsHpPriv*)wd->hpPrivate)->ledMode[ledId] = mode;
2211
2212 state = ((struct zsHpPriv*)wd->hpPrivate)->ledMode[0]
2213 | (((struct zsHpPriv*)wd->hpPrivate)->ledMode[1]<<1);
2214 zfDelayWriteInternalReg(dev, 0x1d0104, state);
2215 zfFlushDelayWrite(dev);
2216 //zm_debug_msg0("Update LED");
2217 }
2218 }
2219 }
2220
2221 /************************************************************************/
2222 /* */
2223 /* FUNCTION DESCRIPTION zfHpResetTxRx */
2224 /* Reset Tx and Rx Desc. */
2225 /* */
2226 /* INPUTS */
2227 /* dev : device pointer */
2228 /* */
2229 /* OUTPUTS */
2230 /* 0 : success */
2231 /* other : fail */
2232 /* */
2233 /* AUTHOR */
2234 /* Chao-Wen Yang ZyDAS Technology Corporation 2007.3 */
2235 /* */
2236 /************************************************************************/
2237 u16_t zfHpUsbReset(zdev_t* dev)
2238 {
2239 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2240 u16_t ret = 0;
2241
2242 //zm_debug_msg0("CWY - Reset Tx and Rx");
2243
2244 cmd[0] = 0 | (ZM_CMD_RESET << 8);
2245
2246 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL);
2247 return ret;
2248 }
2249
2250 u16_t zfHpDKReset(zdev_t* dev, u8_t flag)
2251 {
2252 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
2253 u16_t ret = 0;
2254
2255 //zm_debug_msg0("CWY - Reset Tx and Rx");
2256
2257 cmd[0] = 4 | (ZM_CMD_DKRESET << 8);
2258 cmd[1] = flag;
2259
2260 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
2261 return ret;
2262 }
2263
2264 u32_t zfHpCwmUpdate(zdev_t* dev)
2265 {
2266 //u32_t cmd[3];
2267 //u16_t ret;
2268 //
2269 //cmd[0] = 0x00000008;
2270 //cmd[1] = 0x1c36e8;
2271 //cmd[2] = 0x1c36ec;
2272 //
2273 //ret = zfIssueCmd(dev, cmd, 12, ZM_CWM_READ, 0);
2274 //return ret;
2275
2276 struct zsHpPriv* hpPriv;
2277
2278 zmw_get_wlan_dev(dev);
2279 hpPriv=wd->hpPrivate;
2280
2281 zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(hpPriv->ctlBusy, hpPriv->extBusy));
2282
2283 hpPriv->ctlBusy = 0;
2284 hpPriv->extBusy = 0;
2285
2286 return 0;
2287 }
2288
2289 u32_t zfHpAniUpdate(zdev_t* dev)
2290 {
2291 u32_t cmd[5];
2292 u16_t ret;
2293
2294 cmd[0] = 0x00000010;
2295 cmd[1] = 0x1c36e8;
2296 cmd[2] = 0x1c36ec;
2297 cmd[3] = 0x1c3cb4;
2298 cmd[4] = 0x1c3cb8;
2299
2300 ret = zfIssueCmd(dev, cmd, 20, ZM_ANI_READ, 0);
2301 return ret;
2302 }
2303
2304 /*
2305 * Update Beacon RSSI in ANI
2306 */
2307 u32_t zfHpAniUpdateRssi(zdev_t* dev, u8_t rssi)
2308 {
2309 struct zsHpPriv* hpPriv;
2310
2311 zmw_get_wlan_dev(dev);
2312 hpPriv=wd->hpPrivate;
2313
2314 hpPriv->stats.ast_nodestats.ns_avgbrssi = rssi;
2315
2316 return 0;
2317 }
2318
2319 #define ZM_SEEPROM_MAC_ADDRESS_OFFSET (0x1400 + (0x106<<1))
2320 #define ZM_SEEPROM_REGDOMAIN_OFFSET (0x1400 + (0x104<<1))
2321 #define ZM_SEEPROM_VERISON_OFFSET (0x1400 + (0x102<<1))
2322 #define ZM_SEEPROM_HARDWARE_TYPE_OFFSET (0x1374)
2323 #define ZM_SEEPROM_HW_HEAVY_CLIP (0x161c)
2324
2325 u32_t zfHpGetMacAddress(zdev_t* dev)
2326 {
2327 u32_t cmd[7];
2328 u16_t ret;
2329
2330 cmd[0] = 0x00000000 | 24;
2331 cmd[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET;
2332 cmd[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4;
2333 cmd[3] = ZM_SEEPROM_REGDOMAIN_OFFSET;
2334 cmd[4] = ZM_SEEPROM_VERISON_OFFSET;
2335 cmd[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET;
2336 cmd[6] = ZM_SEEPROM_HW_HEAVY_CLIP;
2337
2338 ret = zfIssueCmd(dev, cmd, 28, ZM_MAC_READ, 0);
2339 return ret;
2340 }
2341
2342 u32_t zfHpGetTransmitPower(zdev_t* dev)
2343 {
2344 struct zsHpPriv* hpPriv;
2345 u16_t tpc = 0;
2346
2347 zmw_get_wlan_dev(dev);
2348 hpPriv = wd->hpPrivate;
2349
2350 if (hpPriv->hwFrequency < 3000) {
2351 tpc = hpPriv->tPow2x2g[0] & 0x3f;
2352 wd->maxTxPower2 &= 0x3f;
2353 tpc = (tpc > wd->maxTxPower2)? wd->maxTxPower2 : tpc;
2354 } else {
2355 tpc = hpPriv->tPow2x5g[0] & 0x3f;
2356 wd->maxTxPower5 &= 0x3f;
2357 tpc = (tpc > wd->maxTxPower5)? wd->maxTxPower5 : tpc;
2358 }
2359
2360 return tpc;
2361 }
2362
2363 u8_t zfHpGetMinTxPower(zdev_t* dev)
2364 {
2365 struct zsHpPriv* hpPriv;
2366 u8_t tpc = 0;
2367
2368 zmw_get_wlan_dev(dev);
2369 hpPriv = wd->hpPrivate;
2370
2371 if (hpPriv->hwFrequency < 3000)
2372 {
2373 if(wd->BandWidth40)
2374 {
2375 //40M
2376 tpc = (hpPriv->tPow2x2gHt40[7]&0x3f);
2377 }
2378 else
2379 {
2380 //20M
2381 tpc = (hpPriv->tPow2x2gHt20[7]&0x3f);
2382 }
2383 }
2384 else
2385 {
2386 if(wd->BandWidth40)
2387 {
2388 //40M
2389 tpc = (hpPriv->tPow2x5gHt40[7]&0x3f);
2390 }
2391 else
2392 {
2393 //20M
2394 tpc = (hpPriv->tPow2x5gHt20[7]&0x3f);
2395 }
2396 }
2397
2398 return tpc;
2399 }
2400
2401 u8_t zfHpGetMaxTxPower(zdev_t* dev)
2402 {
2403 struct zsHpPriv* hpPriv;
2404 u8_t tpc = 0;
2405
2406 zmw_get_wlan_dev(dev);
2407 hpPriv = wd->hpPrivate;
2408
2409 if (hpPriv->hwFrequency < 3000)
2410 {
2411 tpc = (hpPriv->tPow2xCck[0]&0x3f);
2412 }
2413 else
2414 {
2415 tpc =(hpPriv->tPow2x5g[0]&0x3f);
2416 }
2417
2418 return tpc;
2419 }
2420
2421 u32_t zfHpLoadEEPROMFromFW(zdev_t* dev)
2422 {
2423 u32_t cmd[16];
2424 u32_t ret=0, i, j;
2425 zmw_get_wlan_dev(dev);
2426
2427 i = ((struct zsHpPriv*)wd->hpPrivate)->eepromImageRdReq;
2428
2429 cmd[0] = ZM_HAL_MAX_EEPROM_PRQ*4;
2430
2431 for (j=0; j<ZM_HAL_MAX_EEPROM_PRQ; j++)
2432 {
2433 cmd[j+1] = 0x1000 + (((i*ZM_HAL_MAX_EEPROM_PRQ) + j)*4);
2434 }
2435
2436 ret = zfIssueCmd(dev, cmd, (ZM_HAL_MAX_EEPROM_PRQ+1)*4, ZM_EEPROM_READ, 0);
2437
2438 return ret;
2439 }
2440
2441 void zfHpHeartBeat(zdev_t* dev)
2442 {
2443 struct zsHpPriv* hpPriv;
2444 u8_t polluted = 0;
2445 u8_t ackTpc;
2446
2447 zmw_get_wlan_dev(dev);
2448 hpPriv=wd->hpPrivate;
2449
2450 /* Workaround : Make OTUS fire more beacon in ad hoc mode in 2.4GHz */
2451 if (hpPriv->ibssBcnEnabled != 0)
2452 {
2453 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2454 {
2455 if ((wd->tick % 10) == 0)
2456 {
2457 if ((wd->tick % 40) == 0)
2458 {
2459 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval-1);
2460 polluted = 1;
2461 }
2462 else
2463 {
2464 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, hpPriv->ibssBcnInterval);
2465 polluted = 1;
2466 }
2467 }
2468 }
2469 }
2470
2471 if ((wd->tick & 0x3f) == 0x25)
2472 {
2473 /* Workaround for beacon stuck after SW reset */
2474 if (hpPriv->ibssBcnEnabled != 0)
2475 {
2476 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_ADDR, ZM_BEACON_BUFFER_ADDRESS);
2477 polluted = 1;
2478 }
2479
2480 //DbgPrint("hpPriv->aggMaxDurationBE=%d", hpPriv->aggMaxDurationBE);
2481 //DbgPrint("wd->sta.avgSizeOfReceivePackets=%d", wd->sta.avgSizeOfReceivePackets);
2482 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2483 && (zfStaIsConnected(dev))
2484 && (wd->sta.EnableHT == 1) //11n mode
2485 && (wd->BandWidth40 == 1) //40MHz mode
2486 && (wd->sta.enableDrvBA ==0) //Marvel AP
2487 && (hpPriv->aggMaxDurationBE > 2000) //BE TXOP > 2ms
2488 && (wd->sta.avgSizeOfReceivePackets > 1420))
2489 {
2490 zfDelayWriteInternalReg(dev, 0x1c3b9c, 0x8000a);
2491 polluted = 1;
2492 }
2493 else
2494 {
2495 zfDelayWriteInternalReg(dev, 0x1c3b9c, hpPriv->aggPktNum);
2496 polluted = 1;
2497 }
2498
2499 if (wd->dynamicSIFSEnable == 0)
2500 {
2501 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2502 && (zfStaIsConnected(dev))
2503 && (wd->sta.EnableHT == 1) //11n mode
2504 && (wd->BandWidth40 == 0) //20MHz mode
2505 && (wd->sta.enableDrvBA ==0)) //Marvel AP
2506 {
2507 zfDelayWriteInternalReg(dev, 0x1c3698, 0x5144000);
2508 polluted = 1;
2509 }
2510 else
2511 {
2512 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2513 polluted = 1;
2514 }
2515 }
2516 else
2517 {
2518 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2519 && (zfStaIsConnected(dev))
2520 && (wd->sta.EnableHT == 1) //11n mode
2521 && (wd->sta.athOwlAp == 1)) //Atheros AP
2522 {
2523 if (hpPriv->retransmissionEvent)
2524 {
2525 switch(hpPriv->latestSIFS)
2526 {
2527 case 0:
2528 hpPriv->latestSIFS = 1;
2529 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0x8144000);
2530 break;
2531 case 1:
2532 hpPriv->latestSIFS = 2;
2533 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2534 break;
2535 case 2:
2536 hpPriv->latestSIFS = 3;
2537 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xc144000);
2538 break;
2539 case 3:
2540 hpPriv->latestSIFS = 0;
2541 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2542 break;
2543 default:
2544 hpPriv->latestSIFS = 0;
2545 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, 0xa144000);
2546 break;
2547 }
2548 polluted = 1;
2549 zm_debug_msg1("##### Correct Tx retransmission issue #####, ", hpPriv->latestSIFS);
2550 hpPriv->retransmissionEvent = 0;
2551 }
2552 }
2553 else
2554 {
2555 hpPriv->latestSIFS = 0;
2556 hpPriv->retransmissionEvent = 0;
2557 zfDelayWriteInternalReg(dev, 0x1c3698, 0xA144000);
2558 polluted = 1;
2559 }
2560 }
2561
2562 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2563 {
2564 #define ZM_SIGNAL_THRESHOLD 66
2565 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2566 && (zfStaIsConnected(dev))
2567 && (wd->SignalStrength > ZM_SIGNAL_THRESHOLD))
2568 {
2569 /* remove state handle, always rewrite register setting */
2570 //if (hpPriv->strongRSSI == 0)
2571 {
2572 hpPriv->strongRSSI = 1;
2573 /* Strong RSSI, set ACK to one Tx stream and lower Tx power 7dbm */
2574 if (hpPriv->currentAckRtsTpc > (14+10))
2575 {
2576 ackTpc = hpPriv->currentAckRtsTpc - 14;
2577 }
2578 else
2579 {
2580 ackTpc = 10;
2581 }
2582 zfDelayWriteInternalReg(dev, 0x1c3694, ((ackTpc) << 20) | (0x1<<26));
2583 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((ackTpc) << 5 ) | (0x1<<11) |
2584 ((ackTpc) << 21) | (0x1<<27) );
2585 polluted = 1;
2586 }
2587 }
2588 else
2589 {
2590 /* remove state handle, always rewrite register setting */
2591 //if (hpPriv->strongRSSI == 1)
2592 {
2593 hpPriv->strongRSSI = 0;
2594 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
2595 {
2596 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x1<<26));
2597 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x1<<11) |
2598 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x1<<27) );
2599 }
2600 else
2601 {
2602 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
2603 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
2604 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
2605 }
2606 polluted = 1;
2607 }
2608 }
2609 #undef ZM_SIGNAL_THRESHOLD
2610 }
2611
2612 if ((hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM) == 0)
2613 {
2614 if ((wd->sta.bScheduleScan == FALSE) && (wd->sta.bChannelScan == FALSE))
2615 {
2616 #define ZM_RX_SIGNAL_THRESHOLD_H 71
2617 #define ZM_RX_SIGNAL_THRESHOLD_L 66
2618 u8_t rxSignalThresholdH = ZM_RX_SIGNAL_THRESHOLD_H;
2619 u8_t rxSignalThresholdL = ZM_RX_SIGNAL_THRESHOLD_L;
2620 #undef ZM_RX_SIGNAL_THRESHOLD_H
2621 #undef ZM_RX_SIGNAL_THRESHOLD_L
2622
2623 if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2624 && (zfStaIsConnected(dev))
2625 && (wd->SignalStrength > rxSignalThresholdH)
2626 )//&& (hpPriv->rxStrongRSSI == 0))
2627 {
2628 hpPriv->rxStrongRSSI = 1;
2629 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1220);
2630 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x900);
2631 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x900);
2632 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x900);
2633 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2634 {
2635 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2636 {
2637 zfDelayWriteInternalReg(dev, 0x1c8960, 0x900);
2638 }
2639 else
2640 {
2641 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2642 }
2643 }
2644 else
2645 {
2646 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2647 }
2648 polluted = 1;
2649 }
2650 else if (( wd->wlanMode == ZM_MODE_INFRASTRUCTURE )
2651 && (zfStaIsConnected(dev))
2652 && (wd->SignalStrength > rxSignalThresholdL)
2653 )//&& (hpPriv->rxStrongRSSI == 1))
2654 {
2655 //Do nothing to prevent frequently Rx switching
2656 }
2657 else
2658 {
2659 /* remove state handle, always rewrite register setting */
2660 //if (hpPriv->rxStrongRSSI == 1)
2661 {
2662 hpPriv->rxStrongRSSI = 0;
2663 //zfDelayWriteInternalReg(dev, 0x1c5964, 0x1120);
2664 //zfDelayWriteInternalReg(dev, 0x1c5960, 0x9b40);
2665 //zfDelayWriteInternalReg(dev, 0x1c6960, 0x9b40);
2666 //zfDelayWriteInternalReg(dev, 0x1c7960, 0x9b40);
2667 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
2668 {
2669 if (hpPriv->hwFrequency <= ZM_CH_G_14)
2670 {
2671 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
2672 }
2673 else
2674 {
2675 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
2676 }
2677 }
2678 else
2679 {
2680 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
2681 }
2682 polluted = 1;
2683 }
2684 }
2685
2686 }
2687 }
2688
2689 if (hpPriv->usbAcSendBytes[3] > (hpPriv->usbAcSendBytes[0]*2))
2690 {
2691 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[3]);
2692 polluted = 1;
2693 }
2694 else if (hpPriv->usbAcSendBytes[2] > (hpPriv->usbAcSendBytes[0]*2))
2695 {
2696 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[2]);
2697 polluted = 1;
2698 }
2699 else if (hpPriv->usbAcSendBytes[1] > (hpPriv->usbAcSendBytes[0]*2))
2700 {
2701 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[1]+((u32_t)hpPriv->cwmax[1]<<16));
2702 polluted = 1;
2703 }
2704 else
2705 {
2706 if (hpPriv->slotType == 1)
2707 {
2708 if ((wd->sta.enableDrvBA ==0) //Marvel AP
2709 && (hpPriv->aggMaxDurationBE > 2000)) //BE TXOP > 2ms
2710 {
2711 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, (hpPriv->cwmin[0]/2)+((u32_t)hpPriv->cwmax[0]<<16));
2712 }
2713 else
2714 {
2715 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2716 }
2717 polluted = 1;
2718 }
2719 else
2720 {
2721 /* Compensation for 20us slot time */
2722 //zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, 58+((u32_t)hpPriv->cwmax[0]<<16));
2723 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC0_CW, hpPriv->cwmin[0]+((u32_t)hpPriv->cwmax[0]<<16));
2724 polluted = 1;
2725 }
2726
2727 if ((wd->sta.SWEncryptEnable & (ZM_SW_TKIP_ENCRY_EN|ZM_SW_WEP_ENCRY_EN)) == 0)
2728 {
2729 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, hpPriv->txop[0]);
2730 polluted = 1;
2731 }
2732 else
2733 {
2734 zfDelayWriteInternalReg(dev, ZM_MAC_REG_AC1_AC0_TXOP, 0x30);
2735 polluted = 1;
2736 }
2737
2738 }
2739 hpPriv->usbAcSendBytes[3] = 0;
2740 hpPriv->usbAcSendBytes[2] = 0;
2741 hpPriv->usbAcSendBytes[1] = 0;
2742 hpPriv->usbAcSendBytes[0] = 0;
2743 }
2744
2745 if (polluted == 1)
2746 {
2747 zfFlushDelayWrite(dev);
2748 }
2749
2750 return;
2751 }
2752
2753 /*
2754 * 0x1d4008 : AHB, DAC, ADC clock selection
2755 * bit1~0 AHB_CLK : AHB clock selection,
2756 * 00 : OSC 40MHz;
2757 * 01 : 20MHz in A mode, 22MHz in G mode;
2758 * 10 : 40MHz in A mode, 44MHz in G mode;
2759 * 11 : 80MHz in A mode, 88MHz in G mode.
2760 * bit3~2 CLK_SEL : Select the clock source of clk160 in ADDAC.
2761 * 00 : PLL divider's output;
2762 * 01 : PLL divider's output divided by 2;
2763 * 10 : PLL divider's output divided by 4;
2764 * 11 : REFCLK from XTALOSCPAD.
2765 */
2766 void zfSelAdcClk(zdev_t* dev, u8_t bw40, u32_t frequency)
2767 {
2768 if(bw40 == 1)
2769 {
2770 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x73);
2771 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x10A);
2772 zfFlushDelayWrite(dev);
2773 }
2774 else
2775 {
2776 //zfDelayWriteInternalReg(dev, 0x1D4008, 0x70);
2777 if ( frequency <= ZM_CH_G_14 )
2778 {
2779 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x105);
2780 }
2781 else
2782 {
2783 zfDelayWriteInternalReg(dev, ZM_MAC_REG_DYNAMIC_SIFS_ACK, 0x104);
2784 }
2785 zfFlushDelayWrite(dev);
2786 }
2787 }
2788
2789 u32_t zfHpEchoCommand(zdev_t* dev, u32_t value)
2790 {
2791 u32_t cmd[2];
2792 u16_t ret;
2793
2794 cmd[0] = 0x00008004;
2795 cmd[1] = value;
2796
2797 ret = zfIssueCmd(dev, cmd, 8, ZM_CMD_ECHO, NULL);
2798 return ret;
2799 }
2800
2801 #ifdef ZM_DRV_INIT_USB_MODE
2802
2803 #define ZM_USB_US_STREAM_MODE 0x00000000
2804 #define ZM_USB_US_PACKET_MODE 0x00000008
2805 #define ZM_USB_DS_ENABLE 0x00000001
2806 #define ZM_USB_US_ENABLE 0x00000002
2807
2808 #define ZM_USB_RX_STREAM_4K 0x00000000
2809 #define ZM_USB_RX_STREAM_8K 0x00000010
2810 #define ZM_USB_RX_STREAM_16K 0x00000020
2811 #define ZM_USB_RX_STREAM_32K 0x00000030
2812
2813 #define ZM_USB_TX_STREAM_MODE 0x00000040
2814
2815 #define ZM_USB_MODE_CTRL_REG 0x001E1108
2816
2817 void zfInitUsbMode(zdev_t* dev)
2818 {
2819 u32_t mode;
2820 zmw_get_wlan_dev(dev);
2821
2822 /* TODO: Set USB mode by reading registery */
2823 mode = ZM_USB_DS_ENABLE | ZM_USB_US_ENABLE | ZM_USB_US_PACKET_MODE;
2824
2825 zfDelayWriteInternalReg(dev, ZM_USB_MODE_CTRL_REG, mode);
2826 zfFlushDelayWrite(dev);
2827 }
2828 #endif
2829
2830 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage);
2831 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40);
2832 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40);
2833
2834
2835 s32_t zfInterpolateFunc(s32_t x, s32_t x1, s32_t y1, s32_t x2, s32_t y2)
2836 {
2837 s32_t y;
2838
2839 if (y2 == y1)
2840 {
2841 y = y1;
2842 }
2843 else if (x == x1)
2844 {
2845 y = y1;
2846 }
2847 else if (x == x2)
2848 {
2849 y = y2;
2850 }
2851 else if (x2 != x1)
2852 {
2853 y = y1 + (((y2-y1) * (x-x1))/(x2-x1));
2854 }
2855 else
2856 {
2857 y = y1;
2858 }
2859
2860 return y;
2861 }
2862
2863 //#define ZM_ENABLE_TPC_WINDOWS_DEBUG
2864 //#define ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
2865
2866 /* the tx power offset workaround for ART vs NDIS/MDK */
2867 #define HALTX_POWER_OFFSET 0
2868
2869 u8_t zfInterpolateFuncX(u8_t x, u8_t x1, u8_t y1, u8_t x2, u8_t y2)
2870 {
2871 s32_t y;
2872 s32_t inc;
2873
2874 #define ZM_MULTIPLIER 8
2875 y = zfInterpolateFunc((s32_t)x<<ZM_MULTIPLIER,
2876 (s32_t)x1<<ZM_MULTIPLIER,
2877 (s32_t)y1<<ZM_MULTIPLIER,
2878 (s32_t)x2<<ZM_MULTIPLIER,
2879 (s32_t)y2<<ZM_MULTIPLIER);
2880
2881 inc = (y & (1<<(ZM_MULTIPLIER-1))) >> (ZM_MULTIPLIER-1);
2882 y = (y >> ZM_MULTIPLIER) + inc;
2883 #undef ZM_MULTIPLIER
2884
2885 return (u8_t)y;
2886 }
2887
2888 u8_t zfGetInterpolatedValue(u8_t x, u8_t* x_array, u8_t* y_array)
2889 {
2890 s32_t y;
2891 u16_t xIndex;
2892
2893 if (x <= x_array[1])
2894 {
2895 xIndex = 0;
2896 }
2897 else if (x <= x_array[2])
2898 {
2899 xIndex = 1;
2900 }
2901 else if (x <= x_array[3])
2902 {
2903 xIndex = 2;
2904 }
2905 else //(x > x_array[3])
2906 {
2907 xIndex = 3;
2908 }
2909
2910 y = zfInterpolateFuncX(x,
2911 x_array[xIndex],
2912 y_array[xIndex],
2913 x_array[xIndex+1],
2914 y_array[xIndex+1]);
2915
2916 return (u8_t)y;
2917 }
2918
2919 u8_t zfFindFreqIndex(u8_t f, u8_t* fArray, u8_t fArraySize)
2920 {
2921 u8_t i;
2922 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2923 DbgPrint("f=%d ", f);
2924 for (i=0; i<fArraySize; i++)
2925 {
2926 DbgPrint("%d ", fArray[i]);
2927 }
2928 DbgPrint("\n");
2929 #endif
2930 i=fArraySize-2;
2931 while(1)
2932 {
2933 if (f >= fArray[i])
2934 {
2935 return i;
2936 }
2937 if (i!=0)
2938 {
2939 i--;
2940 }
2941 else
2942 {
2943 return 0;
2944 }
2945 }
2946 }
2947
2948
2949
2950
2951 void zfInitPowerCal(zdev_t* dev)
2952 {
2953 //Program PHY Tx power relatives registers
2954 #define zm_write_phy_reg(cr, val) reg_write((cr*4)+0x9800, val)
2955
2956 zm_write_phy_reg(79, 0x7f);
2957 zm_write_phy_reg(77, 0x3f3f3f3f);
2958 zm_write_phy_reg(78, 0x3f3f3f3f);
2959 zm_write_phy_reg(653, 0x3f3f3f3f);
2960 zm_write_phy_reg(654, 0x3f3f3f3f);
2961 zm_write_phy_reg(739, 0x3f3f3f3f);
2962 zm_write_phy_reg(740, 0x3f3f3f3f);
2963 zm_write_phy_reg(755, 0x3f3f3f3f);
2964 zm_write_phy_reg(756, 0x3f3f3f3f);
2965 zm_write_phy_reg(757, 0x3f3f3f3f);
2966
2967 #undef zm_write_phy_reg
2968 }
2969
2970
2971
2972 void zfPrintTp(u8_t* pwr0, u8_t* vpd0, u8_t* pwr1, u8_t* vpd1)
2973 {
2974 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
2975 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
2976 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
2977 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
2978 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
2979 #endif
2980 }
2981
2982
2983 /*
2984 * To find CTL index(0~23)
2985 * return 24(AR5416_NUM_CTLS)=>no desired index found
2986 */
2987 u8_t zfFindCtlEdgesIndex(zdev_t* dev, u8_t desired_CtlIndex)
2988 {
2989 u8_t i;
2990 struct zsHpPriv* hpPriv;
2991 struct ar5416Eeprom* eepromImage;
2992
2993 zmw_get_wlan_dev(dev);
2994
2995 hpPriv = wd->hpPrivate;
2996
2997 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
2998
2999 //for (i = 0; (i < AR5416_NUM_CTLS) && eepromImage->ctlIndex[i]; i++)
3000 for (i = 0; i < AR5416_NUM_CTLS; i++)
3001 {
3002 if(desired_CtlIndex == eepromImage->ctlIndex[i])
3003 break;
3004 }
3005 return i;
3006 }
3007
3008 /**************************************************************************
3009 * fbin2freq
3010 *
3011 * Get channel value from binary representation held in eeprom
3012 * RETURNS: the frequency in MHz
3013 */
3014 u32_t
3015 fbin2freq(u8_t fbin, u8_t is2GHz)
3016 {
3017 /*
3018 * Reserved value 0xFF provides an empty definition both as
3019 * an fbin and as a frequency - do not convert
3020 */
3021 if (fbin == AR5416_BCHAN_UNUSED) {
3022 return fbin;
3023 }
3024
3025 return (u32_t)((is2GHz==1) ? (2300 + fbin) : (4800 + 5 * fbin));
3026 }
3027
3028
3029 u8_t zfGetMaxEdgePower(zdev_t* dev, CAL_CTL_EDGES *pCtlEdges, u32_t freq)
3030 {
3031 u8_t i;
3032 u8_t maxEdgePower;
3033 u8_t is2GHz;
3034 struct zsHpPriv* hpPriv;
3035 struct ar5416Eeprom* eepromImage;
3036
3037 zmw_get_wlan_dev(dev);
3038
3039 hpPriv = wd->hpPrivate;
3040
3041 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3042
3043 if(freq > ZM_CH_G_14)
3044 is2GHz = 0;
3045 else
3046 is2GHz = 1;
3047
3048 maxEdgePower = AR5416_MAX_RATE_POWER;
3049
3050 /* Get the edge power */
3051 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3052 {
3053 /*
3054 * If there's an exact channel match or an inband flag set
3055 * on the lower channel use the given rdEdgePower
3056 */
3057 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3058 {
3059 maxEdgePower = pCtlEdges[i].tPower;
3060 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3061 zm_dbg(("zfGetMaxEdgePower index i = %d \n", i));
3062 #endif
3063 break;
3064 }
3065 else if ((i > 0) && (freq < fbin2freq(pCtlEdges[i].bChannel, is2GHz)))
3066 {
3067 if (fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) < freq && pCtlEdges[i - 1].flag)
3068 {
3069 maxEdgePower = pCtlEdges[i - 1].tPower;
3070 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3071 zm_dbg(("zfGetMaxEdgePower index i-1 = %d \n", i-1));
3072 #endif
3073 }
3074 /* Leave loop - no more affecting edges possible in this monotonic increasing list */
3075 break;
3076 }
3077
3078 }
3079
3080 if( i == AR5416_NUM_BAND_EDGES )
3081 {
3082 if (freq > fbin2freq(pCtlEdges[i - 1].bChannel, is2GHz) && pCtlEdges[i - 1].flag)
3083 {
3084 maxEdgePower = pCtlEdges[i - 1].tPower;
3085 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3086 zm_dbg(("zfGetMaxEdgePower index=>i-1 = %d \n", i-1));
3087 #endif
3088 }
3089 }
3090
3091 zm_assert(maxEdgePower > 0);
3092
3093 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3094 if ( maxEdgePower == AR5416_MAX_RATE_POWER )
3095 {
3096 zm_dbg(("zfGetMaxEdgePower = %d !!!\n", AR5416_MAX_RATE_POWER));
3097 }
3098 #endif
3099 return maxEdgePower;
3100 }
3101
3102 u32_t zfAdjustHT40FreqOffset(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3103 {
3104 u32_t newFreq = frequency;
3105
3106 if (bw40 == 1)
3107 {
3108 if (extOffset == 1)
3109 {
3110 newFreq += 10;
3111 }
3112 else
3113 {
3114 newFreq -= 10;
3115 }
3116 }
3117 return newFreq;
3118 }
3119
3120 u32_t zfHpCheckDoHeavyClip(zdev_t* dev, u32_t freq, CAL_CTL_EDGES *pCtlEdges, u8_t bw40)
3121 {
3122 u32_t ret = 0;
3123 u8_t i;
3124 u8_t is2GHz;
3125 struct zsHpPriv* hpPriv;
3126
3127 zmw_get_wlan_dev(dev);
3128
3129 hpPriv = wd->hpPrivate;
3130
3131 if(freq > ZM_CH_G_14)
3132 is2GHz = 0;
3133 else
3134 is2GHz = 1;
3135
3136 /* HT40 force enable heavy clip */
3137 if (bw40)
3138 {
3139 ret |= 0xf0;
3140 }
3141 #if 1
3142 /* HT20 : frequency bandedge */
3143 for (i = 0; (i < AR5416_NUM_BAND_EDGES) && (pCtlEdges[i].bChannel != AR5416_BCHAN_UNUSED) ; i++)
3144 {
3145 if (freq == fbin2freq(pCtlEdges[i].bChannel, is2GHz))
3146 {
3147 if (pCtlEdges[i].flag == 0)
3148 {
3149 ret |= 0xf;
3150 }
3151 break;
3152 }
3153 }
3154 #endif
3155
3156 return ret;
3157 }
3158
3159
3160 void zfSetPowerCalTable(zdev_t* dev, u32_t frequency, u8_t bw40, u8_t extOffset)
3161 {
3162 struct ar5416Eeprom* eepromImage;
3163 u8_t pwr0[5];
3164 u8_t pwr1[5];
3165 u8_t vpd0[5];
3166 u8_t vpd1[5];
3167 u8_t vpd_chain1[128];
3168 u8_t vpd_chain3[128];
3169 u16_t boundary1 = 18; //CR 667
3170 u16_t powerTxMax = 63; //CR 79
3171 u8_t i;
3172 struct zsHpPriv* hpPriv;
3173 u8_t fbin;
3174 u8_t index, max2gIndex, max5gIndex;
3175 u8_t chain0pwrPdg0[5];
3176 u8_t chain0vpdPdg0[5];
3177 u8_t chain0pwrPdg1[5];
3178 u8_t chain0vpdPdg1[5];
3179 u8_t chain2pwrPdg0[5];
3180 u8_t chain2vpdPdg0[5];
3181 u8_t chain2pwrPdg1[5];
3182 u8_t chain2vpdPdg1[5];
3183 u8_t fbinArray[8];
3184
3185 /* 4 CTL */
3186 u8_t ctl_i;
3187 u8_t desired_CtlIndex;
3188
3189 u8_t ctlEdgesMaxPowerCCK = AR5416_MAX_RATE_POWER;
3190 u8_t ctlEdgesMaxPower2G = AR5416_MAX_RATE_POWER;
3191 u8_t ctlEdgesMaxPower2GHT20 = AR5416_MAX_RATE_POWER;
3192 u8_t ctlEdgesMaxPower2GHT40 = AR5416_MAX_RATE_POWER;
3193 u8_t ctlEdgesMaxPower5G = AR5416_MAX_RATE_POWER;
3194 u8_t ctlEdgesMaxPower5GHT20 = AR5416_MAX_RATE_POWER;
3195 u8_t ctlEdgesMaxPower5GHT40 = AR5416_MAX_RATE_POWER;
3196
3197 u8_t ctlOffset;
3198
3199 zmw_get_wlan_dev(dev);
3200
3201 hpPriv = wd->hpPrivate;
3202
3203 eepromImage = (struct ar5416Eeprom*)&(hpPriv->eepromImage[(1024+512)/4]);
3204
3205 // Check the total bytes of the EEPROM structure to see the dongle have been calibrated or not.
3206 if (eepromImage->baseEepHeader.length == 0xffff)
3207 {
3208 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3209 zm_dbg(("Warning! This dongle not been calibrated\n"));
3210 #endif
3211 return;
3212 }
3213
3214 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3215 DbgPrint("-----zfSetPowerCalTable : frequency=%d-----\n", frequency);
3216 #endif
3217 /* TODO : 1. boundary1 and powerTxMax should be refered to CR667 and CR79 */
3218 /* in otus.ini file */
3219
3220 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3221 /* 2. Interpolate pwr and vpd test points from frequency */
3222 DbgPrint("calFreqPier5G : %d, %d, %d, %d ,%d, %d, %d, %d\n",
3223 eepromImage->calFreqPier5G[0]*5+4800,
3224 eepromImage->calFreqPier5G[1]*5+4800,
3225 eepromImage->calFreqPier5G[2]*5+4800,
3226 eepromImage->calFreqPier5G[3]*5+4800,
3227 eepromImage->calFreqPier5G[4]*5+4800,
3228 eepromImage->calFreqPier5G[5]*5+4800,
3229 eepromImage->calFreqPier5G[6]*5+4800,
3230 eepromImage->calFreqPier5G[7]*5+4800
3231 );
3232 DbgPrint("calFreqPier2G : %d, %d, %d, %d\n",
3233 eepromImage->calFreqPier2G[0]+2300,
3234 eepromImage->calFreqPier2G[1]+2300,
3235 eepromImage->calFreqPier2G[2]+2300,
3236 eepromImage->calFreqPier2G[3]+2300
3237 );
3238 #endif
3239 if (frequency < 3000)
3240 {
3241 for (i=0; i<4; i++)
3242 {
3243 if (eepromImage->calFreqPier2G[i] == 0xff)
3244 {
3245 break;
3246 }
3247 }
3248 max2gIndex = i;
3249 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3250 DbgPrint("max2gIndex : %d\n", max2gIndex);
3251 #endif
3252 fbin = (u8_t)(frequency - 2300);
3253 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier2G, max2gIndex);
3254 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3255 DbgPrint("2G index : %d\n", index);
3256 DbgPrint("chain 0 index\n");
3257 #endif
3258 zfPrintTp(&eepromImage->calPierData2G[0][index].pwrPdg[0][0],
3259 &eepromImage->calPierData2G[0][index].vpdPdg[0][0],
3260 &eepromImage->calPierData2G[0][index].pwrPdg[1][0],
3261 &eepromImage->calPierData2G[0][index].vpdPdg[1][0]
3262 );
3263 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3264 DbgPrint("chain 0 index+1\n");
3265 #endif
3266 zfPrintTp(&eepromImage->calPierData2G[0][index+1].pwrPdg[0][0],
3267 &eepromImage->calPierData2G[0][index+1].vpdPdg[0][0],
3268 &eepromImage->calPierData2G[0][index+1].pwrPdg[1][0],
3269 &eepromImage->calPierData2G[0][index+1].vpdPdg[1][0]
3270 );
3271
3272 for (i=0; i<5; i++)
3273 {
3274 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3275 eepromImage->calFreqPier2G[index],
3276 eepromImage->calPierData2G[0][index].pwrPdg[0][i],
3277 eepromImage->calFreqPier2G[index+1],
3278 eepromImage->calPierData2G[0][index+1].pwrPdg[0][i]
3279 );
3280 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3281 eepromImage->calFreqPier2G[index],
3282 eepromImage->calPierData2G[0][index].vpdPdg[0][i],
3283 eepromImage->calFreqPier2G[index+1],
3284 eepromImage->calPierData2G[0][index+1].vpdPdg[0][i]
3285 );
3286 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3287 eepromImage->calFreqPier2G[index],
3288 eepromImage->calPierData2G[0][index].pwrPdg[1][i],
3289 eepromImage->calFreqPier2G[index+1],
3290 eepromImage->calPierData2G[0][index+1].pwrPdg[1][i]
3291 );
3292 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3293 eepromImage->calFreqPier2G[index],
3294 eepromImage->calPierData2G[0][index].vpdPdg[1][i],
3295 eepromImage->calFreqPier2G[index+1],
3296 eepromImage->calPierData2G[0][index+1].vpdPdg[1][i]
3297 );
3298
3299 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3300 eepromImage->calFreqPier2G[index],
3301 eepromImage->calPierData2G[1][index].pwrPdg[0][i],
3302 eepromImage->calFreqPier2G[index+1],
3303 eepromImage->calPierData2G[1][index+1].pwrPdg[0][i]
3304 );
3305 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3306 eepromImage->calFreqPier2G[index],
3307 eepromImage->calPierData2G[1][index].vpdPdg[0][i],
3308 eepromImage->calFreqPier2G[index+1],
3309 eepromImage->calPierData2G[1][index+1].vpdPdg[0][i]
3310 );
3311 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3312 eepromImage->calFreqPier2G[index],
3313 eepromImage->calPierData2G[1][index].pwrPdg[1][i],
3314 eepromImage->calFreqPier2G[index+1],
3315 eepromImage->calPierData2G[1][index+1].pwrPdg[1][i]
3316 );
3317 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3318 eepromImage->calFreqPier2G[index],
3319 eepromImage->calPierData2G[1][index].vpdPdg[1][i],
3320 eepromImage->calFreqPier2G[index+1],
3321 eepromImage->calPierData2G[1][index+1].vpdPdg[1][i]
3322 );
3323 }
3324 }
3325 else
3326 {
3327 for (i=0; i<8; i++)
3328 {
3329 if (eepromImage->calFreqPier5G[i] == 0xff)
3330 {
3331 break;
3332 }
3333 }
3334 max5gIndex = i;
3335 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3336 DbgPrint("max5gIndex : %d\n", max5gIndex);
3337 #endif
3338 fbin = (u8_t)((frequency - 4800)/5);
3339 index = zfFindFreqIndex(fbin, eepromImage->calFreqPier5G, max5gIndex);
3340 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3341 DbgPrint("5G index : %d\n", index);
3342 #endif
3343
3344 for (i=0; i<5; i++)
3345 {
3346 chain0pwrPdg0[i] = zfInterpolateFuncX(fbin,
3347 eepromImage->calFreqPier5G[index],
3348 eepromImage->calPierData5G[0][index].pwrPdg[0][i],
3349 eepromImage->calFreqPier5G[index+1],
3350 eepromImage->calPierData5G[0][index+1].pwrPdg[0][i]
3351 );
3352 chain0vpdPdg0[i] = zfInterpolateFuncX(fbin,
3353 eepromImage->calFreqPier5G[index],
3354 eepromImage->calPierData5G[0][index].vpdPdg[0][i],
3355 eepromImage->calFreqPier5G[index+1],
3356 eepromImage->calPierData5G[0][index+1].vpdPdg[0][i]
3357 );
3358 chain0pwrPdg1[i] = zfInterpolateFuncX(fbin,
3359 eepromImage->calFreqPier5G[index],
3360 eepromImage->calPierData5G[0][index].pwrPdg[1][i],
3361 eepromImage->calFreqPier5G[index+1],
3362 eepromImage->calPierData5G[0][index+1].pwrPdg[1][i]
3363 );
3364 chain0vpdPdg1[i] = zfInterpolateFuncX(fbin,
3365 eepromImage->calFreqPier5G[index],
3366 eepromImage->calPierData5G[0][index].vpdPdg[1][i],
3367 eepromImage->calFreqPier5G[index+1],
3368 eepromImage->calPierData5G[0][index+1].vpdPdg[1][i]
3369 );
3370
3371 chain2pwrPdg0[i] = zfInterpolateFuncX(fbin,
3372 eepromImage->calFreqPier5G[index],
3373 eepromImage->calPierData5G[1][index].pwrPdg[0][i],
3374 eepromImage->calFreqPier5G[index+1],
3375 eepromImage->calPierData5G[1][index+1].pwrPdg[0][i]
3376 );
3377 chain2vpdPdg0[i] = zfInterpolateFuncX(fbin,
3378 eepromImage->calFreqPier5G[index],
3379 eepromImage->calPierData5G[1][index].vpdPdg[0][i],
3380 eepromImage->calFreqPier5G[index+1],
3381 eepromImage->calPierData5G[1][index+1].vpdPdg[0][i]
3382 );
3383 chain2pwrPdg1[i] = zfInterpolateFuncX(fbin,
3384 eepromImage->calFreqPier5G[index],
3385 eepromImage->calPierData5G[1][index].pwrPdg[1][i],
3386 eepromImage->calFreqPier5G[index+1],
3387 eepromImage->calPierData5G[1][index+1].pwrPdg[1][i]
3388 );
3389 chain2vpdPdg1[i] = zfInterpolateFuncX(fbin,
3390 eepromImage->calFreqPier5G[index],
3391 eepromImage->calPierData5G[1][index].vpdPdg[1][i],
3392 eepromImage->calFreqPier5G[index+1],
3393 eepromImage->calPierData5G[1][index+1].vpdPdg[1][i]
3394 );
3395 }
3396
3397 }
3398
3399
3400 /* Chain 1 */
3401 /* Get pwr and vpd test points from frequency */
3402 for (i=0; i<5; i++)
3403 {
3404 pwr0[i] = chain0pwrPdg0[i]>>1;
3405 vpd0[i] = chain0vpdPdg0[i];
3406 pwr1[i] = chain0pwrPdg1[i]>>1;
3407 vpd1[i] = chain0vpdPdg1[i];
3408 }
3409 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3410 DbgPrint("Test Points\n");
3411 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3412 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3413 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3414 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3415 #endif
3416 /* Generate the vpd arrays */
3417 for (i=0; i<boundary1+1+6; i++)
3418 {
3419 vpd_chain1[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3420 }
3421 for (; i<powerTxMax+1+6+6; i++)
3422 {
3423 vpd_chain1[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3424 }
3425 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3426 DbgPrint("vpd_chain1\n");
3427 for (i=0; i<powerTxMax+1+6+6; i+=10)
3428 {
3429 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3430 vpd_chain1[i+0], vpd_chain1[i+1], vpd_chain1[i+2], vpd_chain1[i+3], vpd_chain1[i+4],
3431 vpd_chain1[i+5], vpd_chain1[i+6], vpd_chain1[i+7], vpd_chain1[i+8], vpd_chain1[i+9]);
3432 }
3433 #endif
3434 /* Write PHY regs 672-703 */
3435 for (i=0; i<128; i+=4)
3436 {
3437 u32_t regAddr = 0x9800 + (672 * 4);
3438 u32_t val;
3439
3440 val = ((u32_t)vpd_chain1[i+3]<<24) |
3441 ((u32_t)vpd_chain1[i+2]<<16) |
3442 ((u32_t)vpd_chain1[i+1]<<8) |
3443 ((u32_t)vpd_chain1[i]);
3444
3445 #ifndef ZM_OTUS_LINUX_PHASE_2
3446 reg_write(regAddr + i, val); /* CR672 */
3447 #endif
3448 }
3449
3450 /* Chain 2 */
3451 /* Get pwr and vpd test points from frequency */
3452 for (i=0; i<5; i++)
3453 {
3454 pwr0[i] = chain2pwrPdg0[i]>>1;
3455 vpd0[i] = chain2vpdPdg0[i];
3456 pwr1[i] = chain2pwrPdg1[i]>>1;
3457 vpd1[i] = chain2vpdPdg1[i];
3458 }
3459 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3460 DbgPrint("Test Points\n");
3461 DbgPrint("pwr0 : %d, %d, %d, %d ,%d\n", pwr0[0], pwr0[1], pwr0[2], pwr0[3], pwr0[4]);
3462 DbgPrint("vpd0 : %d, %d, %d, %d ,%d\n", vpd0[0], vpd0[1], vpd0[2], vpd0[3], vpd0[4]);
3463 DbgPrint("pwr1 : %d, %d, %d, %d ,%d\n", pwr1[0], pwr1[1], pwr1[2], pwr1[3], pwr1[4]);
3464 DbgPrint("vpd1 : %d, %d, %d, %d ,%d\n", vpd1[0], vpd1[1], vpd1[2], vpd1[3], vpd1[4]);
3465 #endif
3466 /* Generate the vpd arrays */
3467 for (i=0; i<boundary1+1+6; i++)
3468 {
3469 vpd_chain3[i] = zfGetInterpolatedValue(i, &pwr0[0], &vpd0[0]);
3470 }
3471 for (; i<powerTxMax+1+6+6; i++)
3472 {
3473 vpd_chain3[i] = zfGetInterpolatedValue(i-6-6, &pwr1[0], &vpd1[0]);
3474 }
3475 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3476 DbgPrint("vpd_chain3\n");
3477 for (i=0; i<powerTxMax+1+6+6; i+=10)
3478 {
3479 DbgPrint("%d, %d, %d, %d ,%d, %d, %d, %d, %d, %d\n",
3480 vpd_chain3[i+0], vpd_chain3[i+1], vpd_chain3[i+2], vpd_chain3[i+3], vpd_chain3[i+4],
3481 vpd_chain3[i+5], vpd_chain3[i+6], vpd_chain3[i+7], vpd_chain3[i+8], vpd_chain3[i+9]);
3482 }
3483 #endif
3484
3485 /* Write PHY regs 672-703 + 0x1000 */
3486 for (i=0; i<128; i+=4)
3487 {
3488 u32_t regAddr = 0x9800 + (672 * 4) + 0x1000;
3489 u32_t val;
3490
3491 val = ((u32_t)vpd_chain3[i+3]<<24) |
3492 ((u32_t)vpd_chain3[i+2]<<16) |
3493 ((u32_t)vpd_chain3[i+1]<<8) |
3494 ((u32_t)vpd_chain3[i]);
3495
3496 #ifndef ZM_OTUS_LINUX_PHASE_2
3497 reg_write(regAddr + i, val); /* CR672 */
3498 #endif
3499 }
3500
3501 zfFlushDelayWrite(dev);
3502
3503 /* 3. Generate target power table */
3504 if (frequency < 3000)
3505 {
3506 for (i=0; i<3; i++)
3507 {
3508 if (eepromImage->calTargetPowerCck[i].bChannel != 0xff)
3509 {
3510 fbinArray[i] = eepromImage->calTargetPowerCck[i].bChannel;
3511 }
3512 else
3513 {
3514 break;
3515 }
3516
3517 }
3518 index = zfFindFreqIndex(fbin, fbinArray, i);
3519 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3520 DbgPrint("CCK index=%d\n", index);
3521 #endif
3522 for (i=0; i<4; i++)
3523 {
3524 hpPriv->tPow2xCck[i] = zfInterpolateFuncX(fbin,
3525 eepromImage->calTargetPowerCck[index].bChannel,
3526 eepromImage->calTargetPowerCck[index].tPow2x[i],
3527 eepromImage->calTargetPowerCck[index+1].bChannel,
3528 eepromImage->calTargetPowerCck[index+1].tPow2x[i]
3529 );
3530 }
3531
3532 for (i=0; i<4; i++)
3533 {
3534 if (eepromImage->calTargetPower2G[i].bChannel != 0xff)
3535 {
3536 fbinArray[i] = eepromImage->calTargetPower2G[i].bChannel;
3537 }
3538 else
3539 {
3540 break;
3541 }
3542
3543 }
3544 index = zfFindFreqIndex(fbin, fbinArray, i);
3545 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3546 DbgPrint("2G index=%d\n", index);
3547 #endif
3548 for (i=0; i<4; i++)
3549 {
3550 hpPriv->tPow2x2g[i] = zfInterpolateFuncX(fbin,
3551 eepromImage->calTargetPower2G[index].bChannel,
3552 eepromImage->calTargetPower2G[index].tPow2x[i],
3553 eepromImage->calTargetPower2G[index+1].bChannel,
3554 eepromImage->calTargetPower2G[index+1].tPow2x[i]
3555 );
3556 }
3557
3558 for (i=0; i<4; i++)
3559 {
3560 if (eepromImage->calTargetPower2GHT20[i].bChannel != 0xff)
3561 {
3562 fbinArray[i] = eepromImage->calTargetPower2GHT20[i].bChannel;
3563 }
3564 else
3565 {
3566 break;
3567 }
3568
3569 }
3570 index = zfFindFreqIndex(fbin, fbinArray, i);
3571 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3572 DbgPrint("2G HT20 index=%d\n", index);
3573 #endif
3574 for (i=0; i<8; i++)
3575 {
3576 hpPriv->tPow2x2gHt20[i] = zfInterpolateFuncX(fbin,
3577 eepromImage->calTargetPower2GHT20[index].bChannel,
3578 eepromImage->calTargetPower2GHT20[index].tPow2x[i],
3579 eepromImage->calTargetPower2GHT20[index+1].bChannel,
3580 eepromImage->calTargetPower2GHT20[index+1].tPow2x[i]
3581 );
3582 }
3583
3584 for (i=0; i<4; i++)
3585 {
3586 if (eepromImage->calTargetPower2GHT40[i].bChannel != 0xff)
3587 {
3588 fbinArray[i] = eepromImage->calTargetPower2GHT40[i].bChannel;
3589 }
3590 else
3591 {
3592 break;
3593 }
3594
3595 }
3596 index = zfFindFreqIndex( (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3597 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3598 DbgPrint("2G HT40 index=%d\n", index);
3599 #endif
3600 for (i=0; i<8; i++)
3601 {
3602 hpPriv->tPow2x2gHt40[i] = zfInterpolateFuncX(
3603 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3604 eepromImage->calTargetPower2GHT40[index].bChannel,
3605 eepromImage->calTargetPower2GHT40[index].tPow2x[i],
3606 eepromImage->calTargetPower2GHT40[index+1].bChannel,
3607 eepromImage->calTargetPower2GHT40[index+1].tPow2x[i]
3608 );
3609 }
3610
3611 zfPrintTargetPower2G(hpPriv->tPow2xCck,
3612 hpPriv->tPow2x2g,
3613 hpPriv->tPow2x2gHt20,
3614 hpPriv->tPow2x2gHt40);
3615 }
3616 else
3617 {
3618 /* 5G */
3619 for (i=0; i<8; i++)
3620 {
3621 if (eepromImage->calTargetPower5G[i].bChannel != 0xff)
3622 {
3623 fbinArray[i] = eepromImage->calTargetPower5G[i].bChannel;
3624 }
3625 else
3626 {
3627 break;
3628 }
3629
3630 }
3631 index = zfFindFreqIndex(fbin, fbinArray, i);
3632 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3633 DbgPrint("5G index=%d\n", index);
3634 #endif
3635 for (i=0; i<4; i++)
3636 {
3637 hpPriv->tPow2x5g[i] = zfInterpolateFuncX(fbin,
3638 eepromImage->calTargetPower5G[index].bChannel,
3639 eepromImage->calTargetPower5G[index].tPow2x[i],
3640 eepromImage->calTargetPower5G[index+1].bChannel,
3641 eepromImage->calTargetPower5G[index+1].tPow2x[i]
3642 );
3643 }
3644
3645 for (i=0; i<8; i++)
3646 {
3647 if (eepromImage->calTargetPower5GHT20[i].bChannel != 0xff)
3648 {
3649 fbinArray[i] = eepromImage->calTargetPower5GHT20[i].bChannel;
3650 }
3651 else
3652 {
3653 break;
3654 }
3655
3656 }
3657 index = zfFindFreqIndex(fbin, fbinArray, i);
3658 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3659 DbgPrint("5G HT20 index=%d\n", index);
3660 #endif
3661 for (i=0; i<8; i++)
3662 {
3663 hpPriv->tPow2x5gHt20[i] = zfInterpolateFuncX(fbin,
3664 eepromImage->calTargetPower5GHT20[index].bChannel,
3665 eepromImage->calTargetPower5GHT20[index].tPow2x[i],
3666 eepromImage->calTargetPower5GHT20[index+1].bChannel,
3667 eepromImage->calTargetPower5GHT20[index+1].tPow2x[i]
3668 );
3669 }
3670
3671 for (i=0; i<8; i++)
3672 {
3673 if (eepromImage->calTargetPower5GHT40[i].bChannel != 0xff)
3674 {
3675 fbinArray[i] = eepromImage->calTargetPower5GHT40[i].bChannel;
3676 }
3677 else
3678 {
3679 break;
3680 }
3681
3682 }
3683 index = zfFindFreqIndex((u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset), fbinArray, i);
3684 #ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
3685 DbgPrint("5G HT40 index=%d\n", index);
3686 #endif
3687 for (i=0; i<8; i++)
3688 {
3689 hpPriv->tPow2x5gHt40[i] = zfInterpolateFuncX(
3690 (u8_t)zfAdjustHT40FreqOffset(dev, fbin, bw40, extOffset),
3691 eepromImage->calTargetPower5GHT40[index].bChannel,
3692 eepromImage->calTargetPower5GHT40[index].tPow2x[i],
3693 eepromImage->calTargetPower5GHT40[index+1].bChannel,
3694 eepromImage->calTargetPower5GHT40[index+1].tPow2x[i]
3695 );
3696 }
3697
3698 zfPrintTargetPower5G(
3699 hpPriv->tPow2x5g,
3700 hpPriv->tPow2x5gHt20,
3701 hpPriv->tPow2x5gHt40);
3702 }
3703
3704
3705
3706 /* 4. CTL */
3707 /*
3708 * 4.1 Get the bandedges tx power by frequency
3709 * 2.4G we get ctlEdgesMaxPowerCCK
3710 * ctlEdgesMaxPower2G
3711 * ctlEdgesMaxPower2GHT20
3712 * ctlEdgesMaxPower2GHT40
3713 * 5G we get ctlEdgesMaxPower5G
3714 * ctlEdgesMaxPower5GHT20
3715 * ctlEdgesMaxPower5GHT40
3716 * 4.2 Update (3.) target power table by 4.1
3717 * 4.3 Tx power offset for ART - NDIS/MDK
3718 * 4.4 Write MAC reg 0x694 for ACK's TPC
3719 *
3720 */
3721
3722 //zfDumpEepBandEdges(eepromImage);
3723
3724 /* get the cfg from Eeprom: regionCode => RegulatoryDomain : 0x10-FFC 0x30-eu 0x40-jap */
3725 desired_CtlIndex = zfHpGetRegulatoryDomain(dev);
3726 if ((desired_CtlIndex == 0x30) || (desired_CtlIndex == 0x40) || (desired_CtlIndex == 0x0))
3727 {
3728 /* skip CTL and heavy clip */
3729 hpPriv->enableBBHeavyClip = 0;
3730 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3731 zm_dbg(("RegulatoryDomain = 0, skip CTL and heavy clip\n"));
3732 #endif
3733 }
3734 else
3735 {
3736 hpPriv->enableBBHeavyClip = 1;
3737
3738 if (desired_CtlIndex == 0xff)
3739 {
3740 /* desired index not found */
3741 desired_CtlIndex = 0x10;
3742 }
3743
3744 /* first part : 2.4G */
3745 if (frequency <= ZM_CH_G_14)
3746 {
3747 /* 2.4G - CTL_11B */
3748 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11B);
3749 if(ctl_i<AR5416_NUM_CTLS)
3750 {
3751 ctlEdgesMaxPowerCCK = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3752 }
3753 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3754 zm_dbg(("CTL_11B ctl_i = %d\n", ctl_i));
3755 #endif
3756
3757 /* 2.4G - CTL_11G */
3758 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3759 if(ctl_i<AR5416_NUM_CTLS)
3760 {
3761 ctlEdgesMaxPower2G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3762 }
3763 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3764 zm_dbg(("CTL_11G ctl_i = %d\n", ctl_i));
3765 #endif
3766
3767 /* 2.4G - CTL_2GHT20 */
3768 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT20);
3769 if(ctl_i<AR5416_NUM_CTLS)
3770 {
3771 ctlEdgesMaxPower2GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3772 }
3773 else
3774 {
3775 /* workaround for no data in Eeprom, replace by normal 2G */
3776 ctlEdgesMaxPower2GHT20 = ctlEdgesMaxPower2G;
3777 }
3778 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3779 zm_dbg(("CTL_2GHT20 ctl_i = %d\n", ctl_i));
3780 #endif
3781
3782 /* 2.4G - CTL_2GHT40 */
3783 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_2GHT40);
3784 if(ctl_i<AR5416_NUM_CTLS)
3785 {
3786 ctlEdgesMaxPower2GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3787 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3788 }
3789 else
3790 {
3791 /* workaround for no data in Eeprom, replace by normal 2G */
3792 ctlEdgesMaxPower2GHT40 = ctlEdgesMaxPower2G;
3793 }
3794 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3795 zm_dbg(("CTL_2GHT40 ctl_i = %d\n", ctl_i));
3796 #endif
3797
3798
3799 /* 7a17 : */
3800 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3801 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3802 {
3803 if (wd->regulationTable.allowChannel[i].channel == frequency)
3804 {
3805 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3806 {
3807 zm_debug_msg1("frequency use DFS -- ", frequency);
3808 ctlEdgesMaxPowerCCK = zm_min(ctlEdgesMaxPowerCCK, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3809 ctlEdgesMaxPower2G = zm_min(ctlEdgesMaxPower2G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3810 ctlEdgesMaxPower2GHT20 = zm_min(ctlEdgesMaxPower2GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3811 ctlEdgesMaxPower2GHT40 = zm_min(ctlEdgesMaxPower2GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3812 }
3813 break;
3814 }
3815 }
3816
3817 /* Apply ctl mode to correct target power set */
3818 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3819 zm_debug_msg1("ctlEdgesMaxPowerCCK = ", ctlEdgesMaxPowerCCK);
3820 zm_debug_msg1("ctlEdgesMaxPower2G = ", ctlEdgesMaxPower2G);
3821 zm_debug_msg1("ctlEdgesMaxPower2GHT20 = ", ctlEdgesMaxPower2GHT20);
3822 zm_debug_msg1("ctlEdgesMaxPower2GHT40 = ", ctlEdgesMaxPower2GHT40);
3823 #endif
3824 for (i=0; i<4; i++)
3825 {
3826 hpPriv->tPow2xCck[i] = zm_min(hpPriv->tPow2xCck[i], ctlEdgesMaxPowerCCK) + HALTX_POWER_OFFSET;
3827 }
3828 hpPriv->tPow2x2g24HeavyClipOffset = 0;
3829 if (hpPriv->enableBBHeavyClip)
3830 {
3831 ctlOffset = 2;
3832 }
3833 else
3834 {
3835 ctlOffset = 0;
3836 }
3837 for (i=0; i<4; i++)
3838 {
3839 if (((frequency == 2412) || (frequency == 2462)))
3840 {
3841 if (i != 0)
3842 {
3843 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G-ctlOffset) + HALTX_POWER_OFFSET;
3844 }
3845 else
3846 {
3847 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3848 if (hpPriv->tPow2x2g[i] > (ctlEdgesMaxPower2G-ctlOffset))
3849 {
3850 hpPriv->tPow2x2g24HeavyClipOffset = hpPriv->tPow2x2g[i] - (ctlEdgesMaxPower2G-ctlOffset);
3851 }
3852 }
3853 }
3854 else
3855 {
3856 hpPriv->tPow2x2g[i] = zm_min(hpPriv->tPow2x2g[i], ctlEdgesMaxPower2G) + HALTX_POWER_OFFSET;
3857 }
3858 }
3859 for (i=0; i<8; i++)
3860 {
3861 if (((frequency == 2412) || (frequency == 2462)) && (i>=3))
3862 {
3863 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20-ctlOffset) + HALTX_POWER_OFFSET;
3864 }
3865 else
3866 {
3867 hpPriv->tPow2x2gHt20[i] = zm_min(hpPriv->tPow2x2gHt20[i], ctlEdgesMaxPower2GHT20) + HALTX_POWER_OFFSET;
3868 }
3869 }
3870 for (i=0; i<8; i++)
3871 {
3872 if ((frequency == 2412) && (i>=3))
3873 {
3874 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-ctlOffset) + HALTX_POWER_OFFSET;
3875 }
3876 else if ((frequency == 2462) && (i>=3))
3877 {
3878 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40-(ctlOffset*2)) + HALTX_POWER_OFFSET;
3879 }
3880 else
3881 {
3882 hpPriv->tPow2x2gHt40[i] = zm_min(hpPriv->tPow2x2gHt40[i], ctlEdgesMaxPower2GHT40) + HALTX_POWER_OFFSET;
3883 }
3884 }
3885 }
3886 else
3887 {
3888 /* 5G - CTL_11A */
3889 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3890 if(ctl_i<AR5416_NUM_CTLS)
3891 {
3892 ctlEdgesMaxPower5G = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3893 }
3894 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3895 zm_dbg(("CTL_11A ctl_i = %d\n", ctl_i));
3896 #endif
3897
3898 /* 5G - CTL_5GHT20 */
3899 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT20);
3900 if(ctl_i<AR5416_NUM_CTLS)
3901 {
3902 ctlEdgesMaxPower5GHT20 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1], frequency);
3903 }
3904 else
3905 {
3906 /* workaround for no data in Eeprom, replace by normal 5G */
3907 ctlEdgesMaxPower5GHT20 = ctlEdgesMaxPower5G;
3908 }
3909 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3910 zm_dbg(("CTL_5GHT20 ctl_i = %d\n", ctl_i));
3911 #endif
3912
3913 /* 5G - CTL_5GHT40 */
3914 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_5GHT40);
3915 if(ctl_i<AR5416_NUM_CTLS)
3916 {
3917 ctlEdgesMaxPower5GHT40 = zfGetMaxEdgePower(dev, eepromImage->ctlData[ctl_i].ctlEdges[1],
3918 zfAdjustHT40FreqOffset(dev, frequency, bw40, extOffset));
3919 }
3920 else
3921 {
3922 /* workaround for no data in Eeprom, replace by normal 5G */
3923 ctlEdgesMaxPower5GHT40 = ctlEdgesMaxPower5G;
3924 }
3925 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3926 zm_dbg(("CTL_5GHT40 ctl_i = %d\n", ctl_i));
3927 #endif
3928
3929 /* 7a17 : */
3930 /* Max power (dBm) for channel range when using DFS define by madwifi*/
3931 for (i=0; i<wd->regulationTable.allowChannelCnt; i++)
3932 {
3933 if (wd->regulationTable.allowChannel[i].channel == frequency)
3934 {
3935 if (zfHpIsDfsChannel(dev, (u16_t)frequency))
3936 {
3937 zm_debug_msg1("frequency use DFS -- ", frequency);
3938 ctlEdgesMaxPower5G = zm_min(ctlEdgesMaxPower5G, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3939 ctlEdgesMaxPower5GHT20 = zm_min(ctlEdgesMaxPower5GHT20, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3940 ctlEdgesMaxPower5GHT40 = zm_min(ctlEdgesMaxPower5GHT40, wd->regulationTable.allowChannel[i].maxRegTxPower*2);
3941 }
3942 break;
3943 }
3944 }
3945
3946
3947 /* Apply ctl mode to correct target power set */
3948 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3949 zm_debug_msg1("ctlEdgesMaxPower5G = ", ctlEdgesMaxPower5G);
3950 zm_debug_msg1("ctlEdgesMaxPower5GHT20 = ", ctlEdgesMaxPower5GHT20);
3951 zm_debug_msg1("ctlEdgesMaxPower5GHT40 = ", ctlEdgesMaxPower5GHT40);
3952 #endif
3953 for (i=0; i<4; i++)
3954 {
3955 hpPriv->tPow2x5g[i] = zm_min(hpPriv->tPow2x5g[i], ctlEdgesMaxPower5G) + HALTX_POWER_OFFSET;
3956 }
3957 for (i=0; i<8; i++)
3958 {
3959 hpPriv->tPow2x5gHt20[i] = zm_min(hpPriv->tPow2x5gHt20[i], ctlEdgesMaxPower5GHT20) + HALTX_POWER_OFFSET;
3960 }
3961 for (i=0; i<8; i++)
3962 {
3963 hpPriv->tPow2x5gHt40[i] = zm_min(hpPriv->tPow2x5gHt40[i], ctlEdgesMaxPower5GHT40) + HALTX_POWER_OFFSET;
3964 }
3965
3966 }/* end of bandedges of 5G */
3967 }/* end of if ((desired_CtlIndex = zfHpGetRegulatoryDomain(dev)) == 0) */
3968
3969 /* workaround */
3970 /* 5. BB heavy clip */
3971 /* only 2.4G do heavy clip */
3972 if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip && (frequency <= ZM_CH_G_14))
3973 {
3974 if (frequency <= ZM_CH_G_14)
3975 {
3976 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11G);
3977 }
3978 else
3979 {
3980 ctl_i = zfFindCtlEdgesIndex(dev, desired_CtlIndex|CTL_11A);
3981 }
3982
3983 hpPriv->setValueHeavyClip = zfHpCheckDoHeavyClip(dev, frequency, eepromImage->ctlData[ctl_i].ctlEdges[1], bw40);
3984
3985 if (hpPriv->setValueHeavyClip)
3986 {
3987 hpPriv->doBBHeavyClip = 1;
3988 }
3989 else
3990 {
3991 hpPriv->doBBHeavyClip = 0;
3992 }
3993 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
3994 zm_dbg(("zfHpCheckDoHeavyClip ret = %02x, doBBHeavyClip = %d\n",
3995 hpPriv->setValueHeavyClip, hpPriv->doBBHeavyClip));
3996 #endif
3997
3998 if (hpPriv->doBBHeavyClip)
3999 {
4000 if (hpPriv->setValueHeavyClip & 0xf0)
4001 {
4002 hpPriv->tPow2x2gHt40[0] -= 1;
4003 hpPriv->tPow2x2gHt40[1] -= 1;
4004 hpPriv->tPow2x2gHt40[2] -= 1;
4005 }
4006
4007 if (hpPriv->setValueHeavyClip & 0xf)
4008 {
4009 hpPriv->tPow2x2gHt20[0] += 1;
4010 hpPriv->tPow2x2gHt20[1] += 1;
4011 hpPriv->tPow2x2gHt20[2] += 1;
4012 }
4013 }
4014 }
4015 else
4016 {
4017 hpPriv->doBBHeavyClip = 0;
4018 hpPriv->setValueHeavyClip = 0;
4019 }
4020
4021 /* Final : write MAC register for some ctrl frame Tx power */
4022 /* first part : 2.4G */
4023 if (frequency <= ZM_CH_G_14)
4024 {
4025 /* Write MAC reg 0x694 for ACK's TPC */
4026 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4027 /* Always use two stream for low legacy rate */
4028 #if 0
4029 //if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4030 //{
4031 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x1<<26));
4032 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x1<<11) |
4033 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x1<<27) );
4034 //}
4035 #endif
4036 #if 1
4037 //else
4038 {
4039 #ifndef ZM_OTUS_LINUX_PHASE_2
4040 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x2g[0]&0x3f) << 20) | (0x5<<26));
4041 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x2g[0]&0x3f) << 5 ) | (0x5<<11) |
4042 ((hpPriv->tPow2x2g[0]&0x3f) << 21) | (0x5<<27) );
4043 #endif
4044 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4045 }
4046 #endif
4047 zfFlushDelayWrite(dev);
4048
4049 zfPrintTargetPower2G(hpPriv->tPow2xCck,
4050 hpPriv->tPow2x2g,
4051 hpPriv->tPow2x2gHt20,
4052 hpPriv->tPow2x2gHt40);
4053 }
4054 else
4055 {
4056 /* Write MAC reg 0x694 for ACK's TPC */
4057 /* Write MAC reg 0xbb4 RTS and SF-CTS frame power control */
4058 /* Always use two stream for low legacy rate */
4059 if (hpPriv->halCapability & ZM_HP_CAP_11N_ONE_TX_STREAM)
4060 {
4061 #ifndef ZM_OTUS_LINUX_PHASE_2
4062 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x1<<26));
4063 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x1<<11) |
4064 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x1<<27) );
4065 #endif
4066 }
4067 else
4068 {
4069 #ifndef ZM_OTUS_LINUX_PHASE_2
4070 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->tPow2x5g[0]&0x3f) << 20) | (0x5<<26));
4071 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->tPow2x5g[0]&0x3f) << 5 ) | (0x5<<11) |
4072 ((hpPriv->tPow2x5g[0]&0x3f) << 21) | (0x5<<27) );
4073 #endif
4074 hpPriv->currentAckRtsTpc = hpPriv->tPow2x2g[0];
4075 }
4076
4077
4078 zfFlushDelayWrite(dev);
4079
4080 zfPrintTargetPower5G(
4081 hpPriv->tPow2x5g,
4082 hpPriv->tPow2x5gHt20,
4083 hpPriv->tPow2x5gHt40);
4084 }/* end of bandedges of 5G */
4085
4086 }
4087
4088 void zfDumpEepBandEdges(struct ar5416Eeprom* eepromImage)
4089 {
4090 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4091 u8_t i, j, k;
4092
4093 #if 0
4094 zm_dbg(("\n === BandEdges index dump ==== \n"));
4095
4096 for (i = 0; i < AR5416_NUM_CTLS; i++)
4097 {
4098 zm_dbg(("%02x ", eepromImage->ctlIndex[i]));
4099 }
4100
4101 zm_dbg(("\n === BandEdges data dump ==== \n"));
4102
4103 for (i = 0; i < AR5416_NUM_CTLS; i++)
4104 {
4105 for (j = 0; j < 2; j++)
4106 {
4107 for(k = 0; k < AR5416_NUM_BAND_EDGES; k++)
4108 {
4109 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j][k]);
4110 zm_dbg(("(%02x %02x)", pdata[0], pdata[1]));
4111 }
4112 zm_dbg(("\n"));
4113 }
4114 }
4115 #else
4116 zm_dbg(("\n === BandEdges index dump ==== \n"));
4117 for (i = 0; i < 24; i+=8)
4118 {
4119 zm_dbg(("%02x %02x %02x %02x %02x %02x %02x %02x",
4120 eepromImage->ctlIndex[i+0], eepromImage->ctlIndex[i+1], eepromImage->ctlIndex[i+2], eepromImage->ctlIndex[i+3],
4121 eepromImage->ctlIndex[i+4], eepromImage->ctlIndex[i+5], eepromImage->ctlIndex[i+6], eepromImage->ctlIndex[i+7]
4122 ));
4123 }
4124
4125 zm_dbg(("\n === BandEdges data dump ==== \n"));
4126
4127 for (i = 0; i < AR5416_NUM_CTLS; i++)
4128 {
4129 for (j = 0; j < 2; j++)
4130 {
4131 u8_t *pdata = (u8_t*)&(eepromImage->ctlData[i].ctlEdges[j]);
4132 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4133 pdata[0], pdata[1], pdata[2], pdata[3],
4134 pdata[4], pdata[5], pdata[6], pdata[7]
4135 ));
4136 zm_dbg(("(%03d %02x) (%03d %02x) (%03d %02x) (%03d %02x) \n",
4137 pdata[8], pdata[9], pdata[10], pdata[11],
4138 pdata[12], pdata[13], pdata[14], pdata[15]
4139 ));
4140 }
4141 }
4142 #endif
4143 #endif
4144 }
4145
4146 void zfPrintTargetPower2G(u8_t* tPow2xCck, u8_t* tPow2x2g, u8_t* tPow2x2gHt20, u8_t* tPow2x2gHt40)
4147 {
4148 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4149 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4150 DbgPrint("targetPwr CCK : %d, %d, %d, %d\n",
4151 tPow2xCck[0],
4152 tPow2xCck[1],
4153 tPow2xCck[2],
4154 tPow2xCck[3]
4155 );
4156 DbgPrint("targetPwr 2G : %d, %d, %d, %d\n",
4157 tPow2x2g[0],
4158 tPow2x2g[1],
4159 tPow2x2g[2],
4160 tPow2x2g[3]
4161 );
4162 DbgPrint("targetPwr 2GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4163 tPow2x2gHt20[0],
4164 tPow2x2gHt20[1],
4165 tPow2x2gHt20[2],
4166 tPow2x2gHt20[3],
4167 tPow2x2gHt20[4],
4168 tPow2x2gHt20[5],
4169 tPow2x2gHt20[6],
4170 tPow2x2gHt20[7]
4171 );
4172 DbgPrint("targetPwr 2GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4173 tPow2x2gHt40[0],
4174 tPow2x2gHt40[1],
4175 tPow2x2gHt40[2],
4176 tPow2x2gHt40[3],
4177 tPow2x2gHt40[4],
4178 tPow2x2gHt40[5],
4179 tPow2x2gHt40[6],
4180 tPow2x2gHt40[7]
4181 );
4182 #endif
4183 return;
4184 }
4185
4186 void zfPrintTargetPower5G(u8_t* tPow2x5g, u8_t* tPow2x5gHt20, u8_t* tPow2x5gHt40)
4187 {
4188 //#ifdef ZM_ENABLE_TPC_WINDOWS_DEBUG
4189 #ifdef ZM_ENABLE_BANDEDGES_WINDOWS_DEBUG
4190 DbgPrint("targetPwr 5G : %d, %d, %d, %d\n",
4191 tPow2x5g[0],
4192 tPow2x5g[1],
4193 tPow2x5g[2],
4194 tPow2x5g[3]
4195 );
4196 DbgPrint("targetPwr 5GHT20 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4197 tPow2x5gHt20[0],
4198 tPow2x5gHt20[1],
4199 tPow2x5gHt20[2],
4200 tPow2x5gHt20[3],
4201 tPow2x5gHt20[4],
4202 tPow2x5gHt20[5],
4203 tPow2x5gHt20[6],
4204 tPow2x5gHt20[7]
4205 );
4206 DbgPrint("targetPwr 5GHT40 : %d, %d, %d, %d, %d, %d, %d, %d\n",
4207 tPow2x5gHt40[0],
4208 tPow2x5gHt40[1],
4209 tPow2x5gHt40[2],
4210 tPow2x5gHt40[3],
4211 tPow2x5gHt40[4],
4212 tPow2x5gHt40[5],
4213 tPow2x5gHt40[6],
4214 tPow2x5gHt40[7]
4215 );
4216 #endif
4217 return;
4218 }
4219
4220 void zfHpPowerSaveSetMode(zdev_t* dev, u8_t staMode, u8_t psMode, u16_t bcnInterval)
4221 {
4222 if ( staMode == 0 )
4223 {
4224 if ( psMode == 0 )
4225 {
4226 // Turn off pre-TBTT interrupt
4227 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, 0);
4228 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, 0);
4229 zfFlushDelayWrite(dev);
4230 }
4231 else
4232 {
4233 // Turn on pre-TBTT interrupt
4234 zfDelayWriteInternalReg(dev, ZM_MAC_REG_PRETBTT, (bcnInterval-6)<<16);
4235 zfDelayWriteInternalReg(dev, ZM_MAC_REG_BCN_PERIOD, bcnInterval);
4236 zfFlushDelayWrite(dev);
4237 }
4238 }
4239 }
4240
4241 void zfHpPowerSaveSetState(zdev_t* dev, u8_t psState)
4242 {
4243 struct zsHpPriv* hpPriv;
4244
4245 zmw_get_wlan_dev(dev);
4246 hpPriv = wd->hpPrivate;
4247
4248 //DbgPrint("INTO zfHpPowerSaveSetState");
4249
4250 if ( psState == 0 ) //power up
4251 {
4252 //DbgPrint("zfHpPowerSaveSetState Wake up from PS\n");
4253 reg_write(0x982C, 0x0000a000); //wake up ADDAC
4254 reg_write(0x9808, 0x0); //enable all agc gain and offset updates to a2
4255 //# bank 3
4256 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4257 {
4258 /* 11g */
4259 //reg_write (0x98f0, 0x01c00018);
4260 reg_write (0x98f0, 0x01c20098);//syn_on+RX_ON
4261 }
4262 else
4263 {
4264 /* 11a */
4265 //reg_write (0x98f0, 0x01400018);
4266 reg_write (0x98f0, 0x01420098);//syn_on+RX_ON
4267 }
4268
4269 ////#bank 5
4270 //reg_write(0x98b0, 0x00000013);
4271 //reg_write(0x98e4, 0x00000002);
4272
4273
4274 zfFlushDelayWrite(dev);
4275 }
4276 else //power down
4277 {
4278 //DbgPrint("zfHpPowerSaveSetState Go to PS\n");
4279 //reg_write(0x982C, 0xa000a000);
4280 reg_write(0x9808, 0x8000000); //disable all agc gain and offset updates to a2
4281 reg_write(0x982C, 0xa000a000); //power down ADDAC
4282 //# bank 3
4283 if (((struct zsHpPriv*)wd->hpPrivate)->hwFrequency <= ZM_CH_G_14)
4284 {
4285 /* 11g */
4286 reg_write (0x98f0, 0x00c00018);//syn_off+RX_off
4287 }
4288 else
4289 {
4290 /* 11a */
4291 reg_write (0x98f0, 0x00400018);//syn_off+RX_off
4292 }
4293
4294 ////#bank 5
4295 //reg_write(0x98b0, 0x000e0013);
4296 //reg_write(0x98e4, 0x00018002);
4297
4298
4299 zfFlushDelayWrite(dev);
4300 }
4301 }
4302
4303 void zfHpSetAggPktNum(zdev_t* dev, u32_t num)
4304 {
4305 struct zsHpPriv* hpPriv;
4306
4307 zmw_get_wlan_dev(dev);
4308 hpPriv = wd->hpPrivate;
4309
4310 num = (num << 16) | (0xa);
4311
4312 hpPriv->aggPktNum = num;
4313
4314 //aggregation number will be update in HAL heart beat
4315 //zfDelayWriteInternalReg(dev, 0x1c3b9c, num);
4316 //zfFlushDelayWrite(dev);
4317 }
4318
4319 void zfHpSetMPDUDensity(zdev_t* dev, u8_t density)
4320 {
4321 u32_t value;
4322
4323 if (density > ZM_MPDU_DENSITY_8US)
4324 {
4325 return;
4326 }
4327
4328 /* Default value in this register */
4329 value = 0x140A00 | density;
4330
4331 zfDelayWriteInternalReg(dev, 0x1c3ba0, value);
4332 zfFlushDelayWrite(dev);
4333 return;
4334 }
4335
4336 void zfHpSetSlotTime(zdev_t* dev, u8_t type)
4337 {
4338 struct zsHpPriv* hpPriv;
4339
4340 zmw_get_wlan_dev(dev);
4341 hpPriv = wd->hpPrivate;
4342
4343 if (type == 0)
4344 {
4345 //normal slot = 20us
4346 hpPriv->slotType = 0;
4347 }
4348 else //if (type == 1)
4349 {
4350 //short slot = 9us
4351 hpPriv->slotType = 1;
4352 }
4353
4354 return;
4355 }
4356
4357 void zfHpSetSlotTimeRegister(zdev_t* dev, u8_t type)
4358 {
4359 if(type == 0)
4360 {
4361 //normal slot = 20us
4362 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 20<<10);
4363 }
4364 else
4365 {
4366 //short slot = 9us
4367 zfDelayWriteInternalReg(dev, ZM_MAC_REG_SLOT_TIME, 9<<10);
4368 }
4369 }
4370
4371 void zfHpSetRifs(zdev_t* dev, u8_t ht_enable, u8_t ht2040, u8_t g_mode)
4372 {
4373 zfDelayWriteInternalReg(dev, 0x1c6388, 0x0c000000);
4374
4375 zfDelayWriteInternalReg(dev, 0x1c59ec, 0x0cc80caa);
4376
4377 if (ht_enable)
4378 {
4379 if (ht2040)
4380 {
4381 zfDelayWriteInternalReg(dev, 0x1c5918, 40);
4382 }
4383 else
4384 {
4385 zfDelayWriteInternalReg(dev, 0x1c5918, 20);
4386 }
4387 }
4388
4389 if (g_mode)
4390 {
4391 zfDelayWriteInternalReg(dev, 0x1c5850, 0xec08b4e2);
4392 zfDelayWriteInternalReg(dev, 0x1c585c, 0x313a5d5e);
4393 }
4394 else
4395 {
4396 zfDelayWriteInternalReg(dev, 0x1c5850, 0xede8b4e0);
4397 zfDelayWriteInternalReg(dev, 0x1c585c, 0x3139605e);
4398 }
4399
4400 zfFlushDelayWrite(dev);
4401 return;
4402 }
4403
4404 void zfHpBeginSiteSurvey(zdev_t* dev, u8_t status)
4405 {
4406 struct zsHpPriv* hpPriv;
4407
4408 zmw_get_wlan_dev(dev);
4409 hpPriv=wd->hpPrivate;
4410
4411 if ( status == 1 )
4412 { // Connected
4413 hpPriv->isSiteSurvey = 1;
4414 }
4415 else
4416 { // Not connected
4417 hpPriv->isSiteSurvey = 0;
4418 }
4419
4420 /* reset workaround state to default */
4421 // if (hpPriv->rxStrongRSSI == 1)
4422 {
4423 hpPriv->rxStrongRSSI = 0;
4424 if ((hpPriv->eepromImage[0x100+0x110*2/4]&0xff) == 0x80) //FEM TYPE
4425 {
4426 if (hpPriv->hwFrequency <= ZM_CH_G_14)
4427 {
4428 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b49);
4429 }
4430 else
4431 {
4432 zfDelayWriteInternalReg(dev, 0x1c8960, 0x0900);
4433 }
4434 }
4435 else
4436 {
4437 zfDelayWriteInternalReg(dev, 0x1c8960, 0x9b40);
4438 }
4439 zfFlushDelayWrite(dev);
4440 }
4441 // if (hpPriv->strongRSSI == 1)
4442 {
4443 hpPriv->strongRSSI = 0;
4444 zfDelayWriteInternalReg(dev, 0x1c3694, ((hpPriv->currentAckRtsTpc&0x3f) << 20) | (0x5<<26));
4445 zfDelayWriteInternalReg(dev, 0x1c3bb4, ((hpPriv->currentAckRtsTpc&0x3f) << 5 ) | (0x5<<11) |
4446 ((hpPriv->currentAckRtsTpc&0x3f) << 21) | (0x5<<27) );
4447 zfFlushDelayWrite(dev);
4448 }
4449 }
4450
4451 void zfHpFinishSiteSurvey(zdev_t* dev, u8_t status)
4452 {
4453 struct zsHpPriv* hpPriv;
4454
4455 zmw_get_wlan_dev(dev);
4456 hpPriv=wd->hpPrivate;
4457
4458 zmw_declare_for_critical_section();
4459
4460 zmw_enter_critical_section(dev);
4461 if ( status == 1 )
4462 {
4463 hpPriv->isSiteSurvey = 2;
4464 }
4465 else
4466 {
4467 hpPriv->isSiteSurvey = 0;
4468 }
4469 zmw_leave_critical_section(dev);
4470 }
4471
4472 u16_t zfFwRetry(zdev_t* dev, u8_t enable)
4473 {
4474 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
4475 u16_t ret = 0;
4476
4477 cmd[0] = 4 | (0x92 << 8);
4478 cmd[1] = (enable == 1) ? 0x01 : 0x00;
4479
4480 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
4481 return ret;
4482 }
4483
4484 u16_t zfHpEnableHwRetry(zdev_t* dev)
4485 {
4486 u16_t ret;
4487
4488 ret = zfFwRetry(dev, 0);
4489
4490 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x33333);
4491 zfFlushDelayWrite(dev);
4492
4493 return ret;
4494 }
4495
4496 u16_t zfHpDisableHwRetry(zdev_t* dev)
4497 {
4498 u16_t ret;
4499
4500 ret = zfFwRetry(dev, 1);
4501
4502 zfDelayWriteInternalReg(dev, 0x1c3b28, 0x00000);
4503 zfFlushDelayWrite(dev);
4504
4505 return ret;
4506 }
4507
4508 /* Download SPI Fw */
4509 #define ZM_FIRMWARE_WLAN 0
4510 #define ZM_FIRMWARE_SPI_FLASH 1
4511
4512
4513 u16_t zfHpFirmwareDownload(zdev_t* dev, u8_t fwType)
4514 {
4515 u16_t ret = ZM_SUCCESS;
4516
4517 if (fwType == ZM_FIRMWARE_WLAN)
4518 {
4519 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImage,
4520 (u32_t)zcFwImageSize, ZM_FIRMWARE_WLAN_ADDR);
4521 }
4522 else if (fwType == ZM_FIRMWARE_SPI_FLASH)
4523 {
4524 ret = zfFirmwareDownload(dev, (u32_t*)zcFwImageSPI,
4525 (u32_t)zcFwImageSPISize, ZM_FIRMWARE_SPI_ADDR);
4526 }
4527 else
4528 {
4529 zm_debug_msg1("Unknown firmware type = ", fwType);
4530 ret = ZM_ERR_FIRMWARE_WRONG_TYPE;
4531 }
4532
4533 return ret;
4534 }
4535
4536 /* Enable software decryption */
4537 void zfHpSWDecrypt(zdev_t* dev, u8_t enable)
4538 {
4539 u32_t value = 0x70;
4540
4541 /* Bit 4 for enable software decryption */
4542 if (enable == 1)
4543 {
4544 value = 0x78;
4545 }
4546
4547 zfDelayWriteInternalReg(dev, 0x1c3678, value);
4548 zfFlushDelayWrite(dev);
4549 }
4550
4551 /* Enable software encryption */
4552 void zfHpSWEncrypt(zdev_t* dev, u8_t enable)
4553 {
4554 /* Because encryption by software or hardware is judged by driver in Otus,
4555 we don't need to do anything in the HAL layer.
4556 */
4557 }
4558
4559 u32_t zfHpCapability(zdev_t* dev)
4560 {
4561 struct zsHpPriv* hpPriv;
4562
4563 zmw_get_wlan_dev(dev);
4564 hpPriv=wd->hpPrivate;
4565
4566 return hpPriv->halCapability;
4567 }
4568
4569 void zfHpSetRollCallTable(zdev_t* dev)
4570 {
4571 struct zsHpPriv* hpPriv;
4572
4573 zmw_get_wlan_dev(dev);
4574 hpPriv=wd->hpPrivate;
4575
4576 if (hpPriv->camRollCallTable != (u64_t) 0)
4577 {
4578 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_L, (u32_t)(hpPriv->camRollCallTable & 0xffffffff));
4579 zfDelayWriteInternalReg(dev, ZM_MAC_REG_ROLL_CALL_TBL_H, (u32_t)((hpPriv->camRollCallTable >> 32) & 0xffffffff));
4580 zfFlushDelayWrite(dev);
4581 }
4582 }
4583
4584 void zfHpSetTTSIFSTime(zdev_t* dev, u8_t sifs_time)
4585 {
4586 u32_t reg_value = 0;
4587 zmw_get_wlan_dev(dev);
4588
4589 sifs_time &= 0x3f;
4590 reg_value = 0x14400b | (((u32_t)sifs_time)<<24);
4591
4592 zfDelayWriteInternalReg(dev, ZM_MAC_REG_EIFS_AND_SIFS, reg_value);
4593 zfFlushDelayWrite(dev);
4594 }
4595
4596 /* #3 Enable RIFS function if the RIFS pattern matched ! */
4597 void zfHpEnableRifs(zdev_t* dev, u8_t mode24g, u8_t modeHt, u8_t modeHt2040)
4598 {
4599
4600 /* # Enable Reset TDOMAIN
4601 * $rddata = &$phyreg_read(0x9800+(738<<2));
4602 * $wrdata = $rddata | (0x1 << 26) | (0x1 << 27);
4603 * &$phyreg_write(0x9800+(738<<2), $wrdata);
4604 */
4605 reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26) | (0x1 << 27));
4606 //reg_write (0x9800+(738<<2), 0x08000000 | (0x1 << 26));
4607
4608 /* # reg 123: heavy clip factor, xr / RIFS search parameters */
4609 reg_write (0x99ec, 0x0cc80caa);
4610
4611 /* # Reduce Search Start Delay for RIFS */
4612 if (modeHt == 1) /* ($HT_ENABLE == 1) */
4613 {
4614 if (modeHt2040 == 0x1) /* ($DYNAMIC_HT2040_EN == 0x1) */
4615 {
4616 reg_write(0x9800+(70<<2), 40);/*40*/
4617 }
4618 else
4619 {
4620 reg_write(0x9800+(70<<2), 20);
4621 if(mode24g == 0x0)
4622 {
4623 /* $rddata = &$phyreg_read(0x9800+(24<<2));#0x9860;0x1c5860
4624 *$wrdata = ($rddata & 0xffffffc7) | (0x4 << 3);
4625 * &$phyreg_write(0x9800+(24<<2), $wrdata);
4626 */
4627 reg_write(0x9800+(24<<2), (0x0004dd10 & 0xffffffc7) | (0x4 << 3));
4628 }
4629 }
4630 }
4631
4632 if (mode24g == 0x1)
4633 {
4634 reg_write(0x9850, 0xece8b4e4);/*org*/
4635 //reg_write(0x9850, 0xece8b4e2);
4636 reg_write(0x985c, 0x313a5d5e);
4637 }
4638 else
4639 {
4640 reg_write(0x9850, 0xede8b4e4);
4641 reg_write(0x985c, 0x3139605e);
4642 }
4643
4644 zfFlushDelayWrite(dev);
4645
4646 return;
4647 }
4648
4649 /* #4 Disable RIFS function if the RIFS timer is timeout ! */
4650 void zfHpDisableRifs(zdev_t* dev)
4651 {
4652 zmw_get_wlan_dev(dev);
4653
4654 /* Disable RIFS function is to store these HW register initial value while the device plug-in and
4655 re-write to these register if the RIFS function is disabled */
4656
4657 // reg : 9850
4658 reg_write(0x9850, ((struct zsHpPriv*)wd->hpPrivate)->initDesiredSigSize);
4659
4660 // reg : 985c
4661 reg_write(0x985c, ((struct zsHpPriv*)wd->hpPrivate)->initAGC);
4662
4663 // reg : 9860
4664 reg_write(0x9800+(24<<2), ((struct zsHpPriv*)wd->hpPrivate)->initAgcControl);
4665
4666 // reg : 9918
4667 reg_write(0x9800+(70<<2), ((struct zsHpPriv*)wd->hpPrivate)->initSearchStartDelay);
4668
4669 // reg : 991c
4670 reg_write (0x99ec, ((struct zsHpPriv*)wd->hpPrivate)->initRIFSSearchParams);
4671
4672 // reg : a388
4673 reg_write (0x9800+(738<<2), ((struct zsHpPriv*)wd->hpPrivate)->initFastChannelChangeControl);
4674
4675 zfFlushDelayWrite(dev);
4676
4677 return;
4678 }
Linux for Ginger Game Console