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First Support on Ginger and OMAP TI
[linux-ginger.git] / drivers / staging / otus / hal / hprw.c
blobd9fad47d5d59685a4a88ac6b2c48e4406bf27524
1 /*
2 * Copyright (c) 2007-2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16 #include "../80211core/cprecomp.h"
17 #include "hpani.h"
18 #include "hpusb.h"
19 #include "hpreg.h"
20 #include "../80211core/ratectrl.h"
21
22 extern void zfIdlCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen);
23
24 extern void zfCoreCwmBusy(zdev_t* dev, u16_t busy);
25 u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
26 u16_t zfFlushDelayWrite(zdev_t* dev);
27
28 //#define zm_hp_priv(x) struct zsHpPriv* hpPriv=zgWlanDev.hpPrivate;
29
30 void zfInitCmdQueue(zdev_t* dev)
31 {
32 struct zsHpPriv* hpPriv;
33
34 zmw_get_wlan_dev(dev);
35 hpPriv = (struct zsHpPriv*)(wd->hpPrivate);
36
37 zmw_declare_for_critical_section();
38
39 zmw_enter_critical_section(dev);
40 #ifdef ZM_XP_USB_MULTCMD
41 hpPriv->cmdTail = hpPriv->cmdHead = hpPriv->cmdSend = 0;
42 #else
43 hpPriv->cmdTail = hpPriv->cmdHead = 0;
44 #endif
45 hpPriv->cmdPending = 0;
46 hpPriv->cmd.delayWcmdCount = 0;
47 zmw_leave_critical_section(dev);
48 }
49
50 u16_t zfPutCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, u16_t src, u8_t* buf)
51 {
52 u16_t i;
53 struct zsHpPriv* hpPriv;
54
55 zmw_get_wlan_dev(dev);
56 hpPriv=wd->hpPrivate;
57
58 /* Make sure command length < ZM_MAX_CMD_SIZE */
59 zm_assert(cmdLen <= ZM_MAX_CMD_SIZE);
60 /* Make sure command queue not full */
61 //zm_assert(((hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1)) != hpPriv->cmdHead);
62 if (((hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1)) == hpPriv->cmdHead ) {
63 zm_debug_msg0("CMD queue full!!");
64 return 0;
65 }
66
67 hpPriv->cmdQ[hpPriv->cmdTail].cmdLen = cmdLen;
68 hpPriv->cmdQ[hpPriv->cmdTail].src = src;
69 hpPriv->cmdQ[hpPriv->cmdTail].buf = buf;
70 for (i=0; i<(cmdLen>>2); i++)
71 {
72 hpPriv->cmdQ[hpPriv->cmdTail].cmd[i] = cmd[i];
73 }
74
75 hpPriv->cmdTail = (hpPriv->cmdTail+1) & (ZM_CMD_QUEUE_SIZE-1);
76
77 return 0;
78 }
79
80 u16_t zfGetCmd(zdev_t* dev, u32_t* cmd, u16_t* cmdLen, u16_t* src, u8_t** buf)
81 {
82 u16_t i;
83 struct zsHpPriv* hpPriv;
84
85 zmw_get_wlan_dev(dev);
86 hpPriv=wd->hpPrivate;
87
88 if (hpPriv->cmdTail == hpPriv->cmdHead)
89 {
90 return 3;
91 }
92
93 *cmdLen = hpPriv->cmdQ[hpPriv->cmdHead].cmdLen;
94 *src = hpPriv->cmdQ[hpPriv->cmdHead].src;
95 *buf = hpPriv->cmdQ[hpPriv->cmdHead].buf;
96 for (i=0; i<((*cmdLen)>>2); i++)
97 {
98 cmd[i] = hpPriv->cmdQ[hpPriv->cmdHead].cmd[i];
99 }
100
101 hpPriv->cmdHead = (hpPriv->cmdHead+1) & (ZM_CMD_QUEUE_SIZE-1);
102
103 return 0;
104 }
105
106 #ifdef ZM_XP_USB_MULTCMD
107 void zfSendCmdEx(zdev_t* dev)
108 {
109 u32_t ncmd[ZM_MAX_CMD_SIZE/4];
110 u16_t ncmdLen = 0;
111 u16_t cmdFlag = 0;
112 u16_t i;
113 struct zsHpPriv* hpPriv;
114
115 zmw_get_wlan_dev(dev);
116 hpPriv=wd->hpPrivate;
117
118 zmw_declare_for_critical_section();
119
120 zmw_enter_critical_section(dev);
121
122 if (hpPriv->cmdPending == 0)
123 {
124 if (hpPriv->cmdTail != hpPriv->cmdSend)
125 {
126 cmdFlag = 1;
127 /* Get queueing command */
128 ncmdLen= hpPriv->cmdQ[hpPriv->cmdSend].cmdLen;
129 for (i=0; i<(ncmdLen>>2); i++)
130 {
131 ncmd[i] = hpPriv->cmdQ[hpPriv->cmdSend].cmd[i];
132 }
133 hpPriv->cmdSend = (hpPriv->cmdSend+1) & (ZM_CMD_QUEUE_SIZE-1);
134
135 hpPriv->cmdPending = 1;
136 }
137 }
138
139 zmw_leave_critical_section(dev);
140
141 if ((cmdFlag == 1))
142 {
143 zfIdlCmd(dev, ncmd, ncmdLen);
144 }
145 }
146
147 void zfiSendCmdComp(zdev_t* dev)
148 {
149 struct zsHpPriv* hpPriv;
150
151 zmw_get_wlan_dev(dev);
152 hpPriv=wd->hpPrivate;
153
154 zmw_declare_for_critical_section();
155
156 zmw_enter_critical_section(dev);
157 hpPriv->cmdPending = 0;
158 zmw_leave_critical_section(dev);
159
160 zfSendCmdEx(dev);
161 }
162 #endif
163
164 u16_t zfIssueCmd(zdev_t* dev, u32_t* cmd, u16_t cmdLen, u16_t src, u8_t* buf)
165 {
166 u16_t cmdFlag = 0;
167 u16_t ret;
168 struct zsHpPriv* hpPriv;
169
170 zmw_get_wlan_dev(dev);
171 hpPriv=wd->hpPrivate;
172
173 zmw_declare_for_critical_section();
174
175 zm_msg2_mm(ZM_LV_1, "cmdLen=", cmdLen);
176
177 zmw_enter_critical_section(dev);
178
179 #ifdef ZM_XP_USB_MULTCMD
180 ret = zfPutCmd(dev, cmd, cmdLen, src, buf);
181 zmw_leave_critical_section(dev);
182
183 if (ret != 0)
184 {
185 return 1;
186 }
187
188 zfSendCmdEx(dev);
189 #else
190 if (hpPriv->cmdPending == 0)
191 {
192 hpPriv->cmdPending = 1;
193 cmdFlag = 1;
194 }
195 ret = zfPutCmd(dev, cmd, cmdLen, src, buf);
196
197 zmw_leave_critical_section(dev);
198
199 if (ret != 0)
200 {
201 return 1;
202 }
203
204 if (cmdFlag == 1)
205 {
206 zfIdlCmd(dev, cmd, cmdLen);
207 }
208 #endif
209 return 0;
210 }
211
212 void zfIdlRsp(zdev_t* dev, u32_t* rsp, u16_t rspLen)
213 {
214 u32_t cmd[ZM_MAX_CMD_SIZE/4];
215 u16_t cmdLen;
216 u16_t src;
217 u8_t* buf;
218 u32_t ncmd[ZM_MAX_CMD_SIZE/4];
219 u16_t ncmdLen = 0;
220 u16_t ret;
221 u16_t cmdFlag = 0;
222 u16_t i;
223 s32_t nf;
224 s32_t noisefloor[4];
225 struct zsHpPriv* hpPriv;
226
227 zmw_get_wlan_dev(dev);
228 hpPriv=wd->hpPrivate;
229
230
231 zmw_declare_for_critical_section();
232
233 zmw_enter_critical_section(dev);
234
235 ret = zfGetCmd(dev, cmd, &cmdLen, &src, &buf);
236 #if 0
237 zm_assert(ret == 0);
238 #else
239 if (ret != 0)
240 {
241 zm_debug_msg0("Error IdlRsp because none cmd!!\n");
242 #ifndef ZM_XP_USB_MULTCMD
243 zmw_leave_critical_section(dev);
244 return;
245 #endif
246 }
247 #endif
248 #ifdef ZM_XP_USB_MULTCMD
249 zmw_leave_critical_section(dev);
250 #else
251 if (hpPriv->cmdTail != hpPriv->cmdHead)
252 {
253 cmdFlag = 1;
254 /* Get queueing command */
255 ncmdLen= hpPriv->cmdQ[hpPriv->cmdHead].cmdLen;
256 for (i=0; i<(ncmdLen>>2); i++)
257 {
258 ncmd[i] = hpPriv->cmdQ[hpPriv->cmdHead].cmd[i];
259 }
260 }
261 else
262 {
263 hpPriv->cmdPending = 0;
264 }
265
266 zmw_leave_critical_section(dev);
267
268 if (cmdFlag == 1)
269 {
270 zfIdlCmd(dev, ncmd, ncmdLen);
271 }
272 #endif
273 if (src == ZM_OID_READ)
274 {
275 ZM_PERFORMANCE_REG(dev, 0x11772c, rsp[1]);
276 zfwDbgReadRegDone(dev, cmd[1], rsp[1]);
277 }
278 else if (src == ZM_OID_FLASH_CHKSUM)
279 {
280 zfwDbgGetFlashChkSumDone(dev, rsp+1);
281 }
282 else if (src == ZM_OID_FLASH_READ)
283 {
284 u32_t datalen;
285 u16_t i;
286
287 datalen = (rsp[0] & 255);
288
289 zfwDbgReadFlashDone(dev, cmd[1], rsp+1, datalen);
290 }
291 else if (src == ZM_OID_FLASH_PROGRAM)
292 {
293 /* Non do */
294 }
295 else if (src == ZM_OID_WRITE)
296 {
297 zfwDbgWriteRegDone(dev, cmd[1], cmd[2]);
298 }
299 else if (src == ZM_OID_TALLY)
300 {
301 zfCollectHWTally(dev, rsp, 0);
302 }
303 else if (src == ZM_OID_TALLY_APD)
304 {
305 zfCollectHWTally(dev, rsp, 1);
306 zfwDbgReadTallyDone(dev);
307 #ifdef ZM_ENABLE_BA_RATECTRL
308 zfRateCtrlAggrSta(dev);
309 #endif
310 }
311 else if (src == ZM_OID_DKTX_STATUS)
312 {
313 zm_debug_msg0("src = zm_OID_DKTX_STATUS");
314 zfwDbgQueryHwTxBusyDone(dev, rsp[1]);
315 }
316 else if (src == ZM_CMD_SET_FREQUENCY)
317 {
318
319 //#ifdef ZM_OTUS_ENABLE_RETRY_FREQ_CHANGE
320 #if 0
321 zm_debug_msg1("Retry Set Frequency = ", rsp[1]);
322
323 #if 1
324 // Read the Noise Floor value !
325 nf = ((rsp[2]>>19) & 0x1ff);
326 if ((nf & 0x100) != 0x0)
327 {
328 noisefloor[0] = 0 - ((nf ^ 0x1ff) + 1);
329 }
330 else
331 {
332 noisefloor[0] = nf;
333 }
334
335 zm_debug_msg1("Noise Floor[1] = ", noisefloor[0]);
336
337 nf = ((rsp[3]>>19) & 0x1ff);
338 if ((nf & 0x100) != 0x0)
339 {
340 noisefloor[1] = 0 - ((nf ^ 0x1ff) + 1);
341 }
342 else
343 {
344 noisefloor[1] = nf;
345 }
346
347 zm_debug_msg1("Noise Floor[2] = ", noisefloor[1]);
348 zm_debug_msg1("Is Site Survey = ", hpPriv->isSiteSurvey);
349 #endif
350
351 if ( (rsp[1] && hpPriv->freqRetryCounter == 0) ||
352 (((noisefloor[0]>-60)||(noisefloor[1]>-60)) && hpPriv->freqRetryCounter==0) ||
353 ((abs(noisefloor[0]-noisefloor[1])>=9) && hpPriv->freqRetryCounter==0) )
354 {
355 zm_debug_msg0("Retry to issue the frequency change command");
356
357 if ( hpPriv->recordFreqRetryCounter == 1 )
358 {
359 zm_debug_msg0("Cold Reset");
360
361 zfHpSetFrequencyEx(dev, hpPriv->latestFrequency,
362 hpPriv->latestBw40,
363 hpPriv->latestExtOffset,
364 2);
365
366 if ( hpPriv->isSiteSurvey != 2 )
367 {
368 hpPriv->freqRetryCounter++;
369 }
370 hpPriv->recordFreqRetryCounter = 0;
371 }
372 else
373 {
374 zfHpSetFrequencyEx(dev, hpPriv->latestFrequency,
375 hpPriv->latestBw40,
376 hpPriv->latestExtOffset,
377 0);
378 }
379 hpPriv->recordFreqRetryCounter++;
380 }
381 else
382 #endif
383
384 /* ret: Bit0: AGC calibration 0=>finish 1=>unfinish */
385 /* Bit1: Noise calibration 0=>finish 1=>unfinish */
386 /* Bit2: Noise calibration finish, but NF value unexcepted => 1 */
387 if ( (rsp[1] & 0x1) || (rsp[1] & 0x4) )
388 {
389 zm_debug_msg1("Set Frequency fail : ret = ", rsp[1]);
390
391 /* 1. AGC Calibration fail */
392 /* 2. Noise Calibration finish but error NoiseFloor value */
393 /* and not in sitesurvey, try more twice */
394 if ( hpPriv->isSiteSurvey == 2 )
395 {
396 if ( hpPriv->recordFreqRetryCounter < 2 )
397 {
398 /* cold reset */
399 zfHpSetFrequencyEx(dev, hpPriv->latestFrequency,
400 hpPriv->latestBw40,
401 hpPriv->latestExtOffset,
402 2);
403 hpPriv->recordFreqRetryCounter++;
404 zm_debug_msg1("Retry to issue the frequency change command(cold reset) counter = ", hpPriv->recordFreqRetryCounter);
405 }
406 else
407 {
408 /* Fail : we would not accept this result! */
409 zm_debug_msg0("\n\n\n\n Fail twice cold reset \n\n\n\n");
410 hpPriv->coldResetNeedFreq = 0;
411 hpPriv->recordFreqRetryCounter = 0;
412 zfCoreSetFrequencyComplete(dev);
413 }
414 }
415 else
416 {
417 /* in sitesurvey, coldreset in next channel */
418 hpPriv->coldResetNeedFreq = 1;
419 hpPriv->recordFreqRetryCounter = 0;
420 zfCoreSetFrequencyComplete(dev);
421 }
422 }
423 else if (rsp[1] & 0x2)
424 {
425 zm_debug_msg1("Set Frequency fail 2 : ret = ", rsp[1]);
426
427 /* Noise Calibration un-finish */
428 /* and not in sitesurvey, try more once */
429 if ( hpPriv->isSiteSurvey == 2 )
430 {
431 if ( hpPriv->recordFreqRetryCounter < 1 )
432 {
433 /* cold reset */
434 zfHpSetFrequencyEx(dev, hpPriv->latestFrequency,
435 hpPriv->latestBw40,
436 hpPriv->latestExtOffset,
437 2);
438 hpPriv->recordFreqRetryCounter++;
439 zm_debug_msg1("2 Retry to issue the frequency change command(cold reset) counter = ", hpPriv->recordFreqRetryCounter);
440 }
441 else
442 {
443 /* Fail : we would not accept this result! */
444 zm_debug_msg0("\n\n\n\n 2 Fail twice cold reset \n\n\n\n");
445 hpPriv->coldResetNeedFreq = 0;
446 hpPriv->recordFreqRetryCounter = 0;
447 zfCoreSetFrequencyComplete(dev);
448 }
449 }
450 else
451 {
452 /* in sitesurvey, skip this frequency */
453 hpPriv->coldResetNeedFreq = 0;
454 hpPriv->recordFreqRetryCounter = 0;
455 zfCoreSetFrequencyComplete(dev);
456 }
457 }
458 //else if (rsp[1] & 0x4)
459 //{
460 // zm_debug_msg1("Set Frequency fail 3 : ret = ", rsp[1]);
461 // hpPriv->coldResetNeedFreq = 0;
462 // hpPriv->recordFreqRetryCounter = 0;
463 // zfCoreSetFrequencyComplete(dev);
464 //}
465 else
466 {
467 //hpPriv->freqRetryCounter = 0;
468 zm_debug_msg2(" return complete, ret = ", rsp[1]);
469
470 /* set bb_heavy_clip_enable */
471 if (hpPriv->enableBBHeavyClip && hpPriv->hwBBHeavyClip &&
472 hpPriv->doBBHeavyClip)
473 {
474 u32_t setValue = 0x200;
475
476 setValue |= hpPriv->setValueHeavyClip;
477
478 //zm_dbg(("Do heavy clip setValue = %d\n", setValue));
479
480 zfDelayWriteInternalReg(dev, 0x99e0+0x1bc000, setValue);
481 zfFlushDelayWrite(dev);
482 }
483
484 hpPriv->coldResetNeedFreq = 0;
485 hpPriv->recordFreqRetryCounter = 0;
486 zfCoreSetFrequencyComplete(dev);
487 }
488
489 #if 1
490 // Read the Noise Floor value !
491 nf = ((rsp[2]>>19) & 0x1ff);
492 if ((nf & 0x100) != 0x0)
493 {
494 noisefloor[0] = 0 - ((nf ^ 0x1ff) + 1);
495 }
496 else
497 {
498 noisefloor[0] = nf;
499 }
500
501 //zm_debug_msg1("Noise Floor[1] = ", noisefloor[0]);
502
503 nf = ((rsp[3]>>19) & 0x1ff);
504 if ((nf & 0x100) != 0x0)
505 {
506 noisefloor[1] = 0 - ((nf ^ 0x1ff) + 1);
507 }
508 else
509 {
510 noisefloor[1] = nf;
511 }
512
513 //zm_debug_msg1("Noise Floor[2] = ", noisefloor[1]);
514
515 nf = ((rsp[5]>>23) & 0x1ff);
516 if ((nf & 0x100) != 0x0)
517 {
518 noisefloor[2] = 0 - ((nf ^ 0x1ff) + 1);
519 }
520 else
521 {
522 noisefloor[2] = nf;
523 }
524
525 //zm_debug_msg1("Noise Floor ext[1] = ", noisefloor[2]);
526
527 nf = ((rsp[6]>>23) & 0x1ff);
528 if ((nf & 0x100) != 0x0)
529 {
530 noisefloor[3] = 0 - ((nf ^ 0x1ff) + 1);
531 }
532 else
533 {
534 noisefloor[3] = nf;
535 }
536
537 //zm_debug_msg1("Noise Floor ext[2] = ", noisefloor[3]);
538
539 //zm_debug_msg1("Is Site Survey = ", hpPriv->isSiteSurvey);
540 #endif
541 }
542 else if (src == ZM_CMD_SET_KEY)
543 {
544 zfCoreSetKeyComplete(dev);
545 }
546 else if (src == ZM_CWM_READ)
547 {
548 zm_msg2_mm(ZM_LV_0, "CWM rsp[1]=", rsp[1]);
549 zm_msg2_mm(ZM_LV_0, "CWM rsp[2]=", rsp[2]);
550 zfCoreCwmBusy(dev, zfCwmIsExtChanBusy(rsp[1], rsp[2]));
551 }
552 else if (src == ZM_MAC_READ)
553 {
554 /* rsp[1] = ZM_SEEPROM_MAC_ADDRESS_OFFSET; */
555 /* rsp[2] = ZM_SEEPROM_MAC_ADDRESS_OFFSET+4; */
556 /* rsp[3] = ZM_SEEPROM_REGDOMAIN_OFFSET; */
557 /* rsp[4] = ZM_SEEPROM_VERISON_OFFSET; */
558 /* rsp[5] = ZM_SEEPROM_HARDWARE_TYPE_OFFSET; */
559 /* rsp[6] = ZM_SEEPROM_HW_HEAVY_CLIP; */
560
561 u8_t addr[6], CCS, WWR;
562 u16_t CountryDomainCode;
563
564 /* BB heavy clip */
565 //hpPriv->eepromHeavyClipFlag = (u8_t)((rsp[6]>>24) & 0xff); // force enable 8107
566 //zm_msg2_mm(ZM_LV_0, "eepromHeavyClipFlag", hpPriv->eepromHeavyClipFlag);
567 #if 0
568 if (hpPriv->hwBBHeavyClip)
569 {
570 zm_msg0_mm(ZM_LV_0, "enable BB Heavy Clip");
571 }
572 else
573 {
574 zm_msg0_mm(ZM_LV_0, "Not enable BB Heavy Clip");
575 }
576 #endif
577 zm_msg2_mm(ZM_LV_0, "MAC rsp[1]=", rsp[1]);
578 zm_msg2_mm(ZM_LV_0, "MAC rsp[2]=", rsp[2]);
579
580 addr[0] = (u8_t)(rsp[1] & 0xff);
581 addr[1] = (u8_t)((rsp[1]>>8) & 0xff);
582 addr[2] = (u8_t)((rsp[1]>>16) & 0xff);
583 addr[3] = (u8_t)((rsp[1]>>24) & 0xff);
584 addr[4] = (u8_t)(rsp[2] & 0xff);
585 addr[5] = (u8_t)((rsp[2]>>8) & 0xff);
586 /*#ifdef ZM_FB50
587 addr[0] = (u8_t)(0 & 0xff);
588 addr[1] = (u8_t)(3 & 0xff);
589 addr[2] = (u8_t)(127 & 0xff);
590 addr[3] = (u8_t)(0 & 0xff);
591 addr[4] = (u8_t)(9 & 0xff);
592 addr[5] = (u8_t)(11 & 0xff);
593 #endif*/
594
595 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
596 ((((u32_t)addr[3])<<24) | (((u32_t)addr[2])<<16) | (((u32_t)addr[1])<<8) | addr[0]));
597 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H,
598 ((((u32_t)addr[5])<<8) | addr[4]));
599 zfFlushDelayWrite(dev);
600
601 wd->ledStruct.ledMode[0] = (u16_t)(rsp[5]&0xffff);
602 wd->ledStruct.ledMode[1] = (u16_t)(rsp[5]>>16);
603 zm_msg2_mm(ZM_LV_0, "ledMode[0]=", wd->ledStruct.ledMode[0]);
604 zm_msg2_mm(ZM_LV_0, "ledMode[1]=", wd->ledStruct.ledMode[1]);
605
606 /* Regulatory Related Setting */
607 zm_msg2_mm(ZM_LV_0, "RegDomain rsp=", rsp[3]);
608 zm_msg2_mm(ZM_LV_0, "OpFlags+EepMisc=", rsp[4]);
609 hpPriv->OpFlags = (u8_t)((rsp[4]>>16) & 0xff);
610 if ((rsp[2] >> 24) == 0x1) //Tx mask == 0x1
611 {
612 zm_msg0_mm(ZM_LV_0, "OTUS 1x2");
613 hpPriv->halCapability |= ZM_HP_CAP_11N_ONE_TX_STREAM;
614 }
615 else
616 {
617 zm_msg0_mm(ZM_LV_0, "OTUS 2x2");
618 }
619 if (hpPriv->OpFlags & 0x1)
620 {
621 hpPriv->halCapability |= ZM_HP_CAP_5G;
622 }
623 if (hpPriv->OpFlags & 0x2)
624 {
625 hpPriv->halCapability |= ZM_HP_CAP_2G;
626 }
627
628
629 CCS = (u8_t)((rsp[3] & 0x8000) >> 15);
630 WWR = (u8_t)((rsp[3] & 0x4000) >> 14);
631 CountryDomainCode = (u16_t)(rsp[3] & 0x3FFF);
632
633 if (rsp[3] != 0xffffffff)
634 {
635 if (CCS)
636 {
637 //zm_debug_msg0("CWY - Get Regulation Table from Country Code");
638 zfHpGetRegulationTablefromCountry(dev, CountryDomainCode);
639 }
640 else
641 {
642 //zm_debug_msg0("CWY - Get Regulation Table from Reg Domain");
643 zfHpGetRegulationTablefromRegionCode(dev, CountryDomainCode);
644 }
645 if (WWR)
646 {
647 //zm_debug_msg0("CWY - Enable 802.11d");
648 /* below line shall be unmarked after A band is ready */
649 //zfiWlanSetDot11DMode(dev, 1);
650 }
651 }
652 else
653 {
654 zfHpGetRegulationTablefromRegionCode(dev, NO_ENUMRD);
655 }
656
657 zfCoreMacAddressNotify(dev, addr);
658
659 }
660 else if (src == ZM_EEPROM_READ)
661 {
662 #if 0
663 u8_t addr[6], CCS, WWR;
664 u16_t CountryDomainCode;
665 #endif
666 for (i=0; i<ZM_HAL_MAX_EEPROM_PRQ; i++)
667 {
668 if (hpPriv->eepromImageIndex < 1024)
669 {
670 hpPriv->eepromImage[hpPriv->eepromImageIndex++] = rsp[i+1];
671 }
672 }
673
674 if (hpPriv->eepromImageIndex == (ZM_HAL_MAX_EEPROM_REQ*ZM_HAL_MAX_EEPROM_PRQ))
675 {
676 #if 0
677 for (i=0; i<1024; i++)
678 {
679 zm_msg2_mm(ZM_LV_0, "index=", i);
680 zm_msg2_mm(ZM_LV_0, "eepromImage=", hpPriv->eepromImage[i]);
681 }
682 #endif
683 zm_msg2_mm(ZM_LV_0, "MAC [1]=", hpPriv->eepromImage[0x20c/4]);
684 zm_msg2_mm(ZM_LV_0, "MAC [2]=", hpPriv->eepromImage[0x210/4]);
685 #if 0
686 addr[0] = (u8_t)(hpPriv->eepromImage[0x20c/4] & 0xff);
687 addr[1] = (u8_t)((hpPriv->eepromImage[0x20c/4]>>8) & 0xff);
688 addr[2] = (u8_t)((hpPriv->eepromImage[0x20c/4]>>16) & 0xff);
689 addr[3] = (u8_t)((hpPriv->eepromImage[0x20c/4]>>24) & 0xff);
690 addr[4] = (u8_t)(hpPriv->eepromImage[0x210/4] & 0xff);
691 addr[5] = (u8_t)((hpPriv->eepromImage[0x210/4]>>8) & 0xff);
692
693 zfCoreMacAddressNotify(dev, addr);
694
695 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_L,
696 ((((u32_t)addr[3])<<24) | (((u32_t)addr[2])<<16) | (((u32_t)addr[1])<<8) | addr[0]));
697 zfDelayWriteInternalReg(dev, ZM_MAC_REG_MAC_ADDR_H,
698 ((((u32_t)addr[5])<<8) | addr[4]));
699 zfFlushDelayWrite(dev);
700
701 /* Regulatory Related Setting */
702 zm_msg2_mm(ZM_LV_0, "RegDomain =", hpPriv->eepromImage[0x208/4]);
703 CCS = (u8_t)((hpPriv->eepromImage[0x208/4] & 0x8000) >> 15);
704 WWR = (u8_t)((hpPriv->eepromImage[0x208/4] & 0x4000) >> 14);
705 /* below line shall be unmarked after A band is ready */
706 //CountryDomainCode = (u16_t)(hpPriv->eepromImage[0x208/4] & 0x3FFF);
707 CountryDomainCode = 8;
708 if (CCS)
709 {
710 //zm_debug_msg0("CWY - Get Regulation Table from Country Code");
711 zfHpGetRegulationTablefromCountry(dev, CountryDomainCode);
712 }
713 else
714 {
715 //zm_debug_msg0("CWY - Get Regulation Table from Reg Domain");
716 zfHpGetRegulationTablefromRegionCode(dev, CountryDomainCode);
717 }
718 if (WWR)
719 {
720 //zm_debug_msg0("CWY - Enable 802.11d");
721 /* below line shall be unmarked after A band is ready */
722 //zfiWlanSetDot11DMode(dev, 1);
723 }
724 #endif
725 zfCoreHalInitComplete(dev);
726 }
727 else
728 {
729 hpPriv->eepromImageRdReq++;
730 zfHpLoadEEPROMFromFW(dev);
731 }
732 }
733 else if (src == ZM_EEPROM_WRITE)
734 {
735 zfwDbgWriteEepromDone(dev, cmd[1], cmd[2]);
736 }
737 else if (src == ZM_ANI_READ)
738 {
739 u32_t cycleTime, ctlClear;
740
741 zm_msg2_mm(ZM_LV_0, "ANI rsp[1]=", rsp[1]);
742 zm_msg2_mm(ZM_LV_0, "ANI rsp[2]=", rsp[2]);
743 zm_msg2_mm(ZM_LV_0, "ANI rsp[3]=", rsp[3]);
744 zm_msg2_mm(ZM_LV_0, "ANI rsp[4]=", rsp[4]);
745
746 hpPriv->ctlBusy += rsp[1];
747 hpPriv->extBusy += rsp[2];
748
749 cycleTime = 100000; //100 miniseconds
750
751 if (cycleTime > rsp[1])
752 {
753 ctlClear = (cycleTime - rsp[1]) / 100;
754 }
755 else
756 {
757 ctlClear = 0;
758 }
759 if (wd->aniEnable)
760 zfHpAniArPoll(dev, ctlClear, rsp[3], rsp[4]);
761 }
762 else if (src == ZM_CMD_ECHO)
763 {
764 if ( ((struct zsHpPriv*)wd->hpPrivate)->halReInit )
765 {
766 zfCoreHalInitComplete(dev);
767 ((struct zsHpPriv*)wd->hpPrivate)->halReInit = 0;
768 }
769 else
770 {
771 zfHpLoadEEPROMFromFW(dev);
772 }
773 }
774 else if (src == ZM_OID_FW_DL_INIT)
775 {
776 zfwDbgDownloadFwInitDone(dev);
777 }
778 return;
779 }
780
781
782 /************************************************************************/
783 /* */
784 /* FUNCTION DESCRIPTION zfWriteRegInternalReg */
785 /* Write on chip internal register immediately. */
786 /* */
787 /* INPUTS */
788 /* dev : device pointer */
789 /* addr : register address */
790 /* val : value */
791 /* */
792 /* OUTPUTS */
793 /* 0 : success */
794 /* other : fail */
795 /* */
796 /* AUTHOR */
797 /* Stephen Chen ZyDAS Technology Corporation 2005.11 */
798 /* */
799 /************************************************************************/
800 u32_t zfWriteRegInternalReg(zdev_t* dev, u32_t addr, u32_t val)
801 {
802 u32_t cmd[3];
803 u16_t ret;
804
805 cmd[0] = 0x00000108;
806 cmd[1] = addr;
807 cmd[2] = val;
808
809 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_INTERNAL_WRITE, NULL);
810 return ret;
811 }
812
813
814 /************************************************************************/
815 /* */
816 /* FUNCTION DESCRIPTION zfDelayWriteInternalReg */
817 /* Write on chip internal register, write operation may be */
818 /* postponed to form a multiple write command. */
819 /* */
820 /* INPUTS */
821 /* dev : device pointer */
822 /* addr : register address */
823 /* val : value */
824 /* */
825 /* OUTPUTS */
826 /* 0 : command been postponed */
827 /* 1 : commands been executed */
828 /* */
829 /* AUTHOR */
830 /* Stephen Chen ZyDAS Technology Corporation 2005.11 */
831 /* */
832 /************************************************************************/
833 u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val)
834 {
835 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
836 u16_t i;
837 u16_t ret;
838 struct zsHpPriv* hpPriv;
839
840 zmw_get_wlan_dev(dev);
841 hpPriv=wd->hpPrivate;
842
843 zmw_declare_for_critical_section();
844
845 /* enter critical section */
846 zmw_enter_critical_section(dev);
847
848 /* Store command to global buffer */
849 hpPriv->cmd.delayWcmdAddr[hpPriv->cmd.delayWcmdCount] = addr;
850 hpPriv->cmd.delayWcmdVal[hpPriv->cmd.delayWcmdCount++] = val;
851
852 /* If pending command reach size limit */
853 if ((hpPriv->cmd.delayWcmdCount) >= ((ZM_MAX_CMD_SIZE - 4) >> 3))
854 {
855 cmd[0] = 0x00000100 + (hpPriv->cmd.delayWcmdCount<<3);
856
857 /* copy command to cmd buffer */
858 for (i=0; i<hpPriv->cmd.delayWcmdCount; i++)
859 {
860 cmd[1+(i<<1)] = hpPriv->cmd.delayWcmdAddr[i];
861 cmd[2+(i<<1)] = hpPriv->cmd.delayWcmdVal[i];
862 }
863 /* reset pending command */
864 hpPriv->cmd.delayWcmdCount = 0;
865
866 /* leave critical section */
867 zmw_leave_critical_section(dev);
868
869 /* issue write command */
870 ret = zfIssueCmd(dev, cmd, 4+(i<<3), ZM_OID_INTERNAL_WRITE, NULL);
871
872 return 1;
873 }
874 else
875 {
876 /* leave critical section */
877 zmw_leave_critical_section(dev);
878
879 return 0;
880 }
881 }
882
883
884 /************************************************************************/
885 /* */
886 /* FUNCTION DESCRIPTION zfFlushDelayWrite */
887 /* Flush pending write command. */
888 /* */
889 /* INPUTS */
890 /* dev : device pointer */
891 /* */
892 /* OUTPUTS */
893 /* 0 : no pending command */
894 /* 1 : commands been executed */
895 /* */
896 /* AUTHOR */
897 /* Stephen Chen ZyDAS Technology Corporation 2005.11 */
898 /* */
899 /************************************************************************/
900 u16_t zfFlushDelayWrite(zdev_t* dev)
901 {
902 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
903 u16_t i;
904 u16_t ret;
905 struct zsHpPriv* hpPriv;
906
907 zmw_get_wlan_dev(dev);
908 hpPriv=wd->hpPrivate;
909
910 zmw_declare_for_critical_section();
911
912 /* enter critical section */
913 zmw_enter_critical_section(dev);
914
915 /* If there is pending command */
916 if (hpPriv->cmd.delayWcmdCount > 0)
917 {
918 cmd[0] = 0x00000100 + (hpPriv->cmd.delayWcmdCount<<3);
919
920 /* copy command to cmd buffer */
921 for (i=0; i<hpPriv->cmd.delayWcmdCount; i++)
922 {
923 cmd[1+(i<<1)] = hpPriv->cmd.delayWcmdAddr[i];
924 cmd[2+(i<<1)] = hpPriv->cmd.delayWcmdVal[i];
925 }
926 /* reset pending command */
927 hpPriv->cmd.delayWcmdCount = 0;
928
929 /* leave critical section */
930 zmw_leave_critical_section(dev);
931
932 /* issue write command */
933 ret = zfIssueCmd(dev, cmd, 4+(i<<3), ZM_OID_INTERNAL_WRITE, NULL);
934
935 return 1;
936 }
937 else
938 {
939 /* leave critical section */
940 zmw_leave_critical_section(dev);
941
942 return 0;
943 }
944 }
945
946
947 u32_t zfiDbgDelayWriteReg(zdev_t* dev, u32_t addr, u32_t val)
948 {
949 zfDelayWriteInternalReg(dev, addr, val);
950 return 0;
951 }
952
953 u32_t zfiDbgFlushDelayWrite(zdev_t* dev)
954 {
955 zfFlushDelayWrite(dev);
956 return 0;
957 }
958
959 /************************************************************************/
960 /* */
961 /* FUNCTION DESCRIPTION zfiDbgWriteReg */
962 /* Write register. */
963 /* */
964 /* INPUTS */
965 /* dev : device pointer */
966 /* addr : register address */
967 /* val : value */
968 /* */
969 /* OUTPUTS */
970 /* 0 : success */
971 /* other : fail */
972 /* */
973 /* AUTHOR */
974 /* Stephen Chen ZyDAS Technology Corporation 2005.10 */
975 /* */
976 /************************************************************************/
977 u32_t zfiDbgWriteReg(zdev_t* dev, u32_t addr, u32_t val)
978 {
979 u32_t cmd[3];
980 u16_t ret;
981
982 cmd[0] = 0x00000108;
983 cmd[1] = addr;
984 cmd[2] = val;
985
986 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_WRITE, 0);
987 return ret;
988 }
989 /************************************************************************/
990 /* */
991 /* FUNCTION DESCRIPTION zfiDbgWriteFlash */
992 /* Write flash. */
993 /* */
994 /* INPUTS */
995 /* dev : device pointer */
996 /* addr : register address */
997 /* val : value */
998 /* */
999 /* OUTPUTS */
1000 /* 0 : success */
1001 /* other : fail */
1002 /* */
1003 /* AUTHOR */
1004 /* Yjsung ZyDAS Technology Corporation 2007.02 */
1005 /* */
1006 /************************************************************************/
1007 u32_t zfiDbgWriteFlash(zdev_t* dev, u32_t addr, u32_t val)
1008 {
1009 u32_t cmd[3];
1010 u16_t ret;
1011
1012 //cmd[0] = 0x0000B008;
1013 /* len[0] : type[0xB0] : seq[?] */
1014 cmd[0] = 8 | (ZM_CMD_WFLASH << 8);
1015 cmd[1] = addr;
1016 cmd[2] = val;
1017
1018 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_WRITE, 0);
1019 return ret;
1020 }
1021
1022 /************************************************************************/
1023 /* */
1024 /* FUNCTION DESCRIPTION zfiDbgWriteEeprom */
1025 /* Write EEPROM. */
1026 /* */
1027 /* INPUTS */
1028 /* dev : device pointer */
1029 /* addr : register address */
1030 /* val : value */
1031 /* */
1032 /* OUTPUTS */
1033 /* 0 : success */
1034 /* other : fail */
1035 /* */
1036 /* AUTHOR */
1037 /* Paul ZyDAS Technology Corporation 2007.06 */
1038 /* */
1039 /************************************************************************/
1040 u32_t zfiDbgWriteEeprom(zdev_t* dev, u32_t addr, u32_t val)
1041 {
1042 u32_t cmd[3];
1043 u16_t ret;
1044
1045 //cmd[0] = 0x0000B008;
1046 /* len[0] : type[0xB0] : seq[?] */
1047 cmd[0] = 8 | (ZM_CMD_WREEPROM << 8);
1048 cmd[1] = addr;
1049 cmd[2] = val;
1050
1051 ret = zfIssueCmd(dev, cmd, 12, ZM_EEPROM_WRITE, 0);
1052 return ret;
1053 }
1054
1055 /************************************************************************/
1056 /* */
1057 /* FUNCTION DESCRIPTION zfiDbgBlockWriteEeprom */
1058 /* Block Write Eeprom. */
1059 /* */
1060 /* p.s: now,it will write 16 bytes register data per block (N=4) */
1061 /* */
1062 /* INPUTS */
1063 /* dev : device pointer */
1064 /* addr : register address */
1065 /* buf : input data buffer pointer */
1066 /* */
1067 /* OUTPUTS */
1068 /* 0 : success */
1069 /* other : fail */
1070 /* */
1071 /* AUTHOR */
1072 /* Paul ZyDAS Technology Corporation 2007.06 */
1073 /* */
1074 /************************************************************************/
1075 //#define N buflen/4
1076 //#define SIZE (2*N+1)
1077
1078 u32_t zfiDbgBlockWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf)
1079 {
1080 u32_t cmd[9]; //2N+1
1081 u16_t ret,i;
1082
1083 //cmd[0] = 0x0000B008;
1084 /* len[0] : type[0xB0] : seq[?] */
1085
1086 //cmd[0] = (8*N) | (ZM_CMD_WFLASH << 8);
1087 cmd[0] = 32 | (ZM_CMD_WREEPROM << 8); //8N
1088
1089 for (i=0; i<4; i++) // i<N
1090 {
1091 cmd[(2*i)+1] = addr+(4*i);
1092 cmd[(2*i)+2] = *(buf+i);
1093 }
1094
1095 ret = zfIssueCmd(dev, cmd, 36, ZM_EEPROM_WRITE, 0); //8N+4
1096
1097 // added for EEPROMUpdate, wait a moment for prevent cmd queue full!
1098 //zfwSleep(dev, 1);
1099
1100 return ret;
1101 }
1102
1103
1104 /* write EEPROM with wrlen : wrlen must be 4*n */
1105 /* command format : cmd_info(4) + addr(4) + eeprom(wrlen) */
1106 u32_t zfiDbgBlockWriteEeprom_v2(zdev_t* dev, u32_t addr, u32_t* buf, u32_t wrlen)
1107 {
1108 u32_t cmd[16];
1109 u16_t ret,i;
1110
1111 /* len[0] : type[0xB0] : seq[?] */
1112 /* len = addr(4) + eeprom_block(wrlen) */
1113 cmd[0] = (wrlen+4) | (ZM_CMD_MEM_WREEPROM << 8);
1114 cmd[1] = addr;
1115
1116 for (i=0; i<(wrlen/4); i++) // i<wrlen/4
1117 {
1118 cmd[2+i] = *(buf+i);
1119 }
1120 /* cmd_info(4) + addr(4) + eeprom(wrlen) */
1121 ret = zfIssueCmd(dev, cmd, (u16_t)(wrlen+8), ZM_EEPROM_WRITE, 0);
1122
1123 return ret;
1124 }
1125
1126 /************************************************************************/
1127 /* */
1128 /* FUNCTION DESCRIPTION zfDbgOpenEeprom */
1129 /* Open EEPROM. */
1130 /* */
1131 /* INPUTS */
1132 /* dev : device pointer */
1133 /* */
1134 /* OUTPUTS */
1135 /* */
1136 /* AUTHOR */
1137 /* Paul ZyDAS Technology Corporation 2007.06 */
1138 /* */
1139 /************************************************************************/
1140 void zfDbgOpenEeprom(zdev_t* dev)
1141 {
1142 // unlock EEPROM
1143 zfDelayWriteInternalReg(dev, 0x1D1400, 0x12345678);
1144 zfDelayWriteInternalReg(dev, 0x1D1404, 0x55aa00ff);
1145 zfDelayWriteInternalReg(dev, 0x1D1408, 0x13579ace);
1146 zfDelayWriteInternalReg(dev, 0x1D1414, 0x0);
1147 zfFlushDelayWrite(dev);
1148 }
1149
1150 /************************************************************************/
1151 /* */
1152 /* FUNCTION DESCRIPTION zfDbgCloseEeprom */
1153 /* Close EEPROM. */
1154 /* */
1155 /* INPUTS */
1156 /* dev : device pointer */
1157 /* */
1158 /* OUTPUTS */
1159 /* */
1160 /* AUTHOR */
1161 /* Paul ZyDAS Technology Corporation 2007.05 */
1162 /* */
1163 /************************************************************************/
1164 void zfDbgCloseEeprom(zdev_t* dev)
1165 {
1166 // lock EEPROM
1167 zfDelayWriteInternalReg(dev, 0x1D1400, 0x87654321);
1168 //zfDelayWriteInternalReg(dev, 0x1D1404, 0xffffffff);
1169 //zfDelayWriteInternalReg(dev, 0x1D1408, 0xffffffff);
1170 //zfDelayWriteInternalReg(dev, 0x1D1414, 0x100);
1171 zfFlushDelayWrite(dev);
1172 }
1173 #if 0
1174 /************************************************************************/
1175 /* */
1176 /* FUNCTION DESCRIPTION zfiSeriallyWriteEeprom */
1177 /* Write EEPROM Serially. */
1178 /* */
1179 /* INPUTS */
1180 /* dev : device pointer */
1181 /* addr : start address of writing EEPROM */
1182 /* buf : input data buffer */
1183 /* buflen : size of input data buffer */
1184 /* (length of data write into EEPROM) */
1185 /* */
1186 /* OUTPUTS */
1187 /* */
1188 /* */
1189 /* */
1190 /* AUTHOR */
1191 /* Paul ZyDAS Technology Corporation 2007.06 */
1192 /* */
1193 /************************************************************************/
1194 u32_t zfiSeriallyWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf, u32_t buflen)
1195 {
1196 u32_t count;
1197 u16_t i,ret,blocksize;
1198 u8_t temp[2];
1199
1200 // per 4 bytes = 1 count
1201 count = buflen/4;
1202
1203 // Open EEPROM
1204 zfDbgOpenEeprom(dev);
1205
1206 // Write EEPROM
1207 for (i=0; i<count; i++)
1208 {
1209 if (zfwWriteEeprom(dev, (addr+(4*i)), *(buf+i), 0) != 0)
1210 {
1211 // Update failed, Close EEPROM
1212 zm_debug_msg0("zfwWriteEeprom failed \n");
1213 zfDbgCloseEeprom(dev);
1214 return 1;
1215 }
1216 }
1217
1218 // Close EEPROM
1219 zfDbgCloseEeprom(dev);
1220 return 0;
1221 }
1222 #endif
1223 #if 0
1224 /************************************************************************/
1225 /* */
1226 /* FUNCTION DESCRIPTION zfiSeriallyBlockWriteEeprom */
1227 /* Block Write EEPROM Serially. */
1228 /* (BlockWrite: per 16bytes write EEPROM once) */
1229 /* */
1230 /* INPUTS */
1231 /* dev : device pointer */
1232 /* addr : register address */
1233 /* buf : input data buffer */
1234 /* buflen : access data size of buf */
1235 /* */
1236 /* OUTPUTS */
1237 /* 0 : success */
1238 /* other : fail */
1239 /* */
1240 /* AUTHOR */
1241 /* Paul ZyDAS Technology Corporation 2007.05 */
1242 /* */
1243 /************************************************************************/
1244 u32_t zfiSeriallyBlockWriteEeprom(zdev_t* dev, u32_t addr, u32_t* buf, u32_t buflen)
1245 {
1246 u32_t count;
1247 u16_t i,ret,blocksize;
1248 u8_t temp[2];
1249
1250 // per 4 bytes = 1 count
1251 count = buflen/4;
1252
1253 // Open EEPROM
1254 zfDbgOpenEeprom(dev);
1255
1256 // Write EEPROM
1257 // EEPROM Write start address from: 0x1000!?
1258 // per 16bytes(N=4) block write EEPROM once
1259 for (i=0; i<(count/4); i++) // count/N
1260 {
1261 //zfiDbgBlockWriteEeprom(dev, (addr+(4*N*i)), buf+(N*i));
1262 //zfiDbgBlockWriteEeprom(dev, (addr+(16*i)), buf+(4*i));
1263 if (zfwBlockWriteEeprom(dev, (addr+(16*i)), buf+(4*i), 0) != 0)
1264 {
1265 zm_debug_msg0("zfiDbgBlockWriteEeprom failed \n");
1266 // Close EEPROM
1267 zfDbgCloseEeprom(dev);
1268 return 1;
1269 }
1270 }
1271
1272 // Close EEPROM
1273 zfDbgCloseEeprom(dev);
1274 return 0;
1275 }
1276 #endif
1277 #if 0
1278 /************************************************************************/
1279 /* */
1280 /* FUNCTION DESCRIPTION zfiDbgDumpEeprom */
1281 /* Dump EEPROM. */
1282 /* */
1283 /* INPUTS */
1284 /* dev : device pointer */
1285 /* addr : start address of dumping EEPROM */
1286 /* datalen : length of access EEPROM data */
1287 /* buf : point of buffer, the buffer saved dump data */
1288 /* */
1289 /* OUTPUTS */
1290 /* 0 : success */
1291 /* other : fail */
1292 /* */
1293 /* AUTHOR */
1294 /* Paul ZyDAS Technology Corporation 2007.06 */
1295 /* */
1296 /************************************************************************/
1297 u32_t zfiDbgDumpEeprom(zdev_t* dev, u32_t addr, u32_t datalen, u32_t* buf)
1298 {
1299 u32_t count;
1300 u16_t i,ret;
1301
1302 count = datalen/4;
1303
1304 // over EEPROM length
1305 if(datalen > 0x2000)
1306 {
1307 return 1;
1308 }
1309
1310 for(i=0; i<count; i++)
1311 {
1312 buf[i] = zfwReadEeprom(dev, addr+(4*i));
1313 }
1314
1315 return 0;
1316 }
1317 #endif
1318 /************************************************************************/
1319 /* */
1320 /* FUNCTION DESCRIPTION zfiDbgReadReg */
1321 /* Read register. */
1322 /* */
1323 /* INPUTS */
1324 /* dev : device pointer */
1325 /* addr : register address */
1326 /* */
1327 /* OUTPUTS */
1328 /* 0 : success */
1329 /* other : fail */
1330 /* */
1331 /* AUTHOR */
1332 /* Stephen Chen ZyDAS Technology Corporation 2005.10 */
1333 /* */
1334 /************************************************************************/
1335 u32_t zfiDbgReadReg(zdev_t* dev, u32_t addr)
1336 {
1337 u32_t cmd[2];
1338 u16_t ret;
1339
1340 cmd[0] = 0x00000004;
1341 cmd[1] = addr;
1342
1343 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_READ, 0);
1344 return ret;
1345 }
1346
1347
1348 /************************************************************************/
1349 /* */
1350 /* FUNCTION DESCRIPTION zfiDbgReadTally */
1351 /* Read register. */
1352 /* */
1353 /* INPUTS */
1354 /* dev : device pointer */
1355 /* */
1356 /* OUTPUTS */
1357 /* 0 : success */
1358 /* other : fail */
1359 /* */
1360 /* AUTHOR */
1361 /* Stephen Chen ZyDAS Technology Corporation 2005.10 */
1362 /* */
1363 /************************************************************************/
1364 u32_t zfiDbgReadTally(zdev_t* dev)
1365 {
1366 u32_t cmd[1];
1367 u16_t ret;
1368 zmw_get_wlan_dev(dev);
1369
1370 if ( ((struct zsHpPriv*)wd->hpPrivate)->halReInit )
1371 {
1372 return 1;
1373 }
1374
1375 /* len[0] : type[0x81] : seq[?] */
1376 cmd[0] = 0 | (ZM_CMD_TALLY << 8);
1377 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_TALLY, 0);
1378
1379 /* len[0] : type[0x82] : seq[?] */
1380 cmd[0] = 0 | (ZM_CMD_TALLY_APD << 8);
1381 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_TALLY_APD, 0);
1382
1383 return ret;
1384 }
1385
1386
1387 u32_t zfiDbgSetIFSynthesizer(zdev_t* dev, u32_t value)
1388 {
1389 u32_t cmd[2];
1390 u16_t ret;
1391
1392 /* len[4] : type[0x32] : seq[?] */
1393 cmd[0] = 0x4 | (ZM_OID_SYNTH << 8);
1394 cmd[1] = value;
1395
1396 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_SYNTH, 0);
1397 return ret;
1398 }
1399
1400 u32_t zfiDbgQueryHwTxBusy(zdev_t* dev)
1401 {
1402 u32_t cmd[1];
1403 u16_t ret;
1404
1405 /* len[4] : type[0xC0] : seq[?] */
1406 cmd[0] = 0 | (ZM_CMD_DKTX_STATUS << 8);
1407
1408 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_DKTX_STATUS, 0);
1409 return ret;
1410 }
1411
1412 //Paul++
1413 #if 0
1414 u16_t zfHpBlockEraseFlash(zdev_t *dev, u32_t addr)
1415 {
1416 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1417 u16_t ret;
1418
1419 cmd[0] = 0x00000004 | (ZM_CMD_FLASH_ERASE << 8);
1420 cmd[1] = addr;
1421
1422 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_INTERNAL_WRITE, NULL);
1423 return ret;
1424 }
1425 #endif
1426
1427 #if 0
1428 u16_t zfiDbgProgramFlash(zdev_t *dev, u32_t offset, u32_t len, u32_t *data)
1429 {
1430 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1431 u16_t ret;
1432 u16_t i;
1433
1434
1435 cmd[0] = (ZM_CMD_FLASH_PROG << 8) | ((len+8) & 0xff);
1436 cmd[1] = offset;
1437 cmd[2] = len;
1438
1439 for (i = 0; i < (len >> 2); i++)
1440 {
1441 cmd[3+i] = data[i];
1442 }
1443
1444 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FLASH_PROGRAM, NULL);
1445
1446 return ret;
1447 }
1448 #endif
1449
1450 /************************************************************************/
1451 /* */
1452 /* FUNCTION DESCRIPTION zfiDbgChipEraseFlash */
1453 /* Chip Erase Flash. */
1454 /* */
1455 /* INPUTS */
1456 /* dev : device pointer */
1457 /* */
1458 /* OUTPUTS */
1459 /* 0 : success */
1460 /* other : fail */
1461 /* */
1462 /* AUTHOR */
1463 /* Paul Atheros Technology Corporation 2007.09 */
1464 /* */
1465 /************************************************************************/
1466 u16_t zfiDbgChipEraseFlash(zdev_t *dev)
1467 {
1468 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1469 u16_t ret;
1470
1471 cmd[0] = 0x00000000 | (ZM_CMD_FLASH_ERASE << 8);
1472
1473 ret = zfIssueCmd(dev, cmd, 4, ZM_OID_INTERNAL_WRITE, NULL);
1474 return ret;
1475 }
1476 /************************************************************************/
1477 /* */
1478 /* FUNCTION DESCRIPTION zfiDbgGetFlashCheckSum */
1479 /* Get FlashCheckSum. */
1480 /* */
1481 /* INPUTS */
1482 /* dev : device pointer */
1483 /* addr : Start address of getchksum */
1484 /* len : total lenth of calculate getchksum */
1485 /* */
1486 /* OUTPUTS */
1487 /* 0 : success */
1488 /* other : fail */
1489 /* */
1490 /* AUTHOR */
1491 /* Paul Atheros Technology Corporation 2007.08 */
1492 /* */
1493 /************************************************************************/
1494 u32_t zfiDbgGetFlashCheckSum(zdev_t *dev, u32_t addr, u32_t len)
1495 {
1496 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1497 u32_t ret;
1498
1499 cmd[0] = 0x00000008 | (ZM_CMD_FLASH_CHKSUM << 8);
1500 cmd[1] = addr;
1501 cmd[2] = len;
1502
1503 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FLASH_CHKSUM, NULL);
1504
1505 return ret;
1506 }
1507
1508 /************************************************************************/
1509 /* */
1510 /* FUNCTION DESCRIPTION zfiDbgReadFlash */
1511 /* Read Flash. */
1512 /* */
1513 /* INPUTS */
1514 /* dev : device pointer */
1515 /* addr : Start address of read flash */
1516 /* len : total lenth of read flash data */
1517 /* */
1518 /* OUTPUTS */
1519 /* 0 : success */
1520 /* other : fail */
1521 /* */
1522 /* AUTHOR */
1523 /* Paul Atheros Technology Corporation 2007.09 */
1524 /* */
1525 /************************************************************************/
1526 u32_t zfiDbgReadFlash(zdev_t *dev, u32_t addr, u32_t len)
1527 {
1528 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1529 u32_t ret;
1530
1531 cmd[0] = len | (ZM_CMD_FLASH_READ << 8);
1532 cmd[1] = addr;
1533
1534 ret = zfIssueCmd(dev, cmd, 8, ZM_OID_FLASH_READ, NULL);
1535 return ret;
1536 }
1537
1538 /************************************************************************/
1539 /* */
1540 /* FUNCTION DESCRIPTION zfiDownloadFwSet */
1541 /* Before Download FW, */
1542 /* Command FW to Software reset and close watch dog control. */
1543 /* */
1544 /* */
1545 /* INPUTS */
1546 /* dev : device pointer */
1547 /* */
1548 /* OUTPUTS */
1549 /* 0 : success */
1550 /* other : fail */
1551 /* */
1552 /* AUTHOR */
1553 /* Paul Atheros Technology Corporation 2007.09 */
1554 /* */
1555 /************************************************************************/
1556 u32_t zfiDownloadFwSet(zdev_t *dev)
1557 {
1558 //softwarereset
1559 //close watch dog
1560 u32_t cmd[(ZM_MAX_CMD_SIZE/4)];
1561 u32_t ret;
1562
1563 cmd[0] = 0x00000008 | (ZM_CMD_FW_DL_INIT << 8);
1564
1565 ret = zfIssueCmd(dev, cmd, 12, ZM_OID_FW_DL_INIT, NULL);
1566
1567 return ret;
1568 }
1569 //Paul--
Linux for Ginger Game Console