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First Support on Ginger and OMAP TI
[linux-ginger.git] / drivers / staging / rt3090 / rtmp_phy.h
blobb9848cac282e055ce4847d686209106ea0f1e7fe
1 /*
2 *************************************************************************
3 * Ralink Tech Inc.
4 * 5F., No.36, Taiyuan St., Jhubei City,
5 * Hsinchu County 302,
6 * Taiwan, R.O.C.
7 *
8 * (c) Copyright 2002-2007, Ralink Technology, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify *
11 * it under the terms of the GNU General Public License as published by *
12 * the Free Software Foundation; either version 2 of the License, or *
13 * (at your option) any later version. *
14 * *
15 * This program is distributed in the hope that it will be useful, *
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
18 * GNU General Public License for more details. *
19 * *
20 * You should have received a copy of the GNU General Public License *
21 * along with this program; if not, write to the *
22 * Free Software Foundation, Inc., *
23 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
24 * *
25 *************************************************************************
26
27 Module Name:
28 rtmp_phy.h
29
30 Abstract:
31 Ralink Wireless Chip PHY(BBP/RF) related definition & structures
32
33 Revision History:
34 Who When What
35 -------- ---------- ----------------------------------------------
36 */
37
38 #ifndef __RTMP_PHY_H__
39 #define __RTMP_PHY_H__
40
41
42 /*
43 RF sections
44 */
45 #define RF_R00 0
46 #define RF_R01 1
47 #define RF_R02 2
48 #define RF_R03 3
49 #define RF_R04 4
50 #define RF_R05 5
51 #define RF_R06 6
52 #define RF_R07 7
53 #define RF_R08 8
54 #define RF_R09 9
55 #define RF_R10 10
56 #define RF_R11 11
57 #define RF_R12 12
58 #define RF_R13 13
59 #define RF_R14 14
60 #define RF_R15 15
61 #define RF_R16 16
62 #define RF_R17 17
63 #define RF_R18 18
64 #define RF_R19 19
65 #define RF_R20 20
66 #define RF_R21 21
67 #define RF_R22 22
68 #define RF_R23 23
69 #define RF_R24 24
70 #define RF_R25 25
71 #define RF_R26 26
72 #define RF_R27 27
73 #define RF_R28 28
74 #define RF_R29 29
75 #define RF_R30 30
76 #define RF_R31 31
77
78
79 // value domain of pAd->RfIcType
80 #define RFIC_2820 1 // 2.4G 2T3R
81 #define RFIC_2850 2 // 2.4G/5G 2T3R
82 #define RFIC_2720 3 // 2.4G 1T2R
83 #define RFIC_2750 4 // 2.4G/5G 1T2R
84 #define RFIC_3020 5 // 2.4G 1T1R
85 #define RFIC_2020 6 // 2.4G B/G
86 #define RFIC_3021 7 // 2.4G 1T2R
87 #define RFIC_3022 8 // 2.4G 2T2R
88 #define RFIC_3052 9 // 2.4G/5G 2T2R
89
90 /*
91 BBP sections
92 */
93 #define BBP_R0 0 // version
94 #define BBP_R1 1 // TSSI
95 #define BBP_R2 2 // TX configure
96 #define BBP_R3 3
97 #define BBP_R4 4
98 #define BBP_R5 5
99 #define BBP_R6 6
100 #define BBP_R14 14 // RX configure
101 #define BBP_R16 16
102 #define BBP_R17 17 // RX sensibility
103 #define BBP_R18 18
104 #define BBP_R21 21
105 #define BBP_R22 22
106 #define BBP_R24 24
107 #define BBP_R25 25
108 #define BBP_R26 26
109 #define BBP_R27 27
110 #define BBP_R31 31
111 #define BBP_R49 49 //TSSI
112 #define BBP_R50 50
113 #define BBP_R51 51
114 #define BBP_R52 52
115 #define BBP_R55 55
116 #define BBP_R62 62 // Rx SQ0 Threshold HIGH
117 #define BBP_R63 63
118 #define BBP_R64 64
119 #define BBP_R65 65
120 #define BBP_R66 66
121 #define BBP_R67 67
122 #define BBP_R68 68
123 #define BBP_R69 69
124 #define BBP_R70 70 // Rx AGC SQ CCK Xcorr threshold
125 #define BBP_R73 73
126 #define BBP_R75 75
127 #define BBP_R77 77
128 #define BBP_R78 78
129 #define BBP_R79 79
130 #define BBP_R80 80
131 #define BBP_R81 81
132 #define BBP_R82 82
133 #define BBP_R83 83
134 #define BBP_R84 84
135 #define BBP_R86 86
136 #define BBP_R91 91
137 #define BBP_R92 92
138 #define BBP_R94 94 // Tx Gain Control
139 #define BBP_R103 103
140 #define BBP_R105 105
141 #define BBP_R106 106
142 #define BBP_R113 113
143 #define BBP_R114 114
144 #define BBP_R115 115
145 #define BBP_R116 116
146 #define BBP_R117 117
147 #define BBP_R118 118
148 #define BBP_R119 119
149 #define BBP_R120 120
150 #define BBP_R121 121
151 #define BBP_R122 122
152 #define BBP_R123 123
153 #ifdef RT30xx
154 #define BBP_R138 138 // add by johnli, RF power sequence setup, ADC dynamic on/off control
155 #endif // RT30xx //
156
157
158 #define BBPR94_DEFAULT 0x06 // Add 1 value will gain 1db
159
160
161 #ifdef MERGE_ARCH_TEAM
162 #define MAX_BBP_ID 200
163 #define MAX_BBP_MSG_SIZE 4096
164 #else
165 #ifdef RT30xx
166 // edit by johnli, RF power sequence setup, add BBP R138 for ADC dynamic on/off control
167 #define MAX_BBP_ID 138
168 #endif // RT30xx //
169 #ifndef RT30xx
170 #define MAX_BBP_ID 136
171 #endif // RT30xx //
172 #define MAX_BBP_MSG_SIZE 2048
173 #endif // MERGE_ARCH_TEAM //
174
175
176 //
177 // BBP & RF are using indirect access. Before write any value into it.
178 // We have to make sure there is no outstanding command pending via checking busy bit.
179 //
180 #define MAX_BUSY_COUNT 100 // Number of retry before failing access BBP & RF indirect register
181
182 //#define PHY_TR_SWITCH_TIME 5 // usec
183
184 //#define BBP_R17_LOW_SENSIBILITY 0x50
185 //#define BBP_R17_MID_SENSIBILITY 0x41
186 //#define BBP_R17_DYNAMIC_UP_BOUND 0x40
187
188 #define RSSI_FOR_VERY_LOW_SENSIBILITY -35
189 #define RSSI_FOR_LOW_SENSIBILITY -58
190 #define RSSI_FOR_MID_LOW_SENSIBILITY -80
191 #define RSSI_FOR_MID_SENSIBILITY -90
192
193 /*****************************************************************************
194 RF register Read/Write marco definition
195 *****************************************************************************/
196 #ifdef RTMP_MAC_PCI
197 #define RTMP_RF_IO_WRITE32(_A, _V) \
198 { \
199 if ((_A)->bPCIclkOff == FALSE) \
200 { \
201 PHY_CSR4_STRUC _value; \
202 ULONG _busyCnt = 0; \
203 \
204 do { \
205 RTMP_IO_READ32((_A), RF_CSR_CFG0, &_value.word); \
206 if (_value.field.Busy == IDLE) \
207 break; \
208 _busyCnt++; \
209 }while (_busyCnt < MAX_BUSY_COUNT); \
210 if(_busyCnt < MAX_BUSY_COUNT) \
211 { \
212 RTMP_IO_WRITE32((_A), RF_CSR_CFG0, (_V)); \
213 } \
214 } \
215 }
216 #endif // RTMP_MAC_PCI //
217
218
219
220 #ifdef RT30xx
221 #define RTMP_RF_IO_READ8_BY_REG_ID(_A, _I, _pV) RT30xxReadRFRegister(_A, _I, _pV)
222 #define RTMP_RF_IO_WRITE8_BY_REG_ID(_A, _I, _V) RT30xxWriteRFRegister(_A, _I, _V)
223 #endif // RT30xx //
224
225
226 /*****************************************************************************
227 BBP register Read/Write marco definitions.
228 we read/write the bbp value by register's ID.
229 Generate PER to test BA
230 *****************************************************************************/
231 #ifdef RTMP_MAC_PCI
232 /*
233 basic marco for BBP read operation.
234 _pAd: the data structure pointer of RTMP_ADAPTER
235 _bbpID : the bbp register ID
236 _pV: data pointer used to save the value of queried bbp register.
237 _bViaMCU: if we need access the bbp via the MCU.
238 */
239 #define RTMP_BBP_IO_READ8(_pAd, _bbpID, _pV, _bViaMCU) \
240 do{ \
241 BBP_CSR_CFG_STRUC BbpCsr; \
242 int _busyCnt, _secCnt, _regID; \
243 \
244 _regID = ((_bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG); \
245 for (_busyCnt=0; _busyCnt<MAX_BUSY_COUNT; _busyCnt++) \
246 { \
247 RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
248 if (BbpCsr.field.Busy == BUSY) \
249 continue; \
250 BbpCsr.word = 0; \
251 BbpCsr.field.fRead = 1; \
252 BbpCsr.field.BBP_RW_MODE = 1; \
253 BbpCsr.field.Busy = 1; \
254 BbpCsr.field.RegNum = _bbpID; \
255 RTMP_IO_WRITE32(_pAd, _regID, BbpCsr.word); \
256 if ((_bViaMCU) == TRUE) \
257 { \
258 AsicSendCommandToMcu(_pAd, 0x80, 0xff, 0x0, 0x0); \
259 RTMPusecDelay(1000); \
260 } \
261 for (_secCnt=0; _secCnt<MAX_BUSY_COUNT; _secCnt++) \
262 { \
263 RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
264 if (BbpCsr.field.Busy == IDLE) \
265 break; \
266 } \
267 if ((BbpCsr.field.Busy == IDLE) && \
268 (BbpCsr.field.RegNum == _bbpID)) \
269 { \
270 *(_pV) = (UCHAR)BbpCsr.field.Value; \
271 break; \
272 } \
273 } \
274 if (BbpCsr.field.Busy == BUSY) \
275 { \
276 DBGPRINT_ERR(("BBP(viaMCU=%d) read R%d fail\n", (_bViaMCU), _bbpID)); \
277 *(_pV) = (_pAd)->BbpWriteLatch[_bbpID]; \
278 if ((_bViaMCU) == TRUE) \
279 { \
280 RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
281 BbpCsr.field.Busy = 0; \
282 RTMP_IO_WRITE32(_pAd, _regID, BbpCsr.word); \
283 } \
284 } \
285 }while(0)
286
287 /*
288 This marco used for the BBP read operation which didn't need via MCU.
289 */
290 #define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
291 RTMP_BBP_IO_READ8((_A), (_I), (_pV), FALSE)
292
293 /*
294 This marco used for the BBP read operation which need via MCU.
295 But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
296 will use this function too and didn't access the bbp register via the MCU.
297 */
298 #ifndef CONFIG_STA_SUPPORT
299 #define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
300 do{ \
301 if ((_A)->bPCIclkOff == FALSE) \
302 { \
303 if ((_A)->infType == RTMP_DEV_INF_RBUS) \
304 RTMP_BBP_IO_READ8((_A), (_I), (_pV), FALSE); \
305 else \
306 RTMP_BBP_IO_READ8((_A), (_I), (_pV), TRUE); \
307 } \
308 }while(0)
309 #endif // CONFIG_STA_SUPPORT //
310 #ifdef CONFIG_STA_SUPPORT
311 // Read BBP register by register's ID. Generate PER to test BA
312 #define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
313 { \
314 BBP_CSR_CFG_STRUC BbpCsr; \
315 int i, k; \
316 BOOLEAN brc; \
317 BbpCsr.field.Busy = IDLE; \
318 if ((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
319 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE) \
320 && ((_A)->bPCIclkOff == FALSE) \
321 && ((_A)->brt30xxBanMcuCmd == FALSE)) \
322 { \
323 for (i=0; i<MAX_BUSY_COUNT; i++) \
324 { \
325 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
326 if (BbpCsr.field.Busy == BUSY) \
327 { \
328 continue; \
329 } \
330 BbpCsr.word = 0; \
331 BbpCsr.field.fRead = 1; \
332 BbpCsr.field.BBP_RW_MODE = 1; \
333 BbpCsr.field.Busy = 1; \
334 BbpCsr.field.RegNum = _I; \
335 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
336 brc = AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
337 if (brc == TRUE) \
338 { \
339 for (k=0; k<MAX_BUSY_COUNT; k++) \
340 { \
341 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
342 if (BbpCsr.field.Busy == IDLE) \
343 break; \
344 } \
345 if ((BbpCsr.field.Busy == IDLE) && \
346 (BbpCsr.field.RegNum == _I)) \
347 { \
348 *(_pV) = (UCHAR)BbpCsr.field.Value; \
349 break; \
350 } \
351 } \
352 else \
353 { \
354 BbpCsr.field.Busy = 0; \
355 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
356 } \
357 } \
358 } \
359 else if (!((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
360 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE)) \
361 && ((_A)->bPCIclkOff == FALSE)) \
362 { \
363 for (i=0; i<MAX_BUSY_COUNT; i++) \
364 { \
365 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
366 if (BbpCsr.field.Busy == BUSY) \
367 { \
368 continue; \
369 } \
370 BbpCsr.word = 0; \
371 BbpCsr.field.fRead = 1; \
372 BbpCsr.field.BBP_RW_MODE = 1; \
373 BbpCsr.field.Busy = 1; \
374 BbpCsr.field.RegNum = _I; \
375 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
376 AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
377 for (k=0; k<MAX_BUSY_COUNT; k++) \
378 { \
379 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
380 if (BbpCsr.field.Busy == IDLE) \
381 break; \
382 } \
383 if ((BbpCsr.field.Busy == IDLE) && \
384 (BbpCsr.field.RegNum == _I)) \
385 { \
386 *(_pV) = (UCHAR)BbpCsr.field.Value; \
387 break; \
388 } \
389 } \
390 } \
391 else \
392 { \
393 DBGPRINT_ERR((" , brt30xxBanMcuCmd = %d, Read BBP %d \n", (_A)->brt30xxBanMcuCmd, (_I))); \
394 *(_pV) = (_A)->BbpWriteLatch[_I]; \
395 } \
396 if ((BbpCsr.field.Busy == BUSY) || ((_A)->bPCIclkOff == TRUE)) \
397 { \
398 DBGPRINT_ERR(("BBP read R%d=0x%x fail\n", _I, BbpCsr.word)); \
399 *(_pV) = (_A)->BbpWriteLatch[_I]; \
400 } \
401 }
402 #endif // CONFIG_STA_SUPPORT //
403
404 /*
405 basic marco for BBP write operation.
406 _pAd: the data structure pointer of RTMP_ADAPTER
407 _bbpID : the bbp register ID
408 _pV: data used to save the value of queried bbp register.
409 _bViaMCU: if we need access the bbp via the MCU.
410 */
411 #define RTMP_BBP_IO_WRITE8(_pAd, _bbpID, _pV, _bViaMCU) \
412 do{ \
413 BBP_CSR_CFG_STRUC BbpCsr; \
414 int _busyCnt, _regID; \
415 \
416 _regID = ((_bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG); \
417 for (_busyCnt=0; _busyCnt<MAX_BUSY_COUNT; _busyCnt++) \
418 { \
419 RTMP_IO_READ32((_pAd), BBP_CSR_CFG, &BbpCsr.word); \
420 if (BbpCsr.field.Busy == BUSY) \
421 continue; \
422 BbpCsr.word = 0; \
423 BbpCsr.field.fRead = 0; \
424 BbpCsr.field.BBP_RW_MODE = 1; \
425 BbpCsr.field.Busy = 1; \
426 BbpCsr.field.Value = _pV; \
427 BbpCsr.field.RegNum = _bbpID; \
428 RTMP_IO_WRITE32((_pAd), BBP_CSR_CFG, BbpCsr.word); \
429 if ((_bViaMCU) == TRUE) \
430 { \
431 AsicSendCommandToMcu(_pAd, 0x80, 0xff, 0x0, 0x0); \
432 if ((_pAd)->OpMode == OPMODE_AP) \
433 RTMPusecDelay(1000); \
434 } \
435 (_pAd)->BbpWriteLatch[_bbpID] = _pV; \
436 break; \
437 } \
438 if (_busyCnt == MAX_BUSY_COUNT) \
439 { \
440 DBGPRINT_ERR(("BBP write R%d fail\n", _bbpID)); \
441 if((_bViaMCU) == TRUE) \
442 { \
443 RTMP_IO_READ32(_pAd, H2M_BBP_AGENT, &BbpCsr.word); \
444 BbpCsr.field.Busy = 0; \
445 RTMP_IO_WRITE32(_pAd, H2M_BBP_AGENT, BbpCsr.word); \
446 } \
447 } \
448 }while(0)
449
450
451 /*
452 This marco used for the BBP write operation which didn't need via MCU.
453 */
454 #define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _pV) \
455 RTMP_BBP_IO_WRITE8((_A), (_I), (_pV), FALSE)
456
457 /*
458 This marco used for the BBP write operation which need via MCU.
459 But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
460 will use this function too and didn't access the bbp register via the MCU.
461 */
462 #ifndef CONFIG_STA_SUPPORT
463 #define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _pV) \
464 do{ \
465 if ((_A)->bPCIclkOff == FALSE) \
466 { \
467 if ((_A)->infType == RTMP_DEV_INF_RBUS) \
468 RTMP_BBP_IO_WRITE8((_A), (_I), (_pV), FALSE); \
469 else \
470 RTMP_BBP_IO_WRITE8((_A), (_I), (_pV), TRUE); \
471 } \
472 }while(0)
473 #endif // CONFIG_STA_SUPPORT //
474 #ifdef CONFIG_STA_SUPPORT
475 // Write BBP register by register's ID & value
476 #define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) \
477 { \
478 BBP_CSR_CFG_STRUC BbpCsr; \
479 INT BusyCnt = 0; \
480 BOOLEAN brc; \
481 if (_I < MAX_NUM_OF_BBP_LATCH) \
482 { \
483 if ((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
484 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE) \
485 && ((_A)->bPCIclkOff == FALSE) \
486 && ((_A)->brt30xxBanMcuCmd == FALSE)) \
487 { \
488 if (_A->AccessBBPFailCount > 20) \
489 { \
490 AsicResetBBPAgent(_A); \
491 _A->AccessBBPFailCount = 0; \
492 } \
493 for (BusyCnt=0; BusyCnt<MAX_BUSY_COUNT; BusyCnt++) \
494 { \
495 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
496 if (BbpCsr.field.Busy == BUSY) \
497 continue; \
498 BbpCsr.word = 0; \
499 BbpCsr.field.fRead = 0; \
500 BbpCsr.field.BBP_RW_MODE = 1; \
501 BbpCsr.field.Busy = 1; \
502 BbpCsr.field.Value = _V; \
503 BbpCsr.field.RegNum = _I; \
504 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
505 brc = AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
506 if (brc == TRUE) \
507 { \
508 (_A)->BbpWriteLatch[_I] = _V; \
509 } \
510 else \
511 { \
512 BbpCsr.field.Busy = 0; \
513 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
514 } \
515 break; \
516 } \
517 } \
518 else if (!((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
519 && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE)) \
520 && ((_A)->bPCIclkOff == FALSE)) \
521 { \
522 if (_A->AccessBBPFailCount > 20) \
523 { \
524 AsicResetBBPAgent(_A); \
525 _A->AccessBBPFailCount = 0; \
526 } \
527 for (BusyCnt=0; BusyCnt<MAX_BUSY_COUNT; BusyCnt++) \
528 { \
529 RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
530 if (BbpCsr.field.Busy == BUSY) \
531 continue; \
532 BbpCsr.word = 0; \
533 BbpCsr.field.fRead = 0; \
534 BbpCsr.field.BBP_RW_MODE = 1; \
535 BbpCsr.field.Busy = 1; \
536 BbpCsr.field.Value = _V; \
537 BbpCsr.field.RegNum = _I; \
538 RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
539 AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
540 (_A)->BbpWriteLatch[_I] = _V; \
541 break; \
542 } \
543 } \
544 else \
545 { \
546 DBGPRINT_ERR((" brt30xxBanMcuCmd = %d. Write BBP %d \n", (_A)->brt30xxBanMcuCmd, (_I))); \
547 } \
548 if ((BusyCnt == MAX_BUSY_COUNT) || ((_A)->bPCIclkOff == TRUE)) \
549 { \
550 if (BusyCnt == MAX_BUSY_COUNT) \
551 (_A)->AccessBBPFailCount++; \
552 DBGPRINT_ERR(("BBP write R%d=0x%x fail. BusyCnt= %d.bPCIclkOff = %d. \n", _I, BbpCsr.word, BusyCnt, (_A)->bPCIclkOff )); \
553 } \
554 } \
555 else \
556 { \
557 DBGPRINT_ERR(("****** BBP_Write_Latch Buffer exceeds max boundry ****** \n")); \
558 } \
559 }
560 #endif // CONFIG_STA_SUPPORT //
561 #endif // RTMP_MAC_PCI //
562
563
564
565 #ifdef RT30xx
566 //Need to collect each ant's rssi concurrently
567 //rssi1 is report to pair2 Ant and rss2 is reprot to pair1 Ant when 4 Ant
568 #define COLLECT_RX_ANTENNA_AVERAGE_RSSI(_pAd, _rssi1, _rssi2) \
569 { \
570 SHORT AvgRssi; \
571 UCHAR UsedAnt; \
572 if (_pAd->RxAnt.EvaluatePeriod == 0) \
573 { \
574 UsedAnt = _pAd->RxAnt.Pair1PrimaryRxAnt; \
575 AvgRssi = _pAd->RxAnt.Pair1AvgRssi[UsedAnt]; \
576 if (AvgRssi < 0) \
577 AvgRssi = AvgRssi - (AvgRssi >> 3) + _rssi1; \
578 else \
579 AvgRssi = _rssi1 << 3; \
580 _pAd->RxAnt.Pair1AvgRssi[UsedAnt] = AvgRssi; \
581 } \
582 else \
583 { \
584 UsedAnt = _pAd->RxAnt.Pair1SecondaryRxAnt; \
585 AvgRssi = _pAd->RxAnt.Pair1AvgRssi[UsedAnt]; \
586 if ((AvgRssi < 0) && (_pAd->RxAnt.FirstPktArrivedWhenEvaluate)) \
587 AvgRssi = AvgRssi - (AvgRssi >> 3) + _rssi1; \
588 else \
589 { \
590 _pAd->RxAnt.FirstPktArrivedWhenEvaluate = TRUE; \
591 AvgRssi = _rssi1 << 3; \
592 } \
593 _pAd->RxAnt.Pair1AvgRssi[UsedAnt] = AvgRssi; \
594 _pAd->RxAnt.RcvPktNumWhenEvaluate++; \
595 } \
596 }
597
598 #define RTMP_ASIC_MMPS_DISABLE(_pAd) \
599 do{ \
600 UCHAR _bbpData; \
601 UINT32 _macData; \
602 /* disable MMPS BBP control register */ \
603 RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
604 _bbpData &= ~(0x04); /*bit 2*/ \
605 RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
606 \
607 /* disable MMPS MAC control register */ \
608 RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
609 _macData &= ~(0x09); /*bit 0, 3*/ \
610 RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
611 }while(0)
612
613
614 #define RTMP_ASIC_MMPS_ENABLE(_pAd) \
615 do{ \
616 UCHAR _bbpData; \
617 UINT32 _macData; \
618 /* enable MMPS BBP control register */ \
619 RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
620 _bbpData |= (0x04); /*bit 2*/ \
621 RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
622 \
623 /* enable MMPS MAC control register */ \
624 RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
625 _macData |= (0x09); /*bit 0, 3*/ \
626 RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
627 }while(0)
628
629 #endif // RT30xx //
630
631 #endif // __RTMP_PHY_H__ //
Linux for Ginger Game Console