drivers/staging/rtl8192e/r8192E_hw.h

   1 /*
   2         This is part of rtl8187 OpenSource driver.
   3         Copyright (C) Andrea Merello 2004-2005  <andreamrl@tiscali.it>
   4         Released under the terms of GPL (General Public Licence)
   5
   6         Parts of this driver are based on the GPL part of the
   7         official Realtek driver.
   8         Parts of this driver are based on the rtl8180 driver skeleton
   9         from Patric Schenke & Andres Salomon.
  10         Parts of this driver are based on the Intel Pro Wireless
  11         2100 GPL driver.
  12
  13         We want to tanks the Authors of those projects
  14         and the Ndiswrapper project Authors.
  15 */
  16
  17 /* Mariusz Matuszek added full registers definition with Realtek's name */
  18
  19 /* this file contains register definitions for the rtl8187 MAC controller */
  20 #ifndef R8180_HW
  21 #define R8180_HW
  22
  23 typedef enum _VERSION_8190{
  24         // RTL8190
  25         VERSION_8190_BD=0x3,
  26         VERSION_8190_BE
  27 }VERSION_8190,*PVERSION_8190;
  28 //added for different RF type
  29 typedef enum _RT_RF_TYPE_DEF
  30 {
  31         RF_1T2R = 0,
  32         RF_2T4R,
  33
  34         RF_819X_MAX_TYPE
  35 }RT_RF_TYPE_DEF;
  36
  37 typedef enum _BaseBand_Config_Type{
  38         BaseBand_Config_PHY_REG = 0,                    //Radio Path A
  39         BaseBand_Config_AGC_TAB = 1,                    //Radio Path B
  40 }BaseBand_Config_Type, *PBaseBand_Config_Type;
  41 #if 0
  42 typedef enum _RT_RF_TYPE_819xU{
  43         RF_TYPE_MIN = 0,
  44         RF_8225,
  45         RF_8256,
  46         RF_8258,
  47         RF_PSEUDO_11N = 4,
  48 }RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
  49 #endif
  50 #define RTL8187_REQT_READ       0xc0
  51 #define RTL8187_REQT_WRITE      0x40
  52 #define RTL8187_REQ_GET_REGS    0x05
  53 #define RTL8187_REQ_SET_REGS    0x05
  54
  55 #define R8180_MAX_RETRY 255
  56 #define MAX_TX_URB 5
  57 #define MAX_RX_URB 16
  58 //#define MAX_RX_NORMAL_URB 3
  59 //#define MAX_RX_COMMAND_URB 2
  60 #define RX_URB_SIZE 9100
  61
  62 #define BB_ANTATTEN_CHAN14      0x0c
  63 #define BB_ANTENNA_B 0x40
  64
  65 #define BB_HOST_BANG (1<<30)
  66 #define BB_HOST_BANG_EN (1<<2)
  67 #define BB_HOST_BANG_CLK (1<<1)
  68 #define BB_HOST_BANG_RW (1<<3)
  69 #define BB_HOST_BANG_DATA        1
  70
  71 //#if (RTL819X_FPGA_VER & RTL819X_FPGA_VIVI_070920)
  72 #define RTL8190_EEPROM_ID       0x8129
  73 #define EEPROM_VID              0x02
  74 #define EEPROM_DID              0x04
  75 #define EEPROM_NODE_ADDRESS_BYTE_0      0x0C
  76
  77 #define EEPROM_TxPowerDiff      0x1F
  78
  79
  80 #define EEPROM_PwDiff           0x21    //0x21
  81 #define EEPROM_CrystalCap       0x22    //0x22
  82
  83
  84
  85 #define EEPROM_TxPwIndex_CCK_V1         0x29    //0x29~0x2B
  86 #define EEPROM_TxPwIndex_OFDM_24G_V1    0x2C    //0x2C~0x2E
  87 #define EEPROM_TxPwIndex_Ver            0x27    //0x27
  88
  89 #define EEPROM_Default_TxPowerDiff              0x0
  90 #define EEPROM_Default_ThermalMeter             0x77
  91 #define EEPROM_Default_AntTxPowerDiff           0x0
  92 #define EEPROM_Default_TxPwDiff_CrystalCap      0x5
  93 #define EEPROM_Default_PwDiff                   0x4
  94 #define EEPROM_Default_CrystalCap               0x5
  95 #define EEPROM_Default_TxPower                  0x1010
  96 #define EEPROM_ICVersion_ChannelPlan    0x7C    //0x7C:ChannelPlan, 0x7D:IC_Version
  97 #define EEPROM_Customer_ID                      0x7B    //0x7B:CustomerID
  98 #ifdef RTL8190P
  99 #define EEPROM_RFInd_PowerDiff                  0x14
 100 #define EEPROM_ThermalMeter                     0x15
 101 #define EEPROM_TxPwDiff_CrystalCap              0x16
 102 #define EEPROM_TxPwIndex_CCK                    0x18    //0x18~0x25
 103 #define EEPROM_TxPwIndex_OFDM_24G       0x26    //0x26~0x33
 104 #define EEPROM_TxPwIndex_OFDM_5G                0x34    //0x34~0x7B
 105 #define EEPROM_C56_CrystalCap                   0x17    //0x17
 106 #define EEPROM_C56_RfA_CCK_Chnl1_TxPwIndex      0x80    //0x80
 107 #define EEPROM_C56_RfA_HT_OFDM_TxPwIndex        0x81    //0x81~0x83
 108 #define EEPROM_C56_RfC_CCK_Chnl1_TxPwIndex      0xbc    //0xb8
 109 #define EEPROM_C56_RfC_HT_OFDM_TxPwIndex        0xb9    //0xb9~0xbb
 110 #else
 111 #ifdef RTL8192E
 112 #define EEPROM_RFInd_PowerDiff                  0x28
 113 #define EEPROM_ThermalMeter                     0x29
 114 #define EEPROM_TxPwDiff_CrystalCap              0x2A    //0x2A~0x2B
 115 #define EEPROM_TxPwIndex_CCK                    0x2C    //0x23
 116 #define EEPROM_TxPwIndex_OFDM_24G       0x3A    //0x24~0x26
 117 #endif
 118 #endif
 119 #define EEPROM_Default_TxPowerLevel             0x10
 120 //#define EEPROM_ChannelPlan                    0x7c    //0x7C
 121 #define EEPROM_IC_VER                           0x7d    //0x7D
 122 #define EEPROM_CRC                              0x7e    //0x7E~0x7F
 123
 124 #define EEPROM_CID_DEFAULT                      0x0
 125 #define EEPROM_CID_CAMEO                                0x1
 126 #define EEPROM_CID_RUNTOP                               0x2
 127 #define EEPROM_CID_Senao                                0x3
 128 #define EEPROM_CID_TOSHIBA                              0x4     // Toshiba setting, Merge by Jacken, 2008/01/31
 129 #define EEPROM_CID_NetCore                              0x5
 130 #define EEPROM_CID_Nettronix                    0x6
 131 #define EEPROM_CID_Pronet                               0x7
 132 #define EEPROM_CID_DLINK                                0x8
 133 #define EEPROM_CID_WHQL                                 0xFE  //added by sherry for dtm, 20080728
 134 //#endif
 135 enum _RTL8192Pci_HW {
 136         MAC0                    = 0x000,
 137         MAC1                    = 0x001,
 138         MAC2                    = 0x002,
 139         MAC3                    = 0x003,
 140         MAC4                    = 0x004,
 141         MAC5                    = 0x005,
 142         PCIF                    = 0x009, // PCI Function Register 0x0009h~0x000bh
 143 //----------------------------------------------------------------------------
 144 //       8190 PCIF bits                                                 (Offset 0x009-000b, 24bit)
 145 //----------------------------------------------------------------------------
 146 #define MXDMA2_16bytes          0x000
 147 #define MXDMA2_32bytes          0x001
 148 #define MXDMA2_64bytes          0x010
 149 #define MXDMA2_128bytes         0x011
 150 #define MXDMA2_256bytes         0x100
 151 #define MXDMA2_512bytes         0x101
 152 #define MXDMA2_1024bytes        0x110
 153 #define MXDMA2_NoLimit          0x7
 154
 155 #define MULRW_SHIFT             3
 156 #define MXDMA2_RX_SHIFT         4
 157 #define MXDMA2_TX_SHIFT         0
 158         PMR                     = 0x00c, // Power management register
 159         EPROM_CMD               = 0x00e,
 160 #define EPROM_CMD_RESERVED_MASK BIT5
 161 #define EPROM_CMD_9356SEL       BIT4
 162 #define EPROM_CMD_OPERATING_MODE_SHIFT 6
 163 #define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6))
 164 #define EPROM_CMD_CONFIG 0x3
 165 #define EPROM_CMD_NORMAL 0
 166 #define EPROM_CMD_LOAD 1
 167 #define EPROM_CMD_PROGRAM 2
 168 #define EPROM_CS_SHIFT 3
 169 #define EPROM_CK_SHIFT 2
 170 #define EPROM_W_SHIFT 1
 171 #define EPROM_R_SHIFT 0
 172
 173         AFR                      = 0x010,
 174 #define AFR_CardBEn             (1<<0)
 175 #define AFR_CLKRUN_SEL          (1<<1)
 176 #define AFR_FuncRegEn           (1<<2)
 177
 178         ANAPAR                  = 0x17,
 179 #define BB_GLOBAL_RESET_BIT     0x1
 180         BB_GLOBAL_RESET         = 0x020, // BasebandGlobal Reset Register
 181         BSSIDR                  = 0x02E, // BSSID Register
 182         CMDR                    = 0x037, // Command register
 183 #define         CR_RST                                  0x10
 184 #define         CR_RE                                   0x08
 185 #define         CR_TE                                   0x04
 186 #define         CR_MulRW                                0x01
 187         SIFS            = 0x03E,        // SIFS register
 188         TCR                     = 0x040, // Transmit Configuration Register
 189         RCR                     = 0x044, // Receive Configuration Register
 190 //----------------------------------------------------------------------------
 191 ////       8190 (RCR) Receive Configuration Register    (Offset 0x44~47, 32 bit)
 192 ////----------------------------------------------------------------------------
 193 #define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
 194 #define RCR_ONLYERLPKT          BIT31                   // Early Receiving based on Packet Size.
 195 #define RCR_ENCS2               BIT30                           // Enable Carrier Sense Detection Method 2
 196 #define RCR_ENCS1               BIT29                           // Enable Carrier Sense Detection Method 1
 197 #define RCR_ENMBID              BIT27                           // Enable Multiple BssId.
 198 #define RCR_ACKTXBW             (BIT24|BIT25)           // TXBW Setting of ACK frames
 199 #define RCR_CBSSID              BIT23                           // Accept BSSID match packet
 200 #define RCR_APWRMGT             BIT22                           // Accept power management packet
 201 #define RCR_ADD3                BIT21                   // Accept address 3 match packet
 202 #define RCR_AMF                 BIT20                           // Accept management type frame
 203 #define RCR_ACF                 BIT19                           // Accept control type frame
 204 #define RCR_ADF                 BIT18                           // Accept data type frame
 205 #define RCR_RXFTH               BIT13   // Rx FIFO Threshold
 206 #define RCR_AICV                BIT12                           // Accept ICV error packet
 207 #define RCR_ACRC32              BIT5                    // Accept CRC32 error packet
 208 #define RCR_AB                  BIT3                    // Accept broadcast packet
 209 #define RCR_AM                  BIT2                    // Accept multicast packet
 210 #define RCR_APM                 BIT1                    // Accept physical match packet
 211 #define RCR_AAP                 BIT0                    // Accept all unicast packet
 212 #define RCR_MXDMA_OFFSET        8
 213 #define RCR_FIFO_OFFSET         13
 214         SLOT_TIME               = 0x049, // Slot Time Register
 215         ACK_TIMEOUT             = 0x04c, // Ack Timeout Register
 216         PIFS_TIME               = 0x04d, // PIFS time
 217         USTIME                  = 0x04e, // Microsecond Tuning Register, Sets the microsecond time unit used by MAC clock.
 218         EDCAPARA_BE             = 0x050, // EDCA Parameter of AC BE
 219         EDCAPARA_BK             = 0x054, // EDCA Parameter of AC BK
 220         EDCAPARA_VO             = 0x058, // EDCA Parameter of AC VO
 221         EDCAPARA_VI             = 0x05C, // EDCA Parameter of AC VI
 222 #define AC_PARAM_TXOP_LIMIT_OFFSET              16
 223 #define AC_PARAM_ECW_MAX_OFFSET         12
 224 #define AC_PARAM_ECW_MIN_OFFSET                 8
 225 #define AC_PARAM_AIFS_OFFSET                            0
 226         RFPC                    = 0x05F, // Rx FIFO Packet Count
 227         CWRR                    = 0x060, // Contention Window Report Register
 228         BCN_TCFG                = 0x062, // Beacon Time Configuration
 229 #define BCN_TCFG_CW_SHIFT               8
 230 #define BCN_TCFG_IFS                    0
 231         BCN_INTERVAL            = 0x070, // Beacon Interval (TU)
 232         ATIMWND                 = 0x072, // ATIM Window Size (TU)
 233         BCN_DRV_EARLY_INT       = 0x074, // Driver Early Interrupt Time (TU). Time to send interrupt to notify to change beacon content before TBTT
 234 #define BCN_DRV_EARLY_INT_SWBCN_SHIFT   8
 235 #define BCN_DRV_EARLY_INT_TIME_SHIFT    0
 236         BCN_DMATIME             = 0x076, // Beacon DMA and ATIM interrupt time (US). Indicates the time before TBTT to perform beacon queue DMA
 237         BCN_ERR_THRESH          = 0x078, // Beacon Error Threshold
 238         RWCAM                   = 0x0A0, //IN 8190 Data Sheet is called CAMcmd
 239         //----------------------------------------------------------------------------
 240         ////       8190 CAM Command Register                    (offset 0xA0, 4 byte)
 241         ////----------------------------------------------------------------------------
 242 #define   CAM_CM_SecCAMPolling          BIT31           //Security CAM Polling
 243 #define   CAM_CM_SecCAMClr                      BIT30           //Clear all bits in CAM
 244 #define   CAM_CM_SecCAMWE                       BIT16           //Security CAM enable
 245 #define   CAM_VALID                            BIT15
 246 #define   CAM_NOTVALID                  0x0000
 247 #define   CAM_USEDK                             BIT5
 248
 249 #define   CAM_NONE                              0x0
 250 #define   CAM_WEP40                             0x01
 251 #define   CAM_TKIP                              0x02
 252 #define   CAM_AES                               0x04
 253 #define   CAM_WEP104                    0x05
 254
 255 #define   TOTAL_CAM_ENTRY                               32
 256
 257 #define   CAM_CONFIG_USEDK      true
 258 #define   CAM_CONFIG_NO_USEDK   false
 259 #define   CAM_WRITE             BIT16
 260 #define   CAM_READ              0x00000000
 261 #define   CAM_POLLINIG          BIT31
 262 #define   SCR_UseDK             0x01
 263         WCAMI                   = 0x0A4, // Software write CAM input content
 264         RCAMO                   = 0x0A8, // Software read/write CAM config
 265         SECR                    = 0x0B0, //Security Configuration Register
 266 #define SCR_TxUseDK                     BIT0                    //Force Tx Use Default Key
 267 #define   SCR_RxUseDK                   BIT1                    //Force Rx Use Default Key
 268 #define   SCR_TxEncEnable               BIT2                    //Enable Tx Encryption
 269 #define   SCR_RxDecEnable               BIT3                    //Enable Rx Decryption
 270 #define   SCR_SKByA2                            BIT4                    //Search kEY BY A2
 271 #define   SCR_NoSKMC                            BIT5                    //No Key Search for Multicast
 272         SWREGULATOR     = 0x0BD,        // Switching Regulator
 273         INTA_MASK               = 0x0f4,
 274 //----------------------------------------------------------------------------
 275 //       8190 IMR/ISR bits                                              (offset 0xfd,  8bits)
 276 //----------------------------------------------------------------------------
 277 #define IMR8190_DISABLED                0x0
 278 #define IMR_ATIMEND                     BIT28                   // ATIM Window End Interrupt
 279 #define IMR_TBDOK                       BIT27                   // Transmit Beacon OK Interrupt
 280 #define IMR_TBDER                       BIT26                   // Transmit Beacon Error Interrupt
 281 #define IMR_TXFOVW                      BIT15                   // Transmit FIFO Overflow
 282 #define IMR_TIMEOUT0                    BIT14                   // TimeOut0
 283 #define IMR_BcnInt                      BIT13                   // Beacon DMA Interrupt 0
 284 #define IMR_RXFOVW                      BIT12                   // Receive FIFO Overflow
 285 #define IMR_RDU                         BIT11                   // Receive Descriptor Unavailable
 286 #define IMR_RXCMDOK                     BIT10                   // Receive Command Packet OK
 287 #define IMR_BDOK                        BIT9                    // Beacon Queue DMA OK Interrup
 288 #define IMR_HIGHDOK                     BIT8                    // High Queue DMA OK Interrupt
 289 #define IMR_COMDOK                      BIT7                    // Command Queue DMA OK Interrupt
 290 #define IMR_MGNTDOK                     BIT6                    // Management Queue DMA OK Interrupt
 291 #define IMR_HCCADOK                     BIT5                    // HCCA Queue DMA OK Interrupt
 292 #define IMR_BKDOK                       BIT4                    // AC_BK DMA OK Interrupt
 293 #define IMR_BEDOK                       BIT3                    // AC_BE DMA OK Interrupt
 294 #define IMR_VIDOK                       BIT2                    // AC_VI DMA OK Interrupt
 295 #define IMR_VODOK                       BIT1                    // AC_VO DMA Interrupt
 296 #define IMR_ROK                         BIT0                    // Receive DMA OK Interrupt
 297         ISR                     = 0x0f8, // Interrupt Status Register
 298         TPPoll                  = 0x0fd, // Transmit priority polling register
 299 #define TPPoll_BKQ              BIT0                            // BK queue polling
 300 #define TPPoll_BEQ              BIT1                            // BE queue polling
 301 #define TPPoll_VIQ              BIT2                            // VI queue polling
 302 #define TPPoll_VOQ              BIT3                            // VO queue polling
 303 #define TPPoll_BQ               BIT4                            // Beacon queue polling
 304 #define TPPoll_CQ               BIT5                            // Command queue polling
 305 #define TPPoll_MQ               BIT6                            // Management queue polling
 306 #define TPPoll_HQ               BIT7                            // High queue polling
 307 #define TPPoll_HCCAQ            BIT8                            // HCCA queue polling
 308 #define TPPoll_StopBK   BIT9                            // Stop BK queue
 309 #define TPPoll_StopBE   BIT10                   // Stop BE queue
 310 #define TPPoll_StopVI           BIT11                   // Stop VI queue
 311 #define TPPoll_StopVO   BIT12                   // Stop VO queue
 312 #define TPPoll_StopMgt  BIT13                   // Stop Mgnt queue
 313 #define TPPoll_StopHigh BIT14                   // Stop High queue
 314 #define TPPoll_StopHCCA BIT15                   // Stop HCCA queue
 315 #define TPPoll_SHIFT            8                               // Queue ID mapping
 316
 317         PSR                     = 0x0ff, // Page Select Register
 318 #define PSR_GEN                 0x0                             // Page 0 register general MAC Control
 319 #define PSR_CPU                 0x1                             // Page 1 register for CPU
 320         CPU_GEN                 = 0x100, // CPU Reset Register
 321         BB_RESET                        = 0x101, // Baseband Reset
 322 //----------------------------------------------------------------------------
 323 //       8190 CPU General Register              (offset 0x100, 4 byte)
 324 //----------------------------------------------------------------------------
 325 #define CPU_CCK_LOOPBACK        0x00030000
 326 #define CPU_GEN_SYSTEM_RESET    0x00000001
 327 #define CPU_GEN_FIRMWARE_RESET  0x00000008
 328 #define CPU_GEN_BOOT_RDY        0x00000010
 329 #define CPU_GEN_FIRM_RDY        0x00000020
 330 #define CPU_GEN_PUT_CODE_OK     0x00000080
 331 #define CPU_GEN_BB_RST          0x00000100
 332 #define CPU_GEN_PWR_STB_CPU     0x00000004
 333 #define CPU_GEN_NO_LOOPBACK_MSK 0xFFF8FFFF // Set bit18,17,16 to 0. Set bit19
 334 #define CPU_GEN_NO_LOOPBACK_SET 0x00080000 // Set BIT19 to 1
 335 #define CPU_GEN_GPIO_UART               0x00007000
 336
 337         LED1Cfg                 = 0x154,// LED1 Configuration Register
 338         LED0Cfg                 = 0x155,// LED0 Configuration Register
 339
 340         AcmAvg                  = 0x170, // ACM Average Period Register
 341         AcmHwCtrl               = 0x171, // ACM Hardware Control Register
 342 //----------------------------------------------------------------------------
 343 //
 344 //       8190 AcmHwCtrl bits                                    (offset 0x171, 1 byte)
 345 //----------------------------------------------------------------------------
 346 #define AcmHw_HwEn              BIT0
 347 #define AcmHw_BeqEn             BIT1
 348 #define AcmHw_ViqEn             BIT2
 349 #define AcmHw_VoqEn             BIT3
 350 #define AcmHw_BeqStatus         BIT4
 351 #define AcmHw_ViqStatus         BIT5
 352 #define AcmHw_VoqStatus         BIT6
 353         AcmFwCtrl               = 0x172, // ACM Firmware Control Register
 354 #define AcmFw_BeqStatus         BIT0
 355 #define AcmFw_ViqStatus         BIT1
 356 #define AcmFw_VoqStatus         BIT2
 357         VOAdmTime               = 0x174, // VO Queue Admitted Time Register
 358         VIAdmTime               = 0x178, // VI Queue Admitted Time Register
 359         BEAdmTime               = 0x17C, // BE Queue Admitted Time Register
 360         RQPN1                   = 0x180, // Reserved Queue Page Number , Vo Vi, Be, Bk
 361         RQPN2                   = 0x184, // Reserved Queue Page Number, HCCA, Cmd, Mgnt, High
 362         RQPN3                   = 0x188, // Reserved Queue Page Number, Bcn, Public,
 363         QPRR                    = 0x1E0, // Queue Page Report per TID
 364         QPNR                    = 0x1F0, // Queue Packet Number report per TID
 365 /* there's 9 tx descriptor base address available */
 366         BQDA                    = 0x200, // Beacon Queue Descriptor Address
 367         HQDA                    = 0x204, // High Priority Queue Descriptor Address
 368         CQDA                    = 0x208, // Command Queue Descriptor Address
 369         MQDA                    = 0x20C, // Management Queue Descriptor Address
 370         HCCAQDA                 = 0x210, // HCCA Queue Descriptor Address
 371         VOQDA                   = 0x214, // VO Queue Descriptor Address
 372         VIQDA                   = 0x218, // VI Queue Descriptor Address
 373         BEQDA                   = 0x21C, // BE Queue Descriptor Address
 374         BKQDA                   = 0x220, // BK Queue Descriptor Address
 375 /* there's 2 rx descriptor base address availalbe */
 376         RCQDA                   = 0x224, // Receive command Queue Descriptor Address
 377         RDQDA                   = 0x228, // Receive Queue Descriptor Start Address
 378
 379         MAR0                    = 0x240, // Multicast filter.
 380         MAR4                    = 0x244,
 381
 382         CCX_PERIOD              = 0x250, // CCX Measurement Period Register, in unit of TU.
 383         CLM_RESULT              = 0x251, // CCA Busy fraction register.
 384         NHM_PERIOD              = 0x252, // NHM Measurement Period register, in unit of TU.
 385
 386         NHM_THRESHOLD0          = 0x253, // Noise Histogram Meashorement0.
 387         NHM_THRESHOLD1          = 0x254, // Noise Histogram Meashorement1.
 388         NHM_THRESHOLD2          = 0x255, // Noise Histogram Meashorement2.
 389         NHM_THRESHOLD3          = 0x256, // Noise Histogram Meashorement3.
 390         NHM_THRESHOLD4          = 0x257, // Noise Histogram Meashorement4.
 391         NHM_THRESHOLD5          = 0x258, // Noise Histogram Meashorement5.
 392         NHM_THRESHOLD6          = 0x259, // Noise Histogram Meashorement6
 393
 394         MCTRL                   = 0x25A, // Measurement Control
 395
 396         NHM_RPI_COUNTER0        = 0x264, // Noise Histogram RPI counter0, the fraction of signal strength < NHM_THRESHOLD0.
 397         NHM_RPI_COUNTER1        = 0x265, // Noise Histogram RPI counter1, the fraction of signal strength in (NHM_THRESHOLD0, NHM_THRESHOLD1].
 398         NHM_RPI_COUNTER2        = 0x266, // Noise Histogram RPI counter2, the fraction of signal strength in (NHM_THRESHOLD1, NHM_THRESHOLD2].
 399         NHM_RPI_COUNTER3        = 0x267, // Noise Histogram RPI counter3, the fraction of signal strength in (NHM_THRESHOLD2, NHM_THRESHOLD3].
 400         NHM_RPI_COUNTER4        = 0x268, // Noise Histogram RPI counter4, the fraction of signal strength in (NHM_THRESHOLD3, NHM_THRESHOLD4].
 401         NHM_RPI_COUNTER5        = 0x269, // Noise Histogram RPI counter5, the fraction of signal strength in (NHM_THRESHOLD4, NHM_THRESHOLD5].
 402         NHM_RPI_COUNTER6        = 0x26A, // Noise Histogram RPI counter6, the fraction of signal strength in (NHM_THRESHOLD5, NHM_THRESHOLD6].
 403         NHM_RPI_COUNTER7        = 0x26B, // Noise Histogram RPI counter7, the fraction of signal strength in (NHM_THRESHOLD6, NHM_THRESHOLD7].
 404         WFCRC0                  = 0x2f0,
 405         WFCRC1                  = 0x2f4,
 406         WFCRC2                  = 0x2f8,
 407
 408         BW_OPMODE               = 0x300, // Bandwidth operation mode
 409 #define BW_OPMODE_11J                   BIT0
 410 #define BW_OPMODE_5G                    BIT1
 411 #define BW_OPMODE_20MHZ                 BIT2
 412         IC_VERRSION             = 0x301,        //IC_VERSION
 413         MSR                     = 0x303, // Media Status register
 414 #define MSR_LINK_MASK      ((1<<0)|(1<<1))
 415 #define MSR_LINK_MANAGED   2
 416 #define MSR_LINK_NONE      0
 417 #define MSR_LINK_SHIFT     0
 418 #define MSR_LINK_ADHOC     1
 419 #define MSR_LINK_MASTER    3
 420 #define MSR_LINK_ENEDCA    (1<<4)
 421         RETRY_LIMIT             = 0x304, // Retry Limit [15:8]-short, [7:0]-long
 422 #define RETRY_LIMIT_SHORT_SHIFT 8
 423 #define RETRY_LIMIT_LONG_SHIFT 0
 424         TSFR                    = 0x308,
 425         RRSR                    = 0x310, // Response Rate Set
 426 #define RRSR_RSC_OFFSET                 21
 427 #define RRSR_SHORT_OFFSET                       23
 428 #define RRSR_RSC_DUPLICATE                      0x600000
 429 #define RRSR_RSC_UPSUBCHNL                      0x400000
 430 #define RRSR_RSC_LOWSUBCHNL             0x200000
 431 #define RRSR_SHORT                                      0x800000
 432 #define RRSR_1M                                         BIT0
 433 #define RRSR_2M                                         BIT1
 434 #define RRSR_5_5M                                       BIT2
 435 #define RRSR_11M                                        BIT3
 436 #define RRSR_6M                                         BIT4
 437 #define RRSR_9M                                         BIT5
 438 #define RRSR_12M                                        BIT6
 439 #define RRSR_18M                                        BIT7
 440 #define RRSR_24M                                        BIT8
 441 #define RRSR_36M                                        BIT9
 442 #define RRSR_48M                                        BIT10
 443 #define RRSR_54M                                        BIT11
 444 #define RRSR_MCS0                                       BIT12
 445 #define RRSR_MCS1                                       BIT13
 446 #define RRSR_MCS2                                       BIT14
 447 #define RRSR_MCS3                                       BIT15
 448 #define RRSR_MCS4                                       BIT16
 449 #define RRSR_MCS5                                       BIT17
 450 #define RRSR_MCS6                                       BIT18
 451 #define RRSR_MCS7                                       BIT19
 452 #define BRSR_AckShortPmb                        BIT23           // CCK ACK: use Short Preamble or not
 453         UFWP                    = 0x318,
 454         RATR0                   = 0x320, // Rate Adaptive Table register1
 455 //----------------------------------------------------------------------------
 456 //       8190 Rate Adaptive Table Register      (offset 0x320, 4 byte)
 457 //----------------------------------------------------------------------------
 458 //CCK
 459 #define RATR_1M                 0x00000001
 460 #define RATR_2M                 0x00000002
 461 #define RATR_55M                0x00000004
 462 #define RATR_11M                0x00000008
 463 //OFDM
 464 #define RATR_6M                 0x00000010
 465 #define RATR_9M                 0x00000020
 466 #define RATR_12M                0x00000040
 467 #define RATR_18M                0x00000080
 468 #define RATR_24M                0x00000100
 469 #define RATR_36M                0x00000200
 470 #define RATR_48M                0x00000400
 471 #define RATR_54M                0x00000800
 472 //MCS 1 Spatial Stream
 473 #define RATR_MCS0               0x00001000
 474 #define RATR_MCS1               0x00002000
 475 #define RATR_MCS2               0x00004000
 476 #define RATR_MCS3               0x00008000
 477 #define RATR_MCS4               0x00010000
 478 #define RATR_MCS5               0x00020000
 479 #define RATR_MCS6               0x00040000
 480 #define RATR_MCS7               0x00080000
 481 //MCS 2 Spatial Stream
 482 #define RATR_MCS8               0x00100000
 483 #define RATR_MCS9               0x00200000
 484 #define RATR_MCS10              0x00400000
 485 #define RATR_MCS11              0x00800000
 486 #define RATR_MCS12              0x01000000
 487 #define RATR_MCS13              0x02000000
 488 #define RATR_MCS14              0x04000000
 489 #define RATR_MCS15              0x08000000
 490 // ALL CCK Rate
 491 #define RATE_ALL_CCK            RATR_1M|RATR_2M|RATR_55M|RATR_11M
 492 #define RATE_ALL_OFDM_AG        RATR_6M|RATR_9M|RATR_12M|RATR_18M|RATR_24M|RATR_36M|RATR_48M|RATR_54M
 493 #define RATE_ALL_OFDM_1SS       RATR_MCS0|RATR_MCS1|RATR_MCS2|RATR_MCS3 | \
 494                                                                         RATR_MCS4|RATR_MCS5|RATR_MCS6   |RATR_MCS7
 495 #define RATE_ALL_OFDM_2SS       RATR_MCS8|RATR_MCS9     |RATR_MCS10|RATR_MCS11| \
 496                                                                         RATR_MCS12|RATR_MCS13|RATR_MCS14|RATR_MCS15
 497
 498
 499         DRIVER_RSSI             = 0x32c,        // Driver tell Firmware current RSSI
 500         MCS_TXAGC               = 0x340, // MCS AGC
 501         CCK_TXAGC               = 0x348, // CCK AGC
 502 //      IMR                     = 0x354, // Interrupt Mask Register
 503 //      IMR_POLL                = 0x360,
 504         MacBlkCtrl              = 0x403, // Mac block on/off control register
 505
 506         //Cmd9346CR             = 0x00e,
 507 //#define Cmd9346CR_9356SEL     (1<<4)
 508 #if 0
 509 /* 0x0006 - 0x0007 - reserved */
 510         RXFIFOCOUNT             = 0x010,
 511         TXFIFOCOUNT             = 0x012,
 512         BQREQ                   = 0x013,
 513 /* 0x0010 - 0x0017 - reserved */
 514         TSFTR                   = 0x018,
 515         TLPDA                   = 0x020,
 516         TNPDA                   = 0x024,
 517         THPDA                   = 0x028,
 518         BSSID                   = 0x02E,
 519         RESP_RATE               = 0x034,
 520         CMD                     = 0x037,
 521 #define CMD_RST_SHIFT 4
 522 #define CMD_RESERVED_MASK ((1<<1) | (1<<5) | (1<<6) | (1<<7))
 523 #define CMD_RX_ENABLE_SHIFT 3
 524 #define CMD_TX_ENABLE_SHIFT 2
 525 #define CR_RST      ((1<< 4))
 526 #define CR_RE       ((1<< 3))
 527 #define CR_TE       ((1<< 2))
 528 #define CR_MulRW    ((1<< 0))
 529
 530         INTA                    = 0x03e,
 531 #endif
 532
 533 ///////////////////
 534 //////////////////
 535 #if 0
 536         TX_CONF                 = 0x040,
 537 #define TX_CONF_HEADER_AUTOICREMENT_SHIFT 30
 538 #define TX_LOOPBACK_SHIFT 17
 539 #define TX_LOOPBACK_MAC 1
 540 #define TX_LOOPBACK_BASEBAND 2
 541 #define TX_LOOPBACK_NONE 0
 542 #define TX_LOOPBACK_CONTINUE 3
 543 #define TX_LOOPBACK_MASK ((1<<17)|(1<<18))
 544 #define TX_LRLRETRY_SHIFT 0
 545 #define TX_SRLRETRY_SHIFT 8
 546 #define TX_NOICV_SHIFT 19
 547 #define TX_NOCRC_SHIFT 16
 548 #define TCR_DurProcMode  ((1<<30))
 549 #define TCR_DISReqQsize  ((1<<28))
 550 #define TCR_HWVERID_MASK ((1<<27)|(1<<26)|(1<<25))
 551 #define TCR_HWVERID_SHIFT 25
 552 #define TCR_SWPLCPLEN     ((1<<24))
 553 #define TCR_PLCP_LEN TCR_SAT // rtl8180
 554 #define TCR_MXDMA_MASK   ((1<<23)|(1<<22)|(1<<21))
 555 #define TCR_MXDMA_1024 6
 556 #define TCR_MXDMA_2048 7
 557 #define TCR_MXDMA_SHIFT  21
 558 #define TCR_DISCW   ((1<<20))
 559 #define TCR_ICV     ((1<<19))
 560 #define TCR_LBK     ((1<<18)|(1<<17))
 561 #define TCR_LBK1    ((1<<18))
 562 #define TCR_LBK0    ((1<<17))
 563 #define TCR_CRC     ((1<<16))
 564 #define TCR_SRL_MASK   ((1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9)|(1<<8))
 565 #define TCR_LRL_MASK   ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)|(1<<6)|(1<<7))
 566 #define TCR_PROBE_NOTIMESTAMP_SHIFT 29 //rtl8185
 567
 568         RX_CONF                 = 0x044,
 569 #define MAC_FILTER_MASK ((1<<0) | (1<<1) | (1<<2) | (1<<3) | (1<<5) | \
 570 (1<<12) | (1<<18) | (1<<19) | (1<<20) | (1<<21) | (1<<22) | (1<<23))
 571 #define RX_CHECK_BSSID_SHIFT 23
 572 #define ACCEPT_PWR_FRAME_SHIFT 22
 573 #define ACCEPT_MNG_FRAME_SHIFT 20
 574 #define ACCEPT_CTL_FRAME_SHIFT 19
 575 #define ACCEPT_DATA_FRAME_SHIFT 18
 576 #define ACCEPT_ICVERR_FRAME_SHIFT 12
 577 #define ACCEPT_CRCERR_FRAME_SHIFT 5
 578 #define ACCEPT_BCAST_FRAME_SHIFT 3
 579 #define ACCEPT_MCAST_FRAME_SHIFT 2
 580 #define ACCEPT_ALLMAC_FRAME_SHIFT 0
 581 #define ACCEPT_NICMAC_FRAME_SHIFT 1
 582 #define RX_FIFO_THRESHOLD_MASK ((1<<13) | (1<<14) | (1<<15))
 583 #define RX_FIFO_THRESHOLD_SHIFT 13
 584 #define RX_FIFO_THRESHOLD_128 3
 585 #define RX_FIFO_THRESHOLD_256 4
 586 #define RX_FIFO_THRESHOLD_512 5
 587 #define RX_FIFO_THRESHOLD_1024 6
 588 #define RX_FIFO_THRESHOLD_NONE 7
 589 #define RX_AUTORESETPHY_SHIFT 28
 590 #define MAX_RX_DMA_MASK ((1<<8) | (1<<9) | (1<<10))
 591 #define MAX_RX_DMA_2048 7
 592 #define MAX_RX_DMA_1024 6
 593 #define MAX_RX_DMA_SHIFT 10
 594 #define RCR_ONLYERLPKT ((1<<31))
 595 #define RCR_CS_SHIFT   29
 596 #define RCR_CS_MASK    ((1<<30) | (1<<29))
 597 #define RCR_ENMARP     ((1<<28))
 598 #define RCR_CBSSID     ((1<<23))
 599 #define RCR_APWRMGT    ((1<<22))
 600 #define RCR_ADD3       ((1<<21))
 601 #define RCR_AMF        ((1<<20))
 602 #define RCR_ACF        ((1<<19))
 603 #define RCR_ADF        ((1<<18))
 604 #define RCR_RXFTH      ((1<<15)|(1<<14)|(1<<13))
 605 #define RCR_RXFTH2     ((1<<15))
 606 #define RCR_RXFTH1     ((1<<14))
 607 #define RCR_RXFTH0     ((1<<13))
 608 #define RCR_AICV       ((1<<12))
 609 #define RCR_MXDMA      ((1<<10)|(1<< 9)|(1<< 8))
 610 #define RCR_MXDMA2     ((1<<10))
 611 #define RCR_MXDMA1     ((1<< 9))
 612 #define RCR_MXDMA0     ((1<< 8))
 613 #define RCR_9356SEL    ((1<< 6))
 614 #define RCR_ACRC32     ((1<< 5))
 615 #define RCR_AB         ((1<< 3))
 616 #define RCR_AM         ((1<< 2))
 617 #define RCR_APM        ((1<< 1))
 618 #define RCR_AAP        ((1<< 0))
 619
 620         INT_TIMEOUT             = 0x048,
 621
 622         TX_BEACON_RING_ADDR     = 0x04c,
 623
 624 #endif
 625 #if 0
 626         CONFIG0                 = 0x051,
 627 #define CONFIG0_WEP104     ((1<<6))
 628 #define CONFIG0_LEDGPO_En  ((1<<4))
 629 #define CONFIG0_Aux_Status ((1<<3))
 630 #define CONFIG0_GL         ((1<<1)|(1<<0))
 631 #define CONFIG0_GL1        ((1<<1))
 632 #define CONFIG0_GL0        ((1<<0))
 633         CONFIG1                 = 0x052,
 634 #define CONFIG1_LEDS       ((1<<7)|(1<<6))
 635 #define CONFIG1_LEDS1      ((1<<7))
 636 #define CONFIG1_LEDS0      ((1<<6))
 637 #define CONFIG1_LWACT      ((1<<4))
 638 #define CONFIG1_MEMMAP     ((1<<3))
 639 #define CONFIG1_IOMAP      ((1<<2))
 640 #define CONFIG1_VPD        ((1<<1))
 641 #define CONFIG1_PMEn       ((1<<0))
 642         CONFIG2                 = 0x053,
 643 #define CONFIG2_LCK        ((1<<7))
 644 #define CONFIG2_ANT        ((1<<6))
 645 #define CONFIG2_DPS        ((1<<3))
 646 #define CONFIG2_PAPE_sign  ((1<<2))
 647 #define CONFIG2_PAPE_time  ((1<<1)|(1<<0))
 648 #define CONFIG2_PAPE_time1 ((1<<1))
 649 #define CONFIG2_PAPE_time0 ((1<<0))
 650         ANA_PARAM               = 0x054,
 651         CONFIG3                 = 0x059,
 652 #define CONFIG3_GNTSel     ((1<<7))
 653 #define CONFIG3_PARM_En    ((1<<6))
 654 #define CONFIG3_Magic      ((1<<5))
 655 #define CONFIG3_CardB_En   ((1<<3))
 656 #define CONFIG3_CLKRUN_En  ((1<<2))
 657 #define CONFIG3_FuncRegEn  ((1<<1))
 658 #define CONFIG3_FBtbEn     ((1<<0))
 659 #define CONFIG3_CLKRUN_SHIFT 2
 660 #define CONFIG3_ANAPARAM_W_SHIFT 6
 661         CONFIG4                 = 0x05a,
 662 #define CONFIG4_VCOPDN     ((1<<7))
 663 #define CONFIG4_PWROFF     ((1<<6))
 664 #define CONFIG4_PWRMGT     ((1<<5))
 665 #define CONFIG4_LWPME      ((1<<4))
 666 #define CONFIG4_LWPTN      ((1<<2))
 667 #define CONFIG4_RFTYPE     ((1<<1)|(1<<0))
 668 #define CONFIG4_RFTYPE1    ((1<<1))
 669 #define CONFIG4_RFTYPE0    ((1<<0))
 670         TESTR                   = 0x05b,
 671 #define TFPC_AC  0x05C
 672
 673 #define SCR 0x05F
 674         PGSELECT                = 0x05e,
 675 #define PGSELECT_PG_SHIFT 0
 676         SECURITY                = 0x05f,
 677 #define SECURITY_WEP_TX_ENABLE_SHIFT 1
 678 #define SECURITY_WEP_RX_ENABLE_SHIFT 0
 679 #define SECURITY_ENCRYP_104 1
 680 #define SECURITY_ENCRYP_SHIFT 4
 681 #define SECURITY_ENCRYP_MASK ((1<<4)|(1<<5))
 682
 683         ANA_PARAM2              = 0x060,
 684         BEACON_INTERVAL         = 0x070,
 685 #define BEACON_INTERVAL_MASK ((1<<0)|(1<<1)|(1<<2)|(1<<3)|(1<<4)|(1<<5)| \
 686 (1<<6)|(1<<7)|(1<<8)|(1<<9))
 687
 688         ATIM_WND                = 0x072,
 689 #define ATIM_WND_MASK      (0x01FF)
 690
 691         BCN_INTR_ITV            = 0x074,
 692 #define BCN_INTR_ITV_MASK  (0x01FF)
 693
 694         ATIM_INTR_ITV           = 0x076,
 695 #define ATIM_INTR_ITV_MASK  (0x01FF)
 696
 697         AckTimeOutReg           = 0x079, //ACK timeout register, in unit of 4 us.
 698         PHY_ADR                 = 0x07c,
 699         PHY_READ                = 0x07e,
 700         RFPinsOutput            = 0x080,
 701         RFPinsEnable            = 0x082,
 702 //Page 0
 703         RFPinsSelect            = 0x084,
 704 #define SW_CONTROL_GPIO 0x400
 705         RFPinsInput             = 0x086,
 706         RF_PARA                 = 0x088,
 707         RF_TIMING               = 0x08c,
 708         GP_ENABLE               = 0x090,
 709         GPIO                    = 0x091,
 710         TX_AGC_CTL              = 0x09c,
 711 #define TX_AGC_CTL_PER_PACKET_TXAGC     0x01
 712 #define TX_AGC_CTL_PERPACKET_GAIN_SHIFT 0
 713 #define TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT 1
 714 #define TX_AGC_CTL_FEEDBACK_ANT 2
 715 #define TXAGC_CTL_PER_PACKET_ANT_SEL 0x02
 716         OFDM_TXAGC              = 0x09e,
 717         ANTSEL                  = 0x09f,
 718
 719
 720
 721         SIFS                    = 0x0b4,
 722         DIFS                    = 0x0b5,
 723         SLOT                    = 0x0b6,
 724         CW_CONF                 = 0x0bc,
 725 #define CW_CONF_PERPACKET_RETRY_LIMIT 0x02
 726 #define CW_CONF_PERPACKET_CW 0x01
 727 #define CW_CONF_PERPACKET_RETRY_SHIFT 1
 728 #define CW_CONF_PERPACKET_CW_SHIFT 0
 729         CW_VAL                  = 0x0bd,
 730         RATE_FALLBACK           = 0x0be,
 731 #define MAX_RESP_RATE_SHIFT 4
 732 #define MIN_RESP_RATE_SHIFT 0
 733 #define RATE_FALLBACK_CTL_ENABLE  0x80
 734 #define RATE_FALLBACK_CTL_AUTO_STEP0 0x00
 735         ACM_CONTROL             = 0x0BF,      // ACM Control Registe
 736 //----------------------------------------------------------------------------
 737 //       8187B ACM_CONTROL bits                                         (Offset 0xBF, 1 Byte)
 738 //----------------------------------------------------------------------------
 739 #define VOQ_ACM_EN                              (0x01 << 7) //BIT7
 740 #define VIQ_ACM_EN                              (0x01 << 6) //BIT6
 741 #define BEQ_ACM_EN                              (0x01 << 5) //BIT5
 742 #define ACM_HW_EN                               (0x01 << 4) //BIT4
 743 #define TXOPSEL                                 (0x01 << 3) //BIT3
 744 #define VOQ_ACM_CTL                             (0x01 << 2) //BIT2 // Set to 1 when AC_VO used time reaches or exceeds the admitted time
 745 #define VIQ_ACM_CTL                             (0x01 << 1) //BIT1 // Set to 1 when AC_VI used time reaches or exceeds the admitted time
 746 #define BEQ_ACM_CTL                             (0x01 << 0) //BIT0 // Set to 1 when AC_BE used time reaches or exceeds the admitted time
 747         CONFIG5                 = 0x0D8,
 748 #define CONFIG5_TX_FIFO_OK ((1<<7))
 749 #define CONFIG5_RX_FIFO_OK ((1<<6))
 750 #define CONFIG5_CALON      ((1<<5))
 751 #define CONFIG5_EACPI      ((1<<2))
 752 #define CONFIG5_LANWake    ((1<<1))
 753 #define CONFIG5_PME_STS    ((1<<0))
 754         TX_DMA_POLLING          = 0x0fd,
 755 #define TX_DMA_POLLING_BEACON_SHIFT 7
 756 #define TX_DMA_POLLING_HIPRIORITY_SHIFT 6
 757 #define TX_DMA_POLLING_NORMPRIORITY_SHIFT 5
 758 #define TX_DMA_POLLING_LOWPRIORITY_SHIFT 4
 759 #define TX_DMA_STOP_BEACON_SHIFT 3
 760 #define TX_DMA_STOP_HIPRIORITY_SHIFT 2
 761 #define TX_DMA_STOP_NORMPRIORITY_SHIFT 1
 762 #define TX_DMA_STOP_LOWPRIORITY_SHIFT 0
 763         CWR                     = 0x0DC,
 764         RetryCTR                = 0x0DE,
 765         INT_MIG                 = 0x0E2,      // Interrupt Migration (0xE2 ~ 0xE3)
 766         TID_AC_MAP              = 0x0E8,     // TID to AC Mapping Register
 767         ANA_PARAM3              = 0x0EE,
 768
 769
 770 //page 1
 771         Wakeup0                 = 0x084,
 772         Wakeup1                 = 0x08C,
 773         Wakeup2LD               = 0x094,
 774         Wakeup2HD               = 0x09C,
 775         Wakeup3LD               = 0x0A4,
 776         Wakeup3HD               = 0x0AC,
 777         Wakeup4LD               = 0x0B4,
 778         Wakeup4HD               = 0x0BC,
 779         CRC0                    = 0x0C4,
 780         CRC1                    = 0x0C6,
 781         CRC2                    = 0x0C8,
 782         CRC3                    = 0x0CA,
 783         CRC4                    = 0x0CC,
 784 /* 0x00CE - 0x00D3 - reserved */
 785
 786         RFSW_CTRL               = 0x272,   // 0x272-0x273.
 787
 788 /**************************************************************************/
 789         FER                     = 0x0F0,
 790         FEMR                    = 0x0F4,
 791         FPSR                    = 0x0F8,
 792         FFER                    = 0x0FC,
 793
 794         AC_VO_PARAM             = 0x0F0,      // AC_VO Parameters Record
 795         AC_VI_PARAM             = 0x0F4,      // AC_VI Parameters Record
 796         AC_BE_PARAM             = 0x0F8,      // AC_BE Parameters Record
 797         AC_BK_PARAM             = 0x0FC,      // AC_BK Parameters Record
 798         TALLY_SEL               = 0x0fc,
 799 #endif
 800 }
 801 ;
 802 //----------------------------------------------------------------------------
 803 //       818xB AnaParm & AnaParm2 Register
 804 //----------------------------------------------------------------------------
 805 //#define ANAPARM_ASIC_ON    0x45090658
 806 //#define ANAPARM2_ASIC_ON   0x727f3f52
 807
 808 #define GPI 0x108
 809 #define GPO 0x109
 810 #define GPE 0x10a
 811 #endif