First Support on Ginger and OMAP TI
[linux-ginger.git] / sound / soc / fsl / fsl_dma.c
blobb1a3a278819fe6fa16a1a14d38b02221a05517e2
1 /*
2 * Freescale DMA ALSA SoC PCM driver
4 * Author: Timur Tabi <timur@freescale.com>
6 * Copyright 2007-2008 Freescale Semiconductor, Inc. This file is licensed
7 * under the terms of the GNU General Public License version 2. This
8 * program is licensed "as is" without any warranty of any kind, whether
9 * express or implied.
11 * This driver implements ASoC support for the Elo DMA controller, which is
12 * the DMA controller on Freescale 83xx, 85xx, and 86xx SOCs. In ALSA terms,
13 * the PCM driver is what handles the DMA buffer.
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/platform_device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
23 #include <sound/core.h>
24 #include <sound/pcm.h>
25 #include <sound/pcm_params.h>
26 #include <sound/soc.h>
28 #include <asm/io.h>
30 #include "fsl_dma.h"
33 * The formats that the DMA controller supports, which is anything
34 * that is 8, 16, or 32 bits.
36 #define FSLDMA_PCM_FORMATS (SNDRV_PCM_FMTBIT_S8 | \
37 SNDRV_PCM_FMTBIT_U8 | \
38 SNDRV_PCM_FMTBIT_S16_LE | \
39 SNDRV_PCM_FMTBIT_S16_BE | \
40 SNDRV_PCM_FMTBIT_U16_LE | \
41 SNDRV_PCM_FMTBIT_U16_BE | \
42 SNDRV_PCM_FMTBIT_S24_LE | \
43 SNDRV_PCM_FMTBIT_S24_BE | \
44 SNDRV_PCM_FMTBIT_U24_LE | \
45 SNDRV_PCM_FMTBIT_U24_BE | \
46 SNDRV_PCM_FMTBIT_S32_LE | \
47 SNDRV_PCM_FMTBIT_S32_BE | \
48 SNDRV_PCM_FMTBIT_U32_LE | \
49 SNDRV_PCM_FMTBIT_U32_BE)
51 #define FSLDMA_PCM_RATES (SNDRV_PCM_RATE_5512 | SNDRV_PCM_RATE_8000_192000 | \
52 SNDRV_PCM_RATE_CONTINUOUS)
54 /* DMA global data. This structure is used by fsl_dma_open() to determine
55 * which DMA channels to assign to a substream. Unfortunately, ASoC V1 does
56 * not allow the machine driver to provide this information to the PCM
57 * driver in advance, and there's no way to differentiate between the two
58 * DMA controllers. So for now, this driver only supports one SSI device
59 * using two DMA channels. We cannot support multiple DMA devices.
61 * ssi_stx_phys: bus address of SSI STX register
62 * ssi_srx_phys: bus address of SSI SRX register
63 * dma_channel: pointer to the DMA channel's registers
64 * irq: IRQ for this DMA channel
65 * assigned: set to 1 if that DMA channel is assigned to a substream
67 static struct {
68 dma_addr_t ssi_stx_phys;
69 dma_addr_t ssi_srx_phys;
70 struct ccsr_dma_channel __iomem *dma_channel[2];
71 unsigned int irq[2];
72 unsigned int assigned[2];
73 } dma_global_data;
76 * The number of DMA links to use. Two is the bare minimum, but if you
77 * have really small links you might need more.
79 #define NUM_DMA_LINKS 2
81 /** fsl_dma_private: p-substream DMA data
83 * Each substream has a 1-to-1 association with a DMA channel.
85 * The link[] array is first because it needs to be aligned on a 32-byte
86 * boundary, so putting it first will ensure alignment without padding the
87 * structure.
89 * @link[]: array of link descriptors
90 * @controller_id: which DMA controller (0, 1, ...)
91 * @channel_id: which DMA channel on the controller (0, 1, 2, ...)
92 * @dma_channel: pointer to the DMA channel's registers
93 * @irq: IRQ for this DMA channel
94 * @substream: pointer to the substream object, needed by the ISR
95 * @ssi_sxx_phys: bus address of the STX or SRX register to use
96 * @ld_buf_phys: physical address of the LD buffer
97 * @current_link: index into link[] of the link currently being processed
98 * @dma_buf_phys: physical address of the DMA buffer
99 * @dma_buf_next: physical address of the next period to process
100 * @dma_buf_end: physical address of the byte after the end of the DMA
101 * @buffer period_size: the size of a single period
102 * @num_periods: the number of periods in the DMA buffer
104 struct fsl_dma_private {
105 struct fsl_dma_link_descriptor link[NUM_DMA_LINKS];
106 unsigned int controller_id;
107 unsigned int channel_id;
108 struct ccsr_dma_channel __iomem *dma_channel;
109 unsigned int irq;
110 struct snd_pcm_substream *substream;
111 dma_addr_t ssi_sxx_phys;
112 dma_addr_t ld_buf_phys;
113 unsigned int current_link;
114 dma_addr_t dma_buf_phys;
115 dma_addr_t dma_buf_next;
116 dma_addr_t dma_buf_end;
117 size_t period_size;
118 unsigned int num_periods;
122 * fsl_dma_hardare: define characteristics of the PCM hardware.
124 * The PCM hardware is the Freescale DMA controller. This structure defines
125 * the capabilities of that hardware.
127 * Since the sampling rate and data format are not controlled by the DMA
128 * controller, we specify no limits for those values. The only exception is
129 * period_bytes_min, which is set to a reasonably low value to prevent the
130 * DMA controller from generating too many interrupts per second.
132 * Since each link descriptor has a 32-bit byte count field, we set
133 * period_bytes_max to the largest 32-bit number. We also have no maximum
134 * number of periods.
136 * Note that we specify SNDRV_PCM_INFO_JOINT_DUPLEX here, but only because a
137 * limitation in the SSI driver requires the sample rates for playback and
138 * capture to be the same.
140 static const struct snd_pcm_hardware fsl_dma_hardware = {
142 .info = SNDRV_PCM_INFO_INTERLEAVED |
143 SNDRV_PCM_INFO_MMAP |
144 SNDRV_PCM_INFO_MMAP_VALID |
145 SNDRV_PCM_INFO_JOINT_DUPLEX |
146 SNDRV_PCM_INFO_PAUSE,
147 .formats = FSLDMA_PCM_FORMATS,
148 .rates = FSLDMA_PCM_RATES,
149 .rate_min = 5512,
150 .rate_max = 192000,
151 .period_bytes_min = 512, /* A reasonable limit */
152 .period_bytes_max = (u32) -1,
153 .periods_min = NUM_DMA_LINKS,
154 .periods_max = (unsigned int) -1,
155 .buffer_bytes_max = 128 * 1024, /* A reasonable limit */
159 * fsl_dma_abort_stream: tell ALSA that the DMA transfer has aborted
161 * This function should be called by the ISR whenever the DMA controller
162 * halts data transfer.
164 static void fsl_dma_abort_stream(struct snd_pcm_substream *substream)
166 unsigned long flags;
168 snd_pcm_stream_lock_irqsave(substream, flags);
170 if (snd_pcm_running(substream))
171 snd_pcm_stop(substream, SNDRV_PCM_STATE_XRUN);
173 snd_pcm_stream_unlock_irqrestore(substream, flags);
177 * fsl_dma_update_pointers - update LD pointers to point to the next period
179 * As each period is completed, this function changes the the link
180 * descriptor pointers for that period to point to the next period.
182 static void fsl_dma_update_pointers(struct fsl_dma_private *dma_private)
184 struct fsl_dma_link_descriptor *link =
185 &dma_private->link[dma_private->current_link];
187 /* Update our link descriptors to point to the next period */
188 if (dma_private->substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
189 link->source_addr =
190 cpu_to_be32(dma_private->dma_buf_next);
191 else
192 link->dest_addr =
193 cpu_to_be32(dma_private->dma_buf_next);
195 /* Update our variables for next time */
196 dma_private->dma_buf_next += dma_private->period_size;
198 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
199 dma_private->dma_buf_next = dma_private->dma_buf_phys;
201 if (++dma_private->current_link >= NUM_DMA_LINKS)
202 dma_private->current_link = 0;
206 * fsl_dma_isr: interrupt handler for the DMA controller
208 * @irq: IRQ of the DMA channel
209 * @dev_id: pointer to the dma_private structure for this DMA channel
211 static irqreturn_t fsl_dma_isr(int irq, void *dev_id)
213 struct fsl_dma_private *dma_private = dev_id;
214 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
215 irqreturn_t ret = IRQ_NONE;
216 u32 sr, sr2 = 0;
218 /* We got an interrupt, so read the status register to see what we
219 were interrupted for.
221 sr = in_be32(&dma_channel->sr);
223 if (sr & CCSR_DMA_SR_TE) {
224 dev_err(dma_private->substream->pcm->card->dev,
225 "DMA transmit error (controller=%u channel=%u irq=%u\n",
226 dma_private->controller_id,
227 dma_private->channel_id, irq);
228 fsl_dma_abort_stream(dma_private->substream);
229 sr2 |= CCSR_DMA_SR_TE;
230 ret = IRQ_HANDLED;
233 if (sr & CCSR_DMA_SR_CH)
234 ret = IRQ_HANDLED;
236 if (sr & CCSR_DMA_SR_PE) {
237 dev_err(dma_private->substream->pcm->card->dev,
238 "DMA%u programming error (channel=%u irq=%u)\n",
239 dma_private->controller_id,
240 dma_private->channel_id, irq);
241 fsl_dma_abort_stream(dma_private->substream);
242 sr2 |= CCSR_DMA_SR_PE;
243 ret = IRQ_HANDLED;
246 if (sr & CCSR_DMA_SR_EOLNI) {
247 sr2 |= CCSR_DMA_SR_EOLNI;
248 ret = IRQ_HANDLED;
251 if (sr & CCSR_DMA_SR_CB)
252 ret = IRQ_HANDLED;
254 if (sr & CCSR_DMA_SR_EOSI) {
255 struct snd_pcm_substream *substream = dma_private->substream;
257 /* Tell ALSA we completed a period. */
258 snd_pcm_period_elapsed(substream);
261 * Update our link descriptors to point to the next period. We
262 * only need to do this if the number of periods is not equal to
263 * the number of links.
265 if (dma_private->num_periods != NUM_DMA_LINKS)
266 fsl_dma_update_pointers(dma_private);
268 sr2 |= CCSR_DMA_SR_EOSI;
269 ret = IRQ_HANDLED;
272 if (sr & CCSR_DMA_SR_EOLSI) {
273 sr2 |= CCSR_DMA_SR_EOLSI;
274 ret = IRQ_HANDLED;
277 /* Clear the bits that we set */
278 if (sr2)
279 out_be32(&dma_channel->sr, sr2);
281 return ret;
285 * fsl_dma_new: initialize this PCM driver.
287 * This function is called when the codec driver calls snd_soc_new_pcms(),
288 * once for each .dai_link in the machine driver's snd_soc_card
289 * structure.
291 static int fsl_dma_new(struct snd_card *card, struct snd_soc_dai *dai,
292 struct snd_pcm *pcm)
294 static u64 fsl_dma_dmamask = DMA_BIT_MASK(32);
295 int ret;
297 if (!card->dev->dma_mask)
298 card->dev->dma_mask = &fsl_dma_dmamask;
300 if (!card->dev->coherent_dma_mask)
301 card->dev->coherent_dma_mask = fsl_dma_dmamask;
303 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
304 fsl_dma_hardware.buffer_bytes_max,
305 &pcm->streams[0].substream->dma_buffer);
306 if (ret) {
307 dev_err(card->dev,
308 "Can't allocate playback DMA buffer (size=%u)\n",
309 fsl_dma_hardware.buffer_bytes_max);
310 return -ENOMEM;
313 ret = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, card->dev,
314 fsl_dma_hardware.buffer_bytes_max,
315 &pcm->streams[1].substream->dma_buffer);
316 if (ret) {
317 snd_dma_free_pages(&pcm->streams[0].substream->dma_buffer);
318 dev_err(card->dev,
319 "Can't allocate capture DMA buffer (size=%u)\n",
320 fsl_dma_hardware.buffer_bytes_max);
321 return -ENOMEM;
324 return 0;
328 * fsl_dma_open: open a new substream.
330 * Each substream has its own DMA buffer.
332 * ALSA divides the DMA buffer into N periods. We create NUM_DMA_LINKS link
333 * descriptors that ping-pong from one period to the next. For example, if
334 * there are six periods and two link descriptors, this is how they look
335 * before playback starts:
337 * The last link descriptor
338 * ____________ points back to the first
339 * | |
340 * V |
341 * ___ ___ |
342 * | |->| |->|
343 * |___| |___|
344 * | |
345 * | |
346 * V V
347 * _________________________________________
348 * | | | | | | | The DMA buffer is
349 * | | | | | | | divided into 6 parts
350 * |______|______|______|______|______|______|
352 * and here's how they look after the first period is finished playing:
354 * ____________
355 * | |
356 * V |
357 * ___ ___ |
358 * | |->| |->|
359 * |___| |___|
360 * | |
361 * |______________
362 * | |
363 * V V
364 * _________________________________________
365 * | | | | | | |
366 * | | | | | | |
367 * |______|______|______|______|______|______|
369 * The first link descriptor now points to the third period. The DMA
370 * controller is currently playing the second period. When it finishes, it
371 * will jump back to the first descriptor and play the third period.
373 * There are four reasons we do this:
375 * 1. The only way to get the DMA controller to automatically restart the
376 * transfer when it gets to the end of the buffer is to use chaining
377 * mode. Basic direct mode doesn't offer that feature.
378 * 2. We need to receive an interrupt at the end of every period. The DMA
379 * controller can generate an interrupt at the end of every link transfer
380 * (aka segment). Making each period into a DMA segment will give us the
381 * interrupts we need.
382 * 3. By creating only two link descriptors, regardless of the number of
383 * periods, we do not need to reallocate the link descriptors if the
384 * number of periods changes.
385 * 4. All of the audio data is still stored in a single, contiguous DMA
386 * buffer, which is what ALSA expects. We're just dividing it into
387 * contiguous parts, and creating a link descriptor for each one.
389 static int fsl_dma_open(struct snd_pcm_substream *substream)
391 struct snd_pcm_runtime *runtime = substream->runtime;
392 struct fsl_dma_private *dma_private;
393 struct ccsr_dma_channel __iomem *dma_channel;
394 dma_addr_t ld_buf_phys;
395 u64 temp_link; /* Pointer to next link descriptor */
396 u32 mr;
397 unsigned int channel;
398 int ret = 0;
399 unsigned int i;
402 * Reject any DMA buffer whose size is not a multiple of the period
403 * size. We need to make sure that the DMA buffer can be evenly divided
404 * into periods.
406 ret = snd_pcm_hw_constraint_integer(runtime,
407 SNDRV_PCM_HW_PARAM_PERIODS);
408 if (ret < 0) {
409 dev_err(substream->pcm->card->dev, "invalid buffer size\n");
410 return ret;
413 channel = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
415 if (dma_global_data.assigned[channel]) {
416 dev_err(substream->pcm->card->dev,
417 "DMA channel already assigned\n");
418 return -EBUSY;
421 dma_private = dma_alloc_coherent(substream->pcm->card->dev,
422 sizeof(struct fsl_dma_private), &ld_buf_phys, GFP_KERNEL);
423 if (!dma_private) {
424 dev_err(substream->pcm->card->dev,
425 "can't allocate DMA private data\n");
426 return -ENOMEM;
428 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
429 dma_private->ssi_sxx_phys = dma_global_data.ssi_stx_phys;
430 else
431 dma_private->ssi_sxx_phys = dma_global_data.ssi_srx_phys;
433 dma_private->dma_channel = dma_global_data.dma_channel[channel];
434 dma_private->irq = dma_global_data.irq[channel];
435 dma_private->substream = substream;
436 dma_private->ld_buf_phys = ld_buf_phys;
437 dma_private->dma_buf_phys = substream->dma_buffer.addr;
439 /* We only support one DMA controller for now */
440 dma_private->controller_id = 0;
441 dma_private->channel_id = channel;
443 ret = request_irq(dma_private->irq, fsl_dma_isr, 0, "DMA", dma_private);
444 if (ret) {
445 dev_err(substream->pcm->card->dev,
446 "can't register ISR for IRQ %u (ret=%i)\n",
447 dma_private->irq, ret);
448 dma_free_coherent(substream->pcm->card->dev,
449 sizeof(struct fsl_dma_private),
450 dma_private, dma_private->ld_buf_phys);
451 return ret;
454 dma_global_data.assigned[channel] = 1;
456 snd_pcm_set_runtime_buffer(substream, &substream->dma_buffer);
457 snd_soc_set_runtime_hwparams(substream, &fsl_dma_hardware);
458 runtime->private_data = dma_private;
460 /* Program the fixed DMA controller parameters */
462 dma_channel = dma_private->dma_channel;
464 temp_link = dma_private->ld_buf_phys +
465 sizeof(struct fsl_dma_link_descriptor);
467 for (i = 0; i < NUM_DMA_LINKS; i++) {
468 dma_private->link[i].next = cpu_to_be64(temp_link);
470 temp_link += sizeof(struct fsl_dma_link_descriptor);
472 /* The last link descriptor points to the first */
473 dma_private->link[i - 1].next = cpu_to_be64(dma_private->ld_buf_phys);
475 /* Tell the DMA controller where the first link descriptor is */
476 out_be32(&dma_channel->clndar,
477 CCSR_DMA_CLNDAR_ADDR(dma_private->ld_buf_phys));
478 out_be32(&dma_channel->eclndar,
479 CCSR_DMA_ECLNDAR_ADDR(dma_private->ld_buf_phys));
481 /* The manual says the BCR must be clear before enabling EMP */
482 out_be32(&dma_channel->bcr, 0);
485 * Program the mode register for interrupts, external master control,
486 * and source/destination hold. Also clear the Channel Abort bit.
488 mr = in_be32(&dma_channel->mr) &
489 ~(CCSR_DMA_MR_CA | CCSR_DMA_MR_DAHE | CCSR_DMA_MR_SAHE);
492 * We want External Master Start and External Master Pause enabled,
493 * because the SSI is controlling the DMA controller. We want the DMA
494 * controller to be set up in advance, and then we signal only the SSI
495 * to start transferring.
497 * We want End-Of-Segment Interrupts enabled, because this will generate
498 * an interrupt at the end of each segment (each link descriptor
499 * represents one segment). Each DMA segment is the same thing as an
500 * ALSA period, so this is how we get an interrupt at the end of every
501 * period.
503 * We want Error Interrupt enabled, so that we can get an error if
504 * the DMA controller is mis-programmed somehow.
506 mr |= CCSR_DMA_MR_EOSIE | CCSR_DMA_MR_EIE | CCSR_DMA_MR_EMP_EN |
507 CCSR_DMA_MR_EMS_EN;
509 /* For playback, we want the destination address to be held. For
510 capture, set the source address to be held. */
511 mr |= (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) ?
512 CCSR_DMA_MR_DAHE : CCSR_DMA_MR_SAHE;
514 out_be32(&dma_channel->mr, mr);
516 return 0;
520 * fsl_dma_hw_params: continue initializing the DMA links
522 * This function obtains hardware parameters about the opened stream and
523 * programs the DMA controller accordingly.
525 * One drawback of big-endian is that when copying integers of different
526 * sizes to a fixed-sized register, the address to which the integer must be
527 * copied is dependent on the size of the integer.
529 * For example, if P is the address of a 32-bit register, and X is a 32-bit
530 * integer, then X should be copied to address P. However, if X is a 16-bit
531 * integer, then it should be copied to P+2. If X is an 8-bit register,
532 * then it should be copied to P+3.
534 * So for playback of 8-bit samples, the DMA controller must transfer single
535 * bytes from the DMA buffer to the last byte of the STX0 register, i.e.
536 * offset by 3 bytes. For 16-bit samples, the offset is two bytes.
538 * For 24-bit samples, the offset is 1 byte. However, the DMA controller
539 * does not support 3-byte copies (the DAHTS register supports only 1, 2, 4,
540 * and 8 bytes at a time). So we do not support packed 24-bit samples.
541 * 24-bit data must be padded to 32 bits.
543 static int fsl_dma_hw_params(struct snd_pcm_substream *substream,
544 struct snd_pcm_hw_params *hw_params)
546 struct snd_pcm_runtime *runtime = substream->runtime;
547 struct fsl_dma_private *dma_private = runtime->private_data;
549 /* Number of bits per sample */
550 unsigned int sample_size =
551 snd_pcm_format_physical_width(params_format(hw_params));
553 /* Number of bytes per frame */
554 unsigned int frame_size = 2 * (sample_size / 8);
556 /* Bus address of SSI STX register */
557 dma_addr_t ssi_sxx_phys = dma_private->ssi_sxx_phys;
559 /* Size of the DMA buffer, in bytes */
560 size_t buffer_size = params_buffer_bytes(hw_params);
562 /* Number of bytes per period */
563 size_t period_size = params_period_bytes(hw_params);
565 /* Pointer to next period */
566 dma_addr_t temp_addr = substream->dma_buffer.addr;
568 /* Pointer to DMA controller */
569 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
571 u32 mr; /* DMA Mode Register */
573 unsigned int i;
575 /* Initialize our DMA tracking variables */
576 dma_private->period_size = period_size;
577 dma_private->num_periods = params_periods(hw_params);
578 dma_private->dma_buf_end = dma_private->dma_buf_phys + buffer_size;
579 dma_private->dma_buf_next = dma_private->dma_buf_phys +
580 (NUM_DMA_LINKS * period_size);
582 if (dma_private->dma_buf_next >= dma_private->dma_buf_end)
583 /* This happens if the number of periods == NUM_DMA_LINKS */
584 dma_private->dma_buf_next = dma_private->dma_buf_phys;
586 mr = in_be32(&dma_channel->mr) & ~(CCSR_DMA_MR_BWC_MASK |
587 CCSR_DMA_MR_SAHTS_MASK | CCSR_DMA_MR_DAHTS_MASK);
589 /* Due to a quirk of the SSI's STX register, the target address
590 * for the DMA operations depends on the sample size. So we calculate
591 * that offset here. While we're at it, also tell the DMA controller
592 * how much data to transfer per sample.
594 switch (sample_size) {
595 case 8:
596 mr |= CCSR_DMA_MR_DAHTS_1 | CCSR_DMA_MR_SAHTS_1;
597 ssi_sxx_phys += 3;
598 break;
599 case 16:
600 mr |= CCSR_DMA_MR_DAHTS_2 | CCSR_DMA_MR_SAHTS_2;
601 ssi_sxx_phys += 2;
602 break;
603 case 32:
604 mr |= CCSR_DMA_MR_DAHTS_4 | CCSR_DMA_MR_SAHTS_4;
605 break;
606 default:
607 /* We should never get here */
608 dev_err(substream->pcm->card->dev,
609 "unsupported sample size %u\n", sample_size);
610 return -EINVAL;
614 * BWC should always be a multiple of the frame size. BWC determines
615 * how many bytes are sent/received before the DMA controller checks the
616 * SSI to see if it needs to stop. For playback, the transmit FIFO can
617 * hold three frames, so we want to send two frames at a time. For
618 * capture, the receive FIFO is triggered when it contains one frame, so
619 * we want to receive one frame at a time.
621 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
622 mr |= CCSR_DMA_MR_BWC(2 * frame_size);
623 else
624 mr |= CCSR_DMA_MR_BWC(frame_size);
626 out_be32(&dma_channel->mr, mr);
628 for (i = 0; i < NUM_DMA_LINKS; i++) {
629 struct fsl_dma_link_descriptor *link = &dma_private->link[i];
631 link->count = cpu_to_be32(period_size);
633 /* Even though the DMA controller supports 36-bit addressing,
634 * for simplicity we allow only 32-bit addresses for the audio
635 * buffer itself. This was enforced in fsl_dma_new() with the
636 * DMA mask.
638 * The snoop bit tells the DMA controller whether it should tell
639 * the ECM to snoop during a read or write to an address. For
640 * audio, we use DMA to transfer data between memory and an I/O
641 * device (the SSI's STX0 or SRX0 register). Snooping is only
642 * needed if there is a cache, so we need to snoop memory
643 * addresses only. For playback, that means we snoop the source
644 * but not the destination. For capture, we snoop the
645 * destination but not the source.
647 * Note that failing to snoop properly is unlikely to cause
648 * cache incoherency if the period size is larger than the
649 * size of L1 cache. This is because filling in one period will
650 * flush out the data for the previous period. So if you
651 * increased period_bytes_min to a large enough size, you might
652 * get more performance by not snooping, and you'll still be
653 * okay.
655 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
656 link->source_addr = cpu_to_be32(temp_addr);
657 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
659 link->dest_addr = cpu_to_be32(ssi_sxx_phys);
660 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
661 } else {
662 link->source_addr = cpu_to_be32(ssi_sxx_phys);
663 link->source_attr = cpu_to_be32(CCSR_DMA_ATR_NOSNOOP);
665 link->dest_addr = cpu_to_be32(temp_addr);
666 link->dest_attr = cpu_to_be32(CCSR_DMA_ATR_SNOOP);
669 temp_addr += period_size;
672 return 0;
676 * fsl_dma_pointer: determine the current position of the DMA transfer
678 * This function is called by ALSA when ALSA wants to know where in the
679 * stream buffer the hardware currently is.
681 * For playback, the SAR register contains the physical address of the most
682 * recent DMA transfer. For capture, the value is in the DAR register.
684 * The base address of the buffer is stored in the source_addr field of the
685 * first link descriptor.
687 static snd_pcm_uframes_t fsl_dma_pointer(struct snd_pcm_substream *substream)
689 struct snd_pcm_runtime *runtime = substream->runtime;
690 struct fsl_dma_private *dma_private = runtime->private_data;
691 struct ccsr_dma_channel __iomem *dma_channel = dma_private->dma_channel;
692 dma_addr_t position;
693 snd_pcm_uframes_t frames;
695 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
696 position = in_be32(&dma_channel->sar);
697 else
698 position = in_be32(&dma_channel->dar);
701 * When capture is started, the SSI immediately starts to fill its FIFO.
702 * This means that the DMA controller is not started until the FIFO is
703 * full. However, ALSA calls this function before that happens, when
704 * MR.DAR is still zero. In this case, just return zero to indicate
705 * that nothing has been received yet.
707 if (!position)
708 return 0;
710 if ((position < dma_private->dma_buf_phys) ||
711 (position > dma_private->dma_buf_end)) {
712 dev_err(substream->pcm->card->dev,
713 "dma pointer is out of range, halting stream\n");
714 return SNDRV_PCM_POS_XRUN;
717 frames = bytes_to_frames(runtime, position - dma_private->dma_buf_phys);
720 * If the current address is just past the end of the buffer, wrap it
721 * around.
723 if (frames == runtime->buffer_size)
724 frames = 0;
726 return frames;
730 * fsl_dma_hw_free: release resources allocated in fsl_dma_hw_params()
732 * Release the resources allocated in fsl_dma_hw_params() and de-program the
733 * registers.
735 * This function can be called multiple times.
737 static int fsl_dma_hw_free(struct snd_pcm_substream *substream)
739 struct snd_pcm_runtime *runtime = substream->runtime;
740 struct fsl_dma_private *dma_private = runtime->private_data;
742 if (dma_private) {
743 struct ccsr_dma_channel __iomem *dma_channel;
745 dma_channel = dma_private->dma_channel;
747 /* Stop the DMA */
748 out_be32(&dma_channel->mr, CCSR_DMA_MR_CA);
749 out_be32(&dma_channel->mr, 0);
751 /* Reset all the other registers */
752 out_be32(&dma_channel->sr, -1);
753 out_be32(&dma_channel->clndar, 0);
754 out_be32(&dma_channel->eclndar, 0);
755 out_be32(&dma_channel->satr, 0);
756 out_be32(&dma_channel->sar, 0);
757 out_be32(&dma_channel->datr, 0);
758 out_be32(&dma_channel->dar, 0);
759 out_be32(&dma_channel->bcr, 0);
760 out_be32(&dma_channel->nlndar, 0);
761 out_be32(&dma_channel->enlndar, 0);
764 return 0;
768 * fsl_dma_close: close the stream.
770 static int fsl_dma_close(struct snd_pcm_substream *substream)
772 struct snd_pcm_runtime *runtime = substream->runtime;
773 struct fsl_dma_private *dma_private = runtime->private_data;
774 int dir = substream->stream == SNDRV_PCM_STREAM_PLAYBACK ? 0 : 1;
776 if (dma_private) {
777 if (dma_private->irq)
778 free_irq(dma_private->irq, dma_private);
780 if (dma_private->ld_buf_phys) {
781 dma_unmap_single(substream->pcm->card->dev,
782 dma_private->ld_buf_phys,
783 sizeof(dma_private->link), DMA_TO_DEVICE);
786 /* Deallocate the fsl_dma_private structure */
787 dma_free_coherent(substream->pcm->card->dev,
788 sizeof(struct fsl_dma_private),
789 dma_private, dma_private->ld_buf_phys);
790 substream->runtime->private_data = NULL;
793 dma_global_data.assigned[dir] = 0;
795 return 0;
799 * Remove this PCM driver.
801 static void fsl_dma_free_dma_buffers(struct snd_pcm *pcm)
803 struct snd_pcm_substream *substream;
804 unsigned int i;
806 for (i = 0; i < ARRAY_SIZE(pcm->streams); i++) {
807 substream = pcm->streams[i].substream;
808 if (substream) {
809 snd_dma_free_pages(&substream->dma_buffer);
810 substream->dma_buffer.area = NULL;
811 substream->dma_buffer.addr = 0;
816 static struct snd_pcm_ops fsl_dma_ops = {
817 .open = fsl_dma_open,
818 .close = fsl_dma_close,
819 .ioctl = snd_pcm_lib_ioctl,
820 .hw_params = fsl_dma_hw_params,
821 .hw_free = fsl_dma_hw_free,
822 .pointer = fsl_dma_pointer,
825 struct snd_soc_platform fsl_soc_platform = {
826 .name = "fsl-dma",
827 .pcm_ops = &fsl_dma_ops,
828 .pcm_new = fsl_dma_new,
829 .pcm_free = fsl_dma_free_dma_buffers,
831 EXPORT_SYMBOL_GPL(fsl_soc_platform);
834 * fsl_dma_configure: store the DMA parameters from the fabric driver.
836 * This function is called by the ASoC fabric driver to give us the DMA and
837 * SSI channel information.
839 * Unfortunately, ASoC V1 does make it possible to determine the DMA/SSI
840 * data when a substream is created, so for now we need to store this data
841 * into a global variable. This means that we can only support one DMA
842 * controller, and hence only one SSI.
844 int fsl_dma_configure(struct fsl_dma_info *dma_info)
846 static int initialized;
848 /* We only support one DMA controller for now */
849 if (initialized)
850 return 0;
852 dma_global_data.ssi_stx_phys = dma_info->ssi_stx_phys;
853 dma_global_data.ssi_srx_phys = dma_info->ssi_srx_phys;
854 dma_global_data.dma_channel[0] = dma_info->dma_channel[0];
855 dma_global_data.dma_channel[1] = dma_info->dma_channel[1];
856 dma_global_data.irq[0] = dma_info->dma_irq[0];
857 dma_global_data.irq[1] = dma_info->dma_irq[1];
858 dma_global_data.assigned[0] = 0;
859 dma_global_data.assigned[1] = 0;
861 initialized = 1;
862 return 1;
864 EXPORT_SYMBOL_GPL(fsl_dma_configure);
866 static int __init fsl_soc_platform_init(void)
868 return snd_soc_register_platform(&fsl_soc_platform);
870 module_init(fsl_soc_platform_init);
872 static void __exit fsl_soc_platform_exit(void)
874 snd_soc_unregister_platform(&fsl_soc_platform);
876 module_exit(fsl_soc_platform_exit);
878 MODULE_AUTHOR("Timur Tabi <timur@freescale.com>");
879 MODULE_DESCRIPTION("Freescale Elo DMA ASoC PCM module");
880 MODULE_LICENSE("GPL");