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OMAP3: SR: Remove redundant defines
[linux-ginger.git] / arch / arm / mach-at91 / at91sam9rl_devices.c
blobd345f5453dbef6f4c033cc3c72dcffc3a9d446a7
1 /*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file COPYING in the main directory of this archive for
6 * more details.
7 */
8
9 #include <asm/mach/arch.h>
10 #include <asm/mach/map.h>
11
12 #include <linux/dma-mapping.h>
13 #include <linux/platform_device.h>
14 #include <linux/i2c-gpio.h>
15
16 #include <linux/fb.h>
17 #include <video/atmel_lcdc.h>
18
19 #include <mach/board.h>
20 #include <mach/gpio.h>
21 #include <mach/at91sam9rl.h>
22 #include <mach/at91sam9rl_matrix.h>
23 #include <mach/at91sam9_smc.h>
24 #include <mach/at_hdmac.h>
25
26 #include "generic.h"
27
28
29 /* --------------------------------------------------------------------
30 * HDMAC - AHB DMA Controller
31 * -------------------------------------------------------------------- */
32
33 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
34 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
35
36 static struct at_dma_platform_data atdma_pdata = {
37 .nr_channels = 2,
38 };
39
40 static struct resource hdmac_resources[] = {
41 [0] = {
42 .start = AT91_BASE_SYS + AT91_DMA,
43 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 [2] = {
47 .start = AT91SAM9RL_ID_DMA,
48 .end = AT91SAM9RL_ID_DMA,
49 .flags = IORESOURCE_IRQ,
50 },
51 };
52
53 static struct platform_device at_hdmac_device = {
54 .name = "at_hdmac",
55 .id = -1,
56 .dev = {
57 .dma_mask = &hdmac_dmamask,
58 .coherent_dma_mask = DMA_BIT_MASK(32),
59 .platform_data = &atdma_pdata,
60 },
61 .resource = hdmac_resources,
62 .num_resources = ARRAY_SIZE(hdmac_resources),
63 };
64
65 void __init at91_add_device_hdmac(void)
66 {
67 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
68 platform_device_register(&at_hdmac_device);
69 }
70 #else
71 void __init at91_add_device_hdmac(void) {}
72 #endif
73
74 /* --------------------------------------------------------------------
75 * USB HS Device (Gadget)
76 * -------------------------------------------------------------------- */
77
78 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
79
80 static struct resource usba_udc_resources[] = {
81 [0] = {
82 .start = AT91SAM9RL_UDPHS_FIFO,
83 .end = AT91SAM9RL_UDPHS_FIFO + SZ_512K - 1,
84 .flags = IORESOURCE_MEM,
85 },
86 [1] = {
87 .start = AT91SAM9RL_BASE_UDPHS,
88 .end = AT91SAM9RL_BASE_UDPHS + SZ_1K - 1,
89 .flags = IORESOURCE_MEM,
90 },
91 [2] = {
92 .start = AT91SAM9RL_ID_UDPHS,
93 .end = AT91SAM9RL_ID_UDPHS,
94 .flags = IORESOURCE_IRQ,
95 },
96 };
97
98 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
99 [idx] = { \
100 .name = nam, \
101 .index = idx, \
102 .fifo_size = maxpkt, \
103 .nr_banks = maxbk, \
104 .can_dma = dma, \
105 .can_isoc = isoc, \
106 }
107
108 static struct usba_ep_data usba_udc_ep[] __initdata = {
109 EP("ep0", 0, 64, 1, 0, 0),
110 EP("ep1", 1, 1024, 2, 1, 1),
111 EP("ep2", 2, 1024, 2, 1, 1),
112 EP("ep3", 3, 1024, 3, 1, 0),
113 EP("ep4", 4, 1024, 3, 1, 0),
114 EP("ep5", 5, 1024, 3, 1, 1),
115 EP("ep6", 6, 1024, 3, 1, 1),
116 };
117
118 #undef EP
119
120 /*
121 * pdata doesn't have room for any endpoints, so we need to
122 * append room for the ones we need right after it.
123 */
124 static struct {
125 struct usba_platform_data pdata;
126 struct usba_ep_data ep[7];
127 } usba_udc_data;
128
129 static struct platform_device at91_usba_udc_device = {
130 .name = "atmel_usba_udc",
131 .id = -1,
132 .dev = {
133 .platform_data = &usba_udc_data.pdata,
134 },
135 .resource = usba_udc_resources,
136 .num_resources = ARRAY_SIZE(usba_udc_resources),
137 };
138
139 void __init at91_add_device_usba(struct usba_platform_data *data)
140 {
141 /*
142 * Invalid pins are 0 on AT91, but the usba driver is shared
143 * with AVR32, which use negative values instead. Once/if
144 * gpio_is_valid() is ported to AT91, revisit this code.
145 */
146 usba_udc_data.pdata.vbus_pin = -EINVAL;
147 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
148 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
149
150 if (data && data->vbus_pin > 0) {
151 at91_set_gpio_input(data->vbus_pin, 0);
152 at91_set_deglitch(data->vbus_pin, 1);
153 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
154 }
155
156 /* Pullup pin is handled internally by USB device peripheral */
157
158 /* Clocks */
159 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
160 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
161
162 platform_device_register(&at91_usba_udc_device);
163 }
164 #else
165 void __init at91_add_device_usba(struct usba_platform_data *data) {}
166 #endif
167
168
169 /* --------------------------------------------------------------------
170 * MMC / SD
171 * -------------------------------------------------------------------- */
172
173 #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
174 static u64 mmc_dmamask = DMA_BIT_MASK(32);
175 static struct at91_mmc_data mmc_data;
176
177 static struct resource mmc_resources[] = {
178 [0] = {
179 .start = AT91SAM9RL_BASE_MCI,
180 .end = AT91SAM9RL_BASE_MCI + SZ_16K - 1,
181 .flags = IORESOURCE_MEM,
182 },
183 [1] = {
184 .start = AT91SAM9RL_ID_MCI,
185 .end = AT91SAM9RL_ID_MCI,
186 .flags = IORESOURCE_IRQ,
187 },
188 };
189
190 static struct platform_device at91sam9rl_mmc_device = {
191 .name = "at91_mci",
192 .id = -1,
193 .dev = {
194 .dma_mask = &mmc_dmamask,
195 .coherent_dma_mask = DMA_BIT_MASK(32),
196 .platform_data = &mmc_data,
197 },
198 .resource = mmc_resources,
199 .num_resources = ARRAY_SIZE(mmc_resources),
200 };
201
202 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
203 {
204 if (!data)
205 return;
206
207 /* input/irq */
208 if (data->det_pin) {
209 at91_set_gpio_input(data->det_pin, 1);
210 at91_set_deglitch(data->det_pin, 1);
211 }
212 if (data->wp_pin)
213 at91_set_gpio_input(data->wp_pin, 1);
214 if (data->vcc_pin)
215 at91_set_gpio_output(data->vcc_pin, 0);
216
217 /* CLK */
218 at91_set_A_periph(AT91_PIN_PA2, 0);
219
220 /* CMD */
221 at91_set_A_periph(AT91_PIN_PA1, 1);
222
223 /* DAT0, maybe DAT1..DAT3 */
224 at91_set_A_periph(AT91_PIN_PA0, 1);
225 if (data->wire4) {
226 at91_set_A_periph(AT91_PIN_PA3, 1);
227 at91_set_A_periph(AT91_PIN_PA4, 1);
228 at91_set_A_periph(AT91_PIN_PA5, 1);
229 }
230
231 mmc_data = *data;
232 platform_device_register(&at91sam9rl_mmc_device);
233 }
234 #else
235 void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
236 #endif
237
238
239 /* --------------------------------------------------------------------
240 * NAND / SmartMedia
241 * -------------------------------------------------------------------- */
242
243 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
244 static struct atmel_nand_data nand_data;
245
246 #define NAND_BASE AT91_CHIPSELECT_3
247
248 static struct resource nand_resources[] = {
249 [0] = {
250 .start = NAND_BASE,
251 .end = NAND_BASE + SZ_256M - 1,
252 .flags = IORESOURCE_MEM,
253 },
254 [1] = {
255 .start = AT91_BASE_SYS + AT91_ECC,
256 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
257 .flags = IORESOURCE_MEM,
258 }
259 };
260
261 static struct platform_device atmel_nand_device = {
262 .name = "atmel_nand",
263 .id = -1,
264 .dev = {
265 .platform_data = &nand_data,
266 },
267 .resource = nand_resources,
268 .num_resources = ARRAY_SIZE(nand_resources),
269 };
270
271 void __init at91_add_device_nand(struct atmel_nand_data *data)
272 {
273 unsigned long csa;
274
275 if (!data)
276 return;
277
278 csa = at91_sys_read(AT91_MATRIX_EBICSA);
279 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
280
281 /* enable pin */
282 if (data->enable_pin)
283 at91_set_gpio_output(data->enable_pin, 1);
284
285 /* ready/busy pin */
286 if (data->rdy_pin)
287 at91_set_gpio_input(data->rdy_pin, 1);
288
289 /* card detect pin */
290 if (data->det_pin)
291 at91_set_gpio_input(data->det_pin, 1);
292
293 at91_set_A_periph(AT91_PIN_PB4, 0); /* NANDOE */
294 at91_set_A_periph(AT91_PIN_PB5, 0); /* NANDWE */
295
296 nand_data = *data;
297 platform_device_register(&atmel_nand_device);
298 }
299
300 #else
301 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
302 #endif
303
304
305 /* --------------------------------------------------------------------
306 * TWI (i2c)
307 * -------------------------------------------------------------------- */
308
309 /*
310 * Prefer the GPIO code since the TWI controller isn't robust
311 * (gets overruns and underruns under load) and can only issue
312 * repeated STARTs in one scenario (the driver doesn't yet handle them).
313 */
314 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
315
316 static struct i2c_gpio_platform_data pdata = {
317 .sda_pin = AT91_PIN_PA23,
318 .sda_is_open_drain = 1,
319 .scl_pin = AT91_PIN_PA24,
320 .scl_is_open_drain = 1,
321 .udelay = 2, /* ~100 kHz */
322 };
323
324 static struct platform_device at91sam9rl_twi_device = {
325 .name = "i2c-gpio",
326 .id = -1,
327 .dev.platform_data = &pdata,
328 };
329
330 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
331 {
332 at91_set_GPIO_periph(AT91_PIN_PA23, 1); /* TWD (SDA) */
333 at91_set_multi_drive(AT91_PIN_PA23, 1);
334
335 at91_set_GPIO_periph(AT91_PIN_PA24, 1); /* TWCK (SCL) */
336 at91_set_multi_drive(AT91_PIN_PA24, 1);
337
338 i2c_register_board_info(0, devices, nr_devices);
339 platform_device_register(&at91sam9rl_twi_device);
340 }
341
342 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
343
344 static struct resource twi_resources[] = {
345 [0] = {
346 .start = AT91SAM9RL_BASE_TWI0,
347 .end = AT91SAM9RL_BASE_TWI0 + SZ_16K - 1,
348 .flags = IORESOURCE_MEM,
349 },
350 [1] = {
351 .start = AT91SAM9RL_ID_TWI0,
352 .end = AT91SAM9RL_ID_TWI0,
353 .flags = IORESOURCE_IRQ,
354 },
355 };
356
357 static struct platform_device at91sam9rl_twi_device = {
358 .name = "at91_i2c",
359 .id = -1,
360 .resource = twi_resources,
361 .num_resources = ARRAY_SIZE(twi_resources),
362 };
363
364 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices)
365 {
366 /* pins used for TWI interface */
367 at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
368 at91_set_multi_drive(AT91_PIN_PA23, 1);
369
370 at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
371 at91_set_multi_drive(AT91_PIN_PA24, 1);
372
373 i2c_register_board_info(0, devices, nr_devices);
374 platform_device_register(&at91sam9rl_twi_device);
375 }
376 #else
377 void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_devices) {}
378 #endif
379
380
381 /* --------------------------------------------------------------------
382 * SPI
383 * -------------------------------------------------------------------- */
384
385 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
386 static u64 spi_dmamask = DMA_BIT_MASK(32);
387
388 static struct resource spi_resources[] = {
389 [0] = {
390 .start = AT91SAM9RL_BASE_SPI,
391 .end = AT91SAM9RL_BASE_SPI + SZ_16K - 1,
392 .flags = IORESOURCE_MEM,
393 },
394 [1] = {
395 .start = AT91SAM9RL_ID_SPI,
396 .end = AT91SAM9RL_ID_SPI,
397 .flags = IORESOURCE_IRQ,
398 },
399 };
400
401 static struct platform_device at91sam9rl_spi_device = {
402 .name = "atmel_spi",
403 .id = 0,
404 .dev = {
405 .dma_mask = &spi_dmamask,
406 .coherent_dma_mask = DMA_BIT_MASK(32),
407 },
408 .resource = spi_resources,
409 .num_resources = ARRAY_SIZE(spi_resources),
410 };
411
412 static const unsigned spi_standard_cs[4] = { AT91_PIN_PA28, AT91_PIN_PB7, AT91_PIN_PD8, AT91_PIN_PD9 };
413
414
415 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
416 {
417 int i;
418 unsigned long cs_pin;
419
420 at91_set_A_periph(AT91_PIN_PA25, 0); /* MISO */
421 at91_set_A_periph(AT91_PIN_PA26, 0); /* MOSI */
422 at91_set_A_periph(AT91_PIN_PA27, 0); /* SPCK */
423
424 /* Enable SPI chip-selects */
425 for (i = 0; i < nr_devices; i++) {
426 if (devices[i].controller_data)
427 cs_pin = (unsigned long) devices[i].controller_data;
428 else
429 cs_pin = spi_standard_cs[devices[i].chip_select];
430
431 /* enable chip-select pin */
432 at91_set_gpio_output(cs_pin, 1);
433
434 /* pass chip-select pin to driver */
435 devices[i].controller_data = (void *) cs_pin;
436 }
437
438 spi_register_board_info(devices, nr_devices);
439 platform_device_register(&at91sam9rl_spi_device);
440 }
441 #else
442 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
443 #endif
444
445
446 /* --------------------------------------------------------------------
447 * AC97
448 * -------------------------------------------------------------------- */
449
450 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
451 static u64 ac97_dmamask = DMA_BIT_MASK(32);
452 static struct ac97c_platform_data ac97_data;
453
454 static struct resource ac97_resources[] = {
455 [0] = {
456 .start = AT91SAM9RL_BASE_AC97C,
457 .end = AT91SAM9RL_BASE_AC97C + SZ_16K - 1,
458 .flags = IORESOURCE_MEM,
459 },
460 [1] = {
461 .start = AT91SAM9RL_ID_AC97C,
462 .end = AT91SAM9RL_ID_AC97C,
463 .flags = IORESOURCE_IRQ,
464 },
465 };
466
467 static struct platform_device at91sam9rl_ac97_device = {
468 .name = "atmel_ac97c",
469 .id = 0,
470 .dev = {
471 .dma_mask = &ac97_dmamask,
472 .coherent_dma_mask = DMA_BIT_MASK(32),
473 .platform_data = &ac97_data,
474 },
475 .resource = ac97_resources,
476 .num_resources = ARRAY_SIZE(ac97_resources),
477 };
478
479 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
480 {
481 if (!data)
482 return;
483
484 at91_set_A_periph(AT91_PIN_PD1, 0); /* AC97FS */
485 at91_set_A_periph(AT91_PIN_PD2, 0); /* AC97CK */
486 at91_set_A_periph(AT91_PIN_PD3, 0); /* AC97TX */
487 at91_set_A_periph(AT91_PIN_PD4, 0); /* AC97RX */
488
489 /* reset */
490 if (data->reset_pin)
491 at91_set_gpio_output(data->reset_pin, 0);
492
493 ac97_data = *data;
494 platform_device_register(&at91sam9rl_ac97_device);
495 }
496 #else
497 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
498 #endif
499
500
501 /* --------------------------------------------------------------------
502 * LCD Controller
503 * -------------------------------------------------------------------- */
504
505 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
506 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
507 static struct atmel_lcdfb_info lcdc_data;
508
509 static struct resource lcdc_resources[] = {
510 [0] = {
511 .start = AT91SAM9RL_LCDC_BASE,
512 .end = AT91SAM9RL_LCDC_BASE + SZ_4K - 1,
513 .flags = IORESOURCE_MEM,
514 },
515 [1] = {
516 .start = AT91SAM9RL_ID_LCDC,
517 .end = AT91SAM9RL_ID_LCDC,
518 .flags = IORESOURCE_IRQ,
519 },
520 };
521
522 static struct platform_device at91_lcdc_device = {
523 .name = "atmel_lcdfb",
524 .id = 0,
525 .dev = {
526 .dma_mask = &lcdc_dmamask,
527 .coherent_dma_mask = DMA_BIT_MASK(32),
528 .platform_data = &lcdc_data,
529 },
530 .resource = lcdc_resources,
531 .num_resources = ARRAY_SIZE(lcdc_resources),
532 };
533
534 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
535 {
536 if (!data) {
537 return;
538 }
539
540 at91_set_B_periph(AT91_PIN_PC1, 0); /* LCDPWR */
541 at91_set_A_periph(AT91_PIN_PC5, 0); /* LCDHSYNC */
542 at91_set_A_periph(AT91_PIN_PC6, 0); /* LCDDOTCK */
543 at91_set_A_periph(AT91_PIN_PC7, 0); /* LCDDEN */
544 at91_set_A_periph(AT91_PIN_PC3, 0); /* LCDCC */
545 at91_set_B_periph(AT91_PIN_PC9, 0); /* LCDD3 */
546 at91_set_B_periph(AT91_PIN_PC10, 0); /* LCDD4 */
547 at91_set_B_periph(AT91_PIN_PC11, 0); /* LCDD5 */
548 at91_set_B_periph(AT91_PIN_PC12, 0); /* LCDD6 */
549 at91_set_B_periph(AT91_PIN_PC13, 0); /* LCDD7 */
550 at91_set_B_periph(AT91_PIN_PC15, 0); /* LCDD11 */
551 at91_set_B_periph(AT91_PIN_PC16, 0); /* LCDD12 */
552 at91_set_B_periph(AT91_PIN_PC17, 0); /* LCDD13 */
553 at91_set_B_periph(AT91_PIN_PC18, 0); /* LCDD14 */
554 at91_set_B_periph(AT91_PIN_PC19, 0); /* LCDD15 */
555 at91_set_B_periph(AT91_PIN_PC20, 0); /* LCDD18 */
556 at91_set_B_periph(AT91_PIN_PC21, 0); /* LCDD19 */
557 at91_set_B_periph(AT91_PIN_PC22, 0); /* LCDD20 */
558 at91_set_B_periph(AT91_PIN_PC23, 0); /* LCDD21 */
559 at91_set_B_periph(AT91_PIN_PC24, 0); /* LCDD22 */
560 at91_set_B_periph(AT91_PIN_PC25, 0); /* LCDD23 */
561
562 lcdc_data = *data;
563 platform_device_register(&at91_lcdc_device);
564 }
565 #else
566 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
567 #endif
568
569
570 /* --------------------------------------------------------------------
571 * Timer/Counter block
572 * -------------------------------------------------------------------- */
573
574 #ifdef CONFIG_ATMEL_TCLIB
575
576 static struct resource tcb_resources[] = {
577 [0] = {
578 .start = AT91SAM9RL_BASE_TCB0,
579 .end = AT91SAM9RL_BASE_TCB0 + SZ_16K - 1,
580 .flags = IORESOURCE_MEM,
581 },
582 [1] = {
583 .start = AT91SAM9RL_ID_TC0,
584 .end = AT91SAM9RL_ID_TC0,
585 .flags = IORESOURCE_IRQ,
586 },
587 [2] = {
588 .start = AT91SAM9RL_ID_TC1,
589 .end = AT91SAM9RL_ID_TC1,
590 .flags = IORESOURCE_IRQ,
591 },
592 [3] = {
593 .start = AT91SAM9RL_ID_TC2,
594 .end = AT91SAM9RL_ID_TC2,
595 .flags = IORESOURCE_IRQ,
596 },
597 };
598
599 static struct platform_device at91sam9rl_tcb_device = {
600 .name = "atmel_tcb",
601 .id = 0,
602 .resource = tcb_resources,
603 .num_resources = ARRAY_SIZE(tcb_resources),
604 };
605
606 static void __init at91_add_device_tc(void)
607 {
608 /* this chip has a separate clock and irq for each TC channel */
609 at91_clock_associate("tc0_clk", &at91sam9rl_tcb_device.dev, "t0_clk");
610 at91_clock_associate("tc1_clk", &at91sam9rl_tcb_device.dev, "t1_clk");
611 at91_clock_associate("tc2_clk", &at91sam9rl_tcb_device.dev, "t2_clk");
612 platform_device_register(&at91sam9rl_tcb_device);
613 }
614 #else
615 static void __init at91_add_device_tc(void) { }
616 #endif
617
618
619 /* --------------------------------------------------------------------
620 * Touchscreen
621 * -------------------------------------------------------------------- */
622
623 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
624 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
625
626 static struct resource tsadcc_resources[] = {
627 [0] = {
628 .start = AT91SAM9RL_BASE_TSC,
629 .end = AT91SAM9RL_BASE_TSC + SZ_16K - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 [1] = {
633 .start = AT91SAM9RL_ID_TSC,
634 .end = AT91SAM9RL_ID_TSC,
635 .flags = IORESOURCE_IRQ,
636 }
637 };
638
639 static struct platform_device at91sam9rl_tsadcc_device = {
640 .name = "atmel_tsadcc",
641 .id = -1,
642 .dev = {
643 .dma_mask = &tsadcc_dmamask,
644 .coherent_dma_mask = DMA_BIT_MASK(32),
645 },
646 .resource = tsadcc_resources,
647 .num_resources = ARRAY_SIZE(tsadcc_resources),
648 };
649
650 void __init at91_add_device_tsadcc(void)
651 {
652 at91_set_A_periph(AT91_PIN_PA17, 0); /* AD0_XR */
653 at91_set_A_periph(AT91_PIN_PA18, 0); /* AD1_XL */
654 at91_set_A_periph(AT91_PIN_PA19, 0); /* AD2_YT */
655 at91_set_A_periph(AT91_PIN_PA20, 0); /* AD3_TB */
656
657 platform_device_register(&at91sam9rl_tsadcc_device);
658 }
659 #else
660 void __init at91_add_device_tsadcc(void) {}
661 #endif
662
663
664 /* --------------------------------------------------------------------
665 * RTC
666 * -------------------------------------------------------------------- */
667
668 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
669 static struct platform_device at91sam9rl_rtc_device = {
670 .name = "at91_rtc",
671 .id = -1,
672 .num_resources = 0,
673 };
674
675 static void __init at91_add_device_rtc(void)
676 {
677 platform_device_register(&at91sam9rl_rtc_device);
678 }
679 #else
680 static void __init at91_add_device_rtc(void) {}
681 #endif
682
683
684 /* --------------------------------------------------------------------
685 * RTT
686 * -------------------------------------------------------------------- */
687
688 static struct resource rtt_resources[] = {
689 {
690 .start = AT91_BASE_SYS + AT91_RTT,
691 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
692 .flags = IORESOURCE_MEM,
693 }
694 };
695
696 static struct platform_device at91sam9rl_rtt_device = {
697 .name = "at91_rtt",
698 .id = 0,
699 .resource = rtt_resources,
700 .num_resources = ARRAY_SIZE(rtt_resources),
701 };
702
703 static void __init at91_add_device_rtt(void)
704 {
705 platform_device_register(&at91sam9rl_rtt_device);
706 }
707
708
709 /* --------------------------------------------------------------------
710 * Watchdog
711 * -------------------------------------------------------------------- */
712
713 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
714 static struct platform_device at91sam9rl_wdt_device = {
715 .name = "at91_wdt",
716 .id = -1,
717 .num_resources = 0,
718 };
719
720 static void __init at91_add_device_watchdog(void)
721 {
722 platform_device_register(&at91sam9rl_wdt_device);
723 }
724 #else
725 static void __init at91_add_device_watchdog(void) {}
726 #endif
727
728
729 /* --------------------------------------------------------------------
730 * PWM
731 * --------------------------------------------------------------------*/
732
733 #if defined(CONFIG_ATMEL_PWM)
734 static u32 pwm_mask;
735
736 static struct resource pwm_resources[] = {
737 [0] = {
738 .start = AT91SAM9RL_BASE_PWMC,
739 .end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
740 .flags = IORESOURCE_MEM,
741 },
742 [1] = {
743 .start = AT91SAM9RL_ID_PWMC,
744 .end = AT91SAM9RL_ID_PWMC,
745 .flags = IORESOURCE_IRQ,
746 },
747 };
748
749 static struct platform_device at91sam9rl_pwm0_device = {
750 .name = "atmel_pwm",
751 .id = -1,
752 .dev = {
753 .platform_data = &pwm_mask,
754 },
755 .resource = pwm_resources,
756 .num_resources = ARRAY_SIZE(pwm_resources),
757 };
758
759 void __init at91_add_device_pwm(u32 mask)
760 {
761 if (mask & (1 << AT91_PWM0))
762 at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
763
764 if (mask & (1 << AT91_PWM1))
765 at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
766
767 if (mask & (1 << AT91_PWM2))
768 at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
769
770 if (mask & (1 << AT91_PWM3))
771 at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
772
773 pwm_mask = mask;
774
775 platform_device_register(&at91sam9rl_pwm0_device);
776 }
777 #else
778 void __init at91_add_device_pwm(u32 mask) {}
779 #endif
780
781
782 /* --------------------------------------------------------------------
783 * SSC -- Synchronous Serial Controller
784 * -------------------------------------------------------------------- */
785
786 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
787 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
788
789 static struct resource ssc0_resources[] = {
790 [0] = {
791 .start = AT91SAM9RL_BASE_SSC0,
792 .end = AT91SAM9RL_BASE_SSC0 + SZ_16K - 1,
793 .flags = IORESOURCE_MEM,
794 },
795 [1] = {
796 .start = AT91SAM9RL_ID_SSC0,
797 .end = AT91SAM9RL_ID_SSC0,
798 .flags = IORESOURCE_IRQ,
799 },
800 };
801
802 static struct platform_device at91sam9rl_ssc0_device = {
803 .name = "ssc",
804 .id = 0,
805 .dev = {
806 .dma_mask = &ssc0_dmamask,
807 .coherent_dma_mask = DMA_BIT_MASK(32),
808 },
809 .resource = ssc0_resources,
810 .num_resources = ARRAY_SIZE(ssc0_resources),
811 };
812
813 static inline void configure_ssc0_pins(unsigned pins)
814 {
815 if (pins & ATMEL_SSC_TF)
816 at91_set_A_periph(AT91_PIN_PC0, 1);
817 if (pins & ATMEL_SSC_TK)
818 at91_set_A_periph(AT91_PIN_PC1, 1);
819 if (pins & ATMEL_SSC_TD)
820 at91_set_A_periph(AT91_PIN_PA15, 1);
821 if (pins & ATMEL_SSC_RD)
822 at91_set_A_periph(AT91_PIN_PA16, 1);
823 if (pins & ATMEL_SSC_RK)
824 at91_set_B_periph(AT91_PIN_PA10, 1);
825 if (pins & ATMEL_SSC_RF)
826 at91_set_B_periph(AT91_PIN_PA22, 1);
827 }
828
829 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
830
831 static struct resource ssc1_resources[] = {
832 [0] = {
833 .start = AT91SAM9RL_BASE_SSC1,
834 .end = AT91SAM9RL_BASE_SSC1 + SZ_16K - 1,
835 .flags = IORESOURCE_MEM,
836 },
837 [1] = {
838 .start = AT91SAM9RL_ID_SSC1,
839 .end = AT91SAM9RL_ID_SSC1,
840 .flags = IORESOURCE_IRQ,
841 },
842 };
843
844 static struct platform_device at91sam9rl_ssc1_device = {
845 .name = "ssc",
846 .id = 1,
847 .dev = {
848 .dma_mask = &ssc1_dmamask,
849 .coherent_dma_mask = DMA_BIT_MASK(32),
850 },
851 .resource = ssc1_resources,
852 .num_resources = ARRAY_SIZE(ssc1_resources),
853 };
854
855 static inline void configure_ssc1_pins(unsigned pins)
856 {
857 if (pins & ATMEL_SSC_TF)
858 at91_set_B_periph(AT91_PIN_PA29, 1);
859 if (pins & ATMEL_SSC_TK)
860 at91_set_B_periph(AT91_PIN_PA30, 1);
861 if (pins & ATMEL_SSC_TD)
862 at91_set_B_periph(AT91_PIN_PA13, 1);
863 if (pins & ATMEL_SSC_RD)
864 at91_set_B_periph(AT91_PIN_PA14, 1);
865 if (pins & ATMEL_SSC_RK)
866 at91_set_B_periph(AT91_PIN_PA9, 1);
867 if (pins & ATMEL_SSC_RF)
868 at91_set_B_periph(AT91_PIN_PA8, 1);
869 }
870
871 /*
872 * SSC controllers are accessed through library code, instead of any
873 * kind of all-singing/all-dancing driver. For example one could be
874 * used by a particular I2S audio codec's driver, while another one
875 * on the same system might be used by a custom data capture driver.
876 */
877 void __init at91_add_device_ssc(unsigned id, unsigned pins)
878 {
879 struct platform_device *pdev;
880
881 /*
882 * NOTE: caller is responsible for passing information matching
883 * "pins" to whatever will be using each particular controller.
884 */
885 switch (id) {
886 case AT91SAM9RL_ID_SSC0:
887 pdev = &at91sam9rl_ssc0_device;
888 configure_ssc0_pins(pins);
889 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
890 break;
891 case AT91SAM9RL_ID_SSC1:
892 pdev = &at91sam9rl_ssc1_device;
893 configure_ssc1_pins(pins);
894 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
895 break;
896 default:
897 return;
898 }
899
900 platform_device_register(pdev);
901 }
902
903 #else
904 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
905 #endif
906
907
908 /* --------------------------------------------------------------------
909 * UART
910 * -------------------------------------------------------------------- */
911
912 #if defined(CONFIG_SERIAL_ATMEL)
913 static struct resource dbgu_resources[] = {
914 [0] = {
915 .start = AT91_VA_BASE_SYS + AT91_DBGU,
916 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
917 .flags = IORESOURCE_MEM,
918 },
919 [1] = {
920 .start = AT91_ID_SYS,
921 .end = AT91_ID_SYS,
922 .flags = IORESOURCE_IRQ,
923 },
924 };
925
926 static struct atmel_uart_data dbgu_data = {
927 .use_dma_tx = 0,
928 .use_dma_rx = 0, /* DBGU not capable of receive DMA */
929 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
930 };
931
932 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
933
934 static struct platform_device at91sam9rl_dbgu_device = {
935 .name = "atmel_usart",
936 .id = 0,
937 .dev = {
938 .dma_mask = &dbgu_dmamask,
939 .coherent_dma_mask = DMA_BIT_MASK(32),
940 .platform_data = &dbgu_data,
941 },
942 .resource = dbgu_resources,
943 .num_resources = ARRAY_SIZE(dbgu_resources),
944 };
945
946 static inline void configure_dbgu_pins(void)
947 {
948 at91_set_A_periph(AT91_PIN_PA21, 0); /* DRXD */
949 at91_set_A_periph(AT91_PIN_PA22, 1); /* DTXD */
950 }
951
952 static struct resource uart0_resources[] = {
953 [0] = {
954 .start = AT91SAM9RL_BASE_US0,
955 .end = AT91SAM9RL_BASE_US0 + SZ_16K - 1,
956 .flags = IORESOURCE_MEM,
957 },
958 [1] = {
959 .start = AT91SAM9RL_ID_US0,
960 .end = AT91SAM9RL_ID_US0,
961 .flags = IORESOURCE_IRQ,
962 },
963 };
964
965 static struct atmel_uart_data uart0_data = {
966 .use_dma_tx = 1,
967 .use_dma_rx = 1,
968 };
969
970 static u64 uart0_dmamask = DMA_BIT_MASK(32);
971
972 static struct platform_device at91sam9rl_uart0_device = {
973 .name = "atmel_usart",
974 .id = 1,
975 .dev = {
976 .dma_mask = &uart0_dmamask,
977 .coherent_dma_mask = DMA_BIT_MASK(32),
978 .platform_data = &uart0_data,
979 },
980 .resource = uart0_resources,
981 .num_resources = ARRAY_SIZE(uart0_resources),
982 };
983
984 static inline void configure_usart0_pins(unsigned pins)
985 {
986 at91_set_A_periph(AT91_PIN_PA6, 1); /* TXD0 */
987 at91_set_A_periph(AT91_PIN_PA7, 0); /* RXD0 */
988
989 if (pins & ATMEL_UART_RTS)
990 at91_set_A_periph(AT91_PIN_PA9, 0); /* RTS0 */
991 if (pins & ATMEL_UART_CTS)
992 at91_set_A_periph(AT91_PIN_PA10, 0); /* CTS0 */
993 if (pins & ATMEL_UART_DSR)
994 at91_set_A_periph(AT91_PIN_PD14, 0); /* DSR0 */
995 if (pins & ATMEL_UART_DTR)
996 at91_set_A_periph(AT91_PIN_PD15, 0); /* DTR0 */
997 if (pins & ATMEL_UART_DCD)
998 at91_set_A_periph(AT91_PIN_PD16, 0); /* DCD0 */
999 if (pins & ATMEL_UART_RI)
1000 at91_set_A_periph(AT91_PIN_PD17, 0); /* RI0 */
1001 }
1002
1003 static struct resource uart1_resources[] = {
1004 [0] = {
1005 .start = AT91SAM9RL_BASE_US1,
1006 .end = AT91SAM9RL_BASE_US1 + SZ_16K - 1,
1007 .flags = IORESOURCE_MEM,
1008 },
1009 [1] = {
1010 .start = AT91SAM9RL_ID_US1,
1011 .end = AT91SAM9RL_ID_US1,
1012 .flags = IORESOURCE_IRQ,
1013 },
1014 };
1015
1016 static struct atmel_uart_data uart1_data = {
1017 .use_dma_tx = 1,
1018 .use_dma_rx = 1,
1019 };
1020
1021 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1022
1023 static struct platform_device at91sam9rl_uart1_device = {
1024 .name = "atmel_usart",
1025 .id = 2,
1026 .dev = {
1027 .dma_mask = &uart1_dmamask,
1028 .coherent_dma_mask = DMA_BIT_MASK(32),
1029 .platform_data = &uart1_data,
1030 },
1031 .resource = uart1_resources,
1032 .num_resources = ARRAY_SIZE(uart1_resources),
1033 };
1034
1035 static inline void configure_usart1_pins(unsigned pins)
1036 {
1037 at91_set_A_periph(AT91_PIN_PA11, 1); /* TXD1 */
1038 at91_set_A_periph(AT91_PIN_PA12, 0); /* RXD1 */
1039
1040 if (pins & ATMEL_UART_RTS)
1041 at91_set_B_periph(AT91_PIN_PA18, 0); /* RTS1 */
1042 if (pins & ATMEL_UART_CTS)
1043 at91_set_B_periph(AT91_PIN_PA19, 0); /* CTS1 */
1044 }
1045
1046 static struct resource uart2_resources[] = {
1047 [0] = {
1048 .start = AT91SAM9RL_BASE_US2,
1049 .end = AT91SAM9RL_BASE_US2 + SZ_16K - 1,
1050 .flags = IORESOURCE_MEM,
1051 },
1052 [1] = {
1053 .start = AT91SAM9RL_ID_US2,
1054 .end = AT91SAM9RL_ID_US2,
1055 .flags = IORESOURCE_IRQ,
1056 },
1057 };
1058
1059 static struct atmel_uart_data uart2_data = {
1060 .use_dma_tx = 1,
1061 .use_dma_rx = 1,
1062 };
1063
1064 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1065
1066 static struct platform_device at91sam9rl_uart2_device = {
1067 .name = "atmel_usart",
1068 .id = 3,
1069 .dev = {
1070 .dma_mask = &uart2_dmamask,
1071 .coherent_dma_mask = DMA_BIT_MASK(32),
1072 .platform_data = &uart2_data,
1073 },
1074 .resource = uart2_resources,
1075 .num_resources = ARRAY_SIZE(uart2_resources),
1076 };
1077
1078 static inline void configure_usart2_pins(unsigned pins)
1079 {
1080 at91_set_A_periph(AT91_PIN_PA13, 1); /* TXD2 */
1081 at91_set_A_periph(AT91_PIN_PA14, 0); /* RXD2 */
1082
1083 if (pins & ATMEL_UART_RTS)
1084 at91_set_A_periph(AT91_PIN_PA29, 0); /* RTS2 */
1085 if (pins & ATMEL_UART_CTS)
1086 at91_set_A_periph(AT91_PIN_PA30, 0); /* CTS2 */
1087 }
1088
1089 static struct resource uart3_resources[] = {
1090 [0] = {
1091 .start = AT91SAM9RL_BASE_US3,
1092 .end = AT91SAM9RL_BASE_US3 + SZ_16K - 1,
1093 .flags = IORESOURCE_MEM,
1094 },
1095 [1] = {
1096 .start = AT91SAM9RL_ID_US3,
1097 .end = AT91SAM9RL_ID_US3,
1098 .flags = IORESOURCE_IRQ,
1099 },
1100 };
1101
1102 static struct atmel_uart_data uart3_data = {
1103 .use_dma_tx = 1,
1104 .use_dma_rx = 1,
1105 };
1106
1107 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1108
1109 static struct platform_device at91sam9rl_uart3_device = {
1110 .name = "atmel_usart",
1111 .id = 4,
1112 .dev = {
1113 .dma_mask = &uart3_dmamask,
1114 .coherent_dma_mask = DMA_BIT_MASK(32),
1115 .platform_data = &uart3_data,
1116 },
1117 .resource = uart3_resources,
1118 .num_resources = ARRAY_SIZE(uart3_resources),
1119 };
1120
1121 static inline void configure_usart3_pins(unsigned pins)
1122 {
1123 at91_set_A_periph(AT91_PIN_PB0, 1); /* TXD3 */
1124 at91_set_A_periph(AT91_PIN_PB1, 0); /* RXD3 */
1125
1126 if (pins & ATMEL_UART_RTS)
1127 at91_set_B_periph(AT91_PIN_PD4, 0); /* RTS3 */
1128 if (pins & ATMEL_UART_CTS)
1129 at91_set_B_periph(AT91_PIN_PD3, 0); /* CTS3 */
1130 }
1131
1132 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1133 struct platform_device *atmel_default_console_device; /* the serial console device */
1134
1135 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1136 {
1137 struct platform_device *pdev;
1138
1139 switch (id) {
1140 case 0: /* DBGU */
1141 pdev = &at91sam9rl_dbgu_device;
1142 configure_dbgu_pins();
1143 at91_clock_associate("mck", &pdev->dev, "usart");
1144 break;
1145 case AT91SAM9RL_ID_US0:
1146 pdev = &at91sam9rl_uart0_device;
1147 configure_usart0_pins(pins);
1148 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1149 break;
1150 case AT91SAM9RL_ID_US1:
1151 pdev = &at91sam9rl_uart1_device;
1152 configure_usart1_pins(pins);
1153 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1154 break;
1155 case AT91SAM9RL_ID_US2:
1156 pdev = &at91sam9rl_uart2_device;
1157 configure_usart2_pins(pins);
1158 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1159 break;
1160 case AT91SAM9RL_ID_US3:
1161 pdev = &at91sam9rl_uart3_device;
1162 configure_usart3_pins(pins);
1163 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1164 break;
1165 default:
1166 return;
1167 }
1168 pdev->id = portnr; /* update to mapped ID */
1169
1170 if (portnr < ATMEL_MAX_UART)
1171 at91_uarts[portnr] = pdev;
1172 }
1173
1174 void __init at91_set_serial_console(unsigned portnr)
1175 {
1176 if (portnr < ATMEL_MAX_UART)
1177 atmel_default_console_device = at91_uarts[portnr];
1178 }
1179
1180 void __init at91_add_device_serial(void)
1181 {
1182 int i;
1183
1184 for (i = 0; i < ATMEL_MAX_UART; i++) {
1185 if (at91_uarts[i])
1186 platform_device_register(at91_uarts[i]);
1187 }
1188
1189 if (!atmel_default_console_device)
1190 printk(KERN_INFO "AT91: No default serial console defined.\n");
1191 }
1192 #else
1193 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1194 void __init at91_set_serial_console(unsigned portnr) {}
1195 void __init at91_add_device_serial(void) {}
1196 #endif
1197
1198
1199 /* -------------------------------------------------------------------- */
1200
1201 /*
1202 * These devices are always present and don't need any board-specific
1203 * setup.
1204 */
1205 static int __init at91_add_standard_devices(void)
1206 {
1207 at91_add_device_hdmac();
1208 at91_add_device_rtc();
1209 at91_add_device_rtt();
1210 at91_add_device_watchdog();
1211 at91_add_device_tc();
1212 return 0;
1213 }
1214
1215 arch_initcall(at91_add_standard_devices);
Linux for Ginger Game Console