arch/arm/mach-bcmring/include/mach/entry-macro.S

   1 /*****************************************************************************
   2 * Copyright 2006 - 2008 Broadcom Corporation.  All rights reserved.
   3 *
   4 * Unless you and Broadcom execute a separate written software license
   5 * agreement governing use of this software, this software is licensed to you
   6 * under the terms of the GNU General Public License version 2, available at
   7 * http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
   8 *
   9 * Notwithstanding the above, under no circumstances may you combine this
  10 * software in any way with any other Broadcom software provided under a
  11 * license other than the GPL, without Broadcom's express prior written
  12 * consent.
  13 *****************************************************************************/
  14
  15 /*
  16  *
  17  * Low-level IRQ helper macros for BCMRing-based platforms
  18  *
  19  */
  20 #include <mach/irqs.h>
  21 #include <mach/hardware.h>
  22 #include <mach/csp/mm_io.h>
  23
  24                 .macro  disable_fiq
  25                 .endm
  26
  27                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  28                 ldr     \base, =(MM_IO_BASE_INTC0)
  29                 ldr     \irqstat, [\base, #0]           @ get status
  30                 ldr     \irqnr, [\base, #0x10]          @ mask with enable register
  31                 ands    \irqstat, \irqstat, \irqnr
  32                 mov     \irqnr, #IRQ_INTC0_START
  33                 cmp     \irqstat, #0
  34                 bne     1001f
  35
  36                 ldr     \base, =(MM_IO_BASE_INTC1)
  37                 ldr     \irqstat, [\base, #0]           @ get status
  38                 ldr     \irqnr, [\base, #0x10]          @ mask with enable register
  39                 ands    \irqstat, \irqstat, \irqnr
  40                 mov     \irqnr, #IRQ_INTC1_START
  41                 cmp     \irqstat, #0
  42                 bne     1001f
  43
  44                 ldr     \base, =(MM_IO_BASE_SINTC)
  45                 ldr     \irqstat, [\base, #0]           @ get status
  46                 ldr     \irqnr, [\base, #0x10]          @ mask with enable register
  47                 ands    \irqstat, \irqstat, \irqnr
  48                 mov     \irqnr, #0xffffffff             @ code meaning no interrupt bits set
  49                 cmp     \irqstat, #0
  50                 beq     1002f
  51
  52                 mov     \irqnr, #IRQ_SINTC_START        @ something is set, so fixup return value
  53
  54 1001:
  55                 movs    \tmp, \irqstat, lsl #16
  56                 movne   \irqstat, \tmp
  57                 addeq   \irqnr, \irqnr, #16
  58
  59                 movs    \tmp, \irqstat, lsl #8
  60                 movne   \irqstat, \tmp
  61                 addeq   \irqnr, \irqnr, #8
  62
  63                 movs    \tmp, \irqstat, lsl #4
  64                 movne   \irqstat, \tmp
  65                 addeq   \irqnr, \irqnr, #4
  66
  67                 movs    \tmp, \irqstat, lsl #2
  68                 movne   \irqstat, \tmp
  69                 addeq   \irqnr, \irqnr, #2
  70
  71                 movs    \tmp, \irqstat, lsl #1
  72                 addeq   \irqnr, \irqnr, #1
  73                 orrs    \base, \base, #1
  74
  75 1002:           @ irqnr will be set to 0xffffffff if no irq bits are set
  76                 .endm
  77
  78                 .macro  get_irqnr_preamble, base, tmp
  79                 .endm
  80
  81                 .macro  arch_ret_to_user, tmp1, tmp2
  82                 .endm
  83
  84                 .macro  irq_prio_table
  85                 .endm
  86