arch/arm/mach-davinci/dm644x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/gpio.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/dm644x.h>
  21 #include <mach/clock.h>
  22 #include <mach/cputype.h>
  23 #include <mach/edma.h>
  24 #include <mach/irqs.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/time.h>
  28 #include <mach/serial.h>
  29 #include <mach/common.h>
  30 #include <mach/asp.h>
  31
  32 #include "clock.h"
  33 #include "mux.h"
  34
  35 /*
  36  * Device specific clocks
  37  */
  38 #define DM644X_REF_FREQ         27000000
  39
  40 static struct pll_data pll1_data = {
  41         .num       = 1,
  42         .phys_base = DAVINCI_PLL1_BASE,
  43 };
  44
  45 static struct pll_data pll2_data = {
  46         .num       = 2,
  47         .phys_base = DAVINCI_PLL2_BASE,
  48 };
  49
  50 static struct clk ref_clk = {
  51         .name = "ref_clk",
  52         .rate = DM644X_REF_FREQ,
  53 };
  54
  55 static struct clk pll1_clk = {
  56         .name = "pll1",
  57         .parent = &ref_clk,
  58         .pll_data = &pll1_data,
  59         .flags = CLK_PLL,
  60 };
  61
  62 static struct clk pll1_sysclk1 = {
  63         .name = "pll1_sysclk1",
  64         .parent = &pll1_clk,
  65         .flags = CLK_PLL,
  66         .div_reg = PLLDIV1,
  67 };
  68
  69 static struct clk pll1_sysclk2 = {
  70         .name = "pll1_sysclk2",
  71         .parent = &pll1_clk,
  72         .flags = CLK_PLL,
  73         .div_reg = PLLDIV2,
  74 };
  75
  76 static struct clk pll1_sysclk3 = {
  77         .name = "pll1_sysclk3",
  78         .parent = &pll1_clk,
  79         .flags = CLK_PLL,
  80         .div_reg = PLLDIV3,
  81 };
  82
  83 static struct clk pll1_sysclk5 = {
  84         .name = "pll1_sysclk5",
  85         .parent = &pll1_clk,
  86         .flags = CLK_PLL,
  87         .div_reg = PLLDIV5,
  88 };
  89
  90 static struct clk pll1_aux_clk = {
  91         .name = "pll1_aux_clk",
  92         .parent = &pll1_clk,
  93         .flags = CLK_PLL | PRE_PLL,
  94 };
  95
  96 static struct clk pll1_sysclkbp = {
  97         .name = "pll1_sysclkbp",
  98         .parent = &pll1_clk,
  99         .flags = CLK_PLL | PRE_PLL,
 100         .div_reg = BPDIV
 101 };
 102
 103 static struct clk pll2_clk = {
 104         .name = "pll2",
 105         .parent = &ref_clk,
 106         .pll_data = &pll2_data,
 107         .flags = CLK_PLL,
 108 };
 109
 110 static struct clk pll2_sysclk1 = {
 111         .name = "pll2_sysclk1",
 112         .parent = &pll2_clk,
 113         .flags = CLK_PLL,
 114         .div_reg = PLLDIV1,
 115 };
 116
 117 static struct clk pll2_sysclk2 = {
 118         .name = "pll2_sysclk2",
 119         .parent = &pll2_clk,
 120         .flags = CLK_PLL,
 121         .div_reg = PLLDIV2,
 122 };
 123
 124 static struct clk pll2_sysclkbp = {
 125         .name = "pll2_sysclkbp",
 126         .parent = &pll2_clk,
 127         .flags = CLK_PLL | PRE_PLL,
 128         .div_reg = BPDIV
 129 };
 130
 131 static struct clk dsp_clk = {
 132         .name = "dsp",
 133         .parent = &pll1_sysclk1,
 134         .lpsc = DAVINCI_LPSC_GEM,
 135         .flags = PSC_DSP,
 136         .usecount = 1,                  /* REVISIT how to disable? */
 137 };
 138
 139 static struct clk arm_clk = {
 140         .name = "arm",
 141         .parent = &pll1_sysclk2,
 142         .lpsc = DAVINCI_LPSC_ARM,
 143         .flags = ALWAYS_ENABLED,
 144 };
 145
 146 static struct clk vicp_clk = {
 147         .name = "vicp",
 148         .parent = &pll1_sysclk2,
 149         .lpsc = DAVINCI_LPSC_IMCOP,
 150         .flags = PSC_DSP,
 151         .usecount = 1,                  /* REVISIT how to disable? */
 152 };
 153
 154 static struct clk vpss_master_clk = {
 155         .name = "vpss_master",
 156         .parent = &pll1_sysclk3,
 157         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 158         .flags = CLK_PSC,
 159 };
 160
 161 static struct clk vpss_slave_clk = {
 162         .name = "vpss_slave",
 163         .parent = &pll1_sysclk3,
 164         .lpsc = DAVINCI_LPSC_VPSSSLV,
 165 };
 166
 167 static struct clk uart0_clk = {
 168         .name = "uart0",
 169         .parent = &pll1_aux_clk,
 170         .lpsc = DAVINCI_LPSC_UART0,
 171 };
 172
 173 static struct clk uart1_clk = {
 174         .name = "uart1",
 175         .parent = &pll1_aux_clk,
 176         .lpsc = DAVINCI_LPSC_UART1,
 177 };
 178
 179 static struct clk uart2_clk = {
 180         .name = "uart2",
 181         .parent = &pll1_aux_clk,
 182         .lpsc = DAVINCI_LPSC_UART2,
 183 };
 184
 185 static struct clk emac_clk = {
 186         .name = "emac",
 187         .parent = &pll1_sysclk5,
 188         .lpsc = DAVINCI_LPSC_EMAC_WRAPPER,
 189 };
 190
 191 static struct clk i2c_clk = {
 192         .name = "i2c",
 193         .parent = &pll1_aux_clk,
 194         .lpsc = DAVINCI_LPSC_I2C,
 195 };
 196
 197 static struct clk ide_clk = {
 198         .name = "ide",
 199         .parent = &pll1_sysclk5,
 200         .lpsc = DAVINCI_LPSC_ATA,
 201 };
 202
 203 static struct clk asp_clk = {
 204         .name = "asp0",
 205         .parent = &pll1_sysclk5,
 206         .lpsc = DAVINCI_LPSC_McBSP,
 207 };
 208
 209 static struct clk mmcsd_clk = {
 210         .name = "mmcsd",
 211         .parent = &pll1_sysclk5,
 212         .lpsc = DAVINCI_LPSC_MMC_SD,
 213 };
 214
 215 static struct clk spi_clk = {
 216         .name = "spi",
 217         .parent = &pll1_sysclk5,
 218         .lpsc = DAVINCI_LPSC_SPI,
 219 };
 220
 221 static struct clk gpio_clk = {
 222         .name = "gpio",
 223         .parent = &pll1_sysclk5,
 224         .lpsc = DAVINCI_LPSC_GPIO,
 225 };
 226
 227 static struct clk usb_clk = {
 228         .name = "usb",
 229         .parent = &pll1_sysclk5,
 230         .lpsc = DAVINCI_LPSC_USB,
 231 };
 232
 233 static struct clk vlynq_clk = {
 234         .name = "vlynq",
 235         .parent = &pll1_sysclk5,
 236         .lpsc = DAVINCI_LPSC_VLYNQ,
 237 };
 238
 239 static struct clk aemif_clk = {
 240         .name = "aemif",
 241         .parent = &pll1_sysclk5,
 242         .lpsc = DAVINCI_LPSC_AEMIF,
 243 };
 244
 245 static struct clk pwm0_clk = {
 246         .name = "pwm0",
 247         .parent = &pll1_aux_clk,
 248         .lpsc = DAVINCI_LPSC_PWM0,
 249 };
 250
 251 static struct clk pwm1_clk = {
 252         .name = "pwm1",
 253         .parent = &pll1_aux_clk,
 254         .lpsc = DAVINCI_LPSC_PWM1,
 255 };
 256
 257 static struct clk pwm2_clk = {
 258         .name = "pwm2",
 259         .parent = &pll1_aux_clk,
 260         .lpsc = DAVINCI_LPSC_PWM2,
 261 };
 262
 263 static struct clk timer0_clk = {
 264         .name = "timer0",
 265         .parent = &pll1_aux_clk,
 266         .lpsc = DAVINCI_LPSC_TIMER0,
 267 };
 268
 269 static struct clk timer1_clk = {
 270         .name = "timer1",
 271         .parent = &pll1_aux_clk,
 272         .lpsc = DAVINCI_LPSC_TIMER1,
 273 };
 274
 275 static struct clk timer2_clk = {
 276         .name = "timer2",
 277         .parent = &pll1_aux_clk,
 278         .lpsc = DAVINCI_LPSC_TIMER2,
 279         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 280 };
 281
 282 struct davinci_clk dm644x_clks[] = {
 283         CLK(NULL, "ref", &ref_clk),
 284         CLK(NULL, "pll1", &pll1_clk),
 285         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 286         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 287         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 288         CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
 289         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 290         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 291         CLK(NULL, "pll2", &pll2_clk),
 292         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 293         CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
 294         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 295         CLK(NULL, "dsp", &dsp_clk),
 296         CLK(NULL, "arm", &arm_clk),
 297         CLK(NULL, "vicp", &vicp_clk),
 298         CLK(NULL, "vpss_master", &vpss_master_clk),
 299         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 300         CLK(NULL, "arm", &arm_clk),
 301         CLK(NULL, "uart0", &uart0_clk),
 302         CLK(NULL, "uart1", &uart1_clk),
 303         CLK(NULL, "uart2", &uart2_clk),
 304         CLK("davinci_emac.1", NULL, &emac_clk),
 305         CLK("i2c_davinci.1", NULL, &i2c_clk),
 306         CLK("palm_bk3710", NULL, &ide_clk),
 307         CLK("davinci-asp", NULL, &asp_clk),
 308         CLK("davinci_mmc.0", NULL, &mmcsd_clk),
 309         CLK(NULL, "spi", &spi_clk),
 310         CLK(NULL, "gpio", &gpio_clk),
 311         CLK(NULL, "usb", &usb_clk),
 312         CLK(NULL, "vlynq", &vlynq_clk),
 313         CLK(NULL, "aemif", &aemif_clk),
 314         CLK(NULL, "pwm0", &pwm0_clk),
 315         CLK(NULL, "pwm1", &pwm1_clk),
 316         CLK(NULL, "pwm2", &pwm2_clk),
 317         CLK(NULL, "timer0", &timer0_clk),
 318         CLK(NULL, "timer1", &timer1_clk),
 319         CLK("watchdog", NULL, &timer2_clk),
 320         CLK(NULL, NULL, NULL),
 321 };
 322
 323 static struct emac_platform_data dm644x_emac_pdata = {
 324         .ctrl_reg_offset        = DM644X_EMAC_CNTRL_OFFSET,
 325         .ctrl_mod_reg_offset    = DM644X_EMAC_CNTRL_MOD_OFFSET,
 326         .ctrl_ram_offset        = DM644X_EMAC_CNTRL_RAM_OFFSET,
 327         .mdio_reg_offset        = DM644X_EMAC_MDIO_OFFSET,
 328         .ctrl_ram_size          = DM644X_EMAC_CNTRL_RAM_SIZE,
 329         .version                = EMAC_VERSION_1,
 330 };
 331
 332 static struct resource dm644x_emac_resources[] = {
 333         {
 334                 .start  = DM644X_EMAC_BASE,
 335                 .end    = DM644X_EMAC_BASE + 0x47ff,
 336                 .flags  = IORESOURCE_MEM,
 337         },
 338         {
 339                 .start = IRQ_EMACINT,
 340                 .end   = IRQ_EMACINT,
 341                 .flags = IORESOURCE_IRQ,
 342         },
 343 };
 344
 345 static struct platform_device dm644x_emac_device = {
 346        .name            = "davinci_emac",
 347        .id              = 1,
 348        .dev = {
 349                .platform_data   = &dm644x_emac_pdata,
 350        },
 351        .num_resources   = ARRAY_SIZE(dm644x_emac_resources),
 352        .resource        = dm644x_emac_resources,
 353 };
 354
 355 #define PINMUX0         0x00
 356 #define PINMUX1         0x04
 357
 358 /*
 359  * Device specific mux setup
 360  *
 361  *      soc     description     mux  mode   mode  mux    dbg
 362  *                              reg  offset mask  mode
 363  */
 364 static const struct mux_config dm644x_pins[] = {
 365 #ifdef CONFIG_DAVINCI_MUX
 366 MUX_CFG(DM644X, HDIREN,         0,   16,    1,    1,     true)
 367 MUX_CFG(DM644X, ATAEN,          0,   17,    1,    1,     true)
 368 MUX_CFG(DM644X, ATAEN_DISABLE,  0,   17,    1,    0,     true)
 369
 370 MUX_CFG(DM644X, HPIEN_DISABLE,  0,   29,    1,    0,     true)
 371
 372 MUX_CFG(DM644X, AEAW,           0,   0,     31,   31,    true)
 373
 374 MUX_CFG(DM644X, MSTK,           1,   9,     1,    0,     false)
 375
 376 MUX_CFG(DM644X, I2C,            1,   7,     1,    1,     false)
 377
 378 MUX_CFG(DM644X, MCBSP,          1,   10,    1,    1,     false)
 379
 380 MUX_CFG(DM644X, UART1,          1,   1,     1,    1,     true)
 381 MUX_CFG(DM644X, UART2,          1,   2,     1,    1,     true)
 382
 383 MUX_CFG(DM644X, PWM0,           1,   4,     1,    1,     false)
 384
 385 MUX_CFG(DM644X, PWM1,           1,   5,     1,    1,     false)
 386
 387 MUX_CFG(DM644X, PWM2,           1,   6,     1,    1,     false)
 388
 389 MUX_CFG(DM644X, VLYNQEN,        0,   15,    1,    1,     false)
 390 MUX_CFG(DM644X, VLSCREN,        0,   14,    1,    1,     false)
 391 MUX_CFG(DM644X, VLYNQWD,        0,   12,    3,    3,     false)
 392
 393 MUX_CFG(DM644X, EMACEN,         0,   31,    1,    1,     true)
 394
 395 MUX_CFG(DM644X, GPIO3V,         0,   31,    1,    0,     true)
 396
 397 MUX_CFG(DM644X, GPIO0,          0,   24,    1,    0,     true)
 398 MUX_CFG(DM644X, GPIO3,          0,   25,    1,    0,     false)
 399 MUX_CFG(DM644X, GPIO43_44,      1,   7,     1,    0,     false)
 400 MUX_CFG(DM644X, GPIO46_47,      0,   22,    1,    0,     true)
 401
 402 MUX_CFG(DM644X, RGB666,         0,   22,    1,    1,     true)
 403
 404 MUX_CFG(DM644X, LOEEN,          0,   24,    1,    1,     true)
 405 MUX_CFG(DM644X, LFLDEN,         0,   25,    1,    1,     false)
 406 #endif
 407 };
 408
 409 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
 410 static u8 dm644x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 411         [IRQ_VDINT0]            = 2,
 412         [IRQ_VDINT1]            = 6,
 413         [IRQ_VDINT2]            = 6,
 414         [IRQ_HISTINT]           = 6,
 415         [IRQ_H3AINT]            = 6,
 416         [IRQ_PRVUINT]           = 6,
 417         [IRQ_RSZINT]            = 6,
 418         [7]                     = 7,
 419         [IRQ_VENCINT]           = 6,
 420         [IRQ_ASQINT]            = 6,
 421         [IRQ_IMXINT]            = 6,
 422         [IRQ_VLCDINT]           = 6,
 423         [IRQ_USBINT]            = 4,
 424         [IRQ_EMACINT]           = 4,
 425         [14]                    = 7,
 426         [15]                    = 7,
 427         [IRQ_CCINT0]            = 5,    /* dma */
 428         [IRQ_CCERRINT]          = 5,    /* dma */
 429         [IRQ_TCERRINT0]         = 5,    /* dma */
 430         [IRQ_TCERRINT]          = 5,    /* dma */
 431         [IRQ_PSCIN]             = 7,
 432         [21]                    = 7,
 433         [IRQ_IDE]               = 4,
 434         [23]                    = 7,
 435         [IRQ_MBXINT]            = 7,
 436         [IRQ_MBRINT]            = 7,
 437         [IRQ_MMCINT]            = 7,
 438         [IRQ_SDIOINT]           = 7,
 439         [28]                    = 7,
 440         [IRQ_DDRINT]            = 7,
 441         [IRQ_AEMIFINT]          = 7,
 442         [IRQ_VLQINT]            = 4,
 443         [IRQ_TINT0_TINT12]      = 2,    /* clockevent */
 444         [IRQ_TINT0_TINT34]      = 2,    /* clocksource */
 445         [IRQ_TINT1_TINT12]      = 7,    /* DSP timer */
 446         [IRQ_TINT1_TINT34]      = 7,    /* system tick */
 447         [IRQ_PWMINT0]           = 7,
 448         [IRQ_PWMINT1]           = 7,
 449         [IRQ_PWMINT2]           = 7,
 450         [IRQ_I2C]               = 3,
 451         [IRQ_UARTINT0]          = 3,
 452         [IRQ_UARTINT1]          = 3,
 453         [IRQ_UARTINT2]          = 3,
 454         [IRQ_SPINT0]            = 3,
 455         [IRQ_SPINT1]            = 3,
 456         [45]                    = 7,
 457         [IRQ_DSP2ARM0]          = 4,
 458         [IRQ_DSP2ARM1]          = 4,
 459         [IRQ_GPIO0]             = 7,
 460         [IRQ_GPIO1]             = 7,
 461         [IRQ_GPIO2]             = 7,
 462         [IRQ_GPIO3]             = 7,
 463         [IRQ_GPIO4]             = 7,
 464         [IRQ_GPIO5]             = 7,
 465         [IRQ_GPIO6]             = 7,
 466         [IRQ_GPIO7]             = 7,
 467         [IRQ_GPIOBNK0]          = 7,
 468         [IRQ_GPIOBNK1]          = 7,
 469         [IRQ_GPIOBNK2]          = 7,
 470         [IRQ_GPIOBNK3]          = 7,
 471         [IRQ_GPIOBNK4]          = 7,
 472         [IRQ_COMMTX]            = 7,
 473         [IRQ_COMMRX]            = 7,
 474         [IRQ_EMUINT]            = 7,
 475 };
 476
 477 /*----------------------------------------------------------------------*/
 478
 479 static const s8 dma_chan_dm644x_no_event[] = {
 480          0,  1, 12, 13, 14,
 481         15, 25, 30, 31, 45,
 482         46, 47, 55, 56, 57,
 483         58, 59, 60, 61, 62,
 484         63,
 485         -1
 486 };
 487
 488 static const s8
 489 queue_tc_mapping[][2] = {
 490         /* {event queue no, TC no} */
 491         {0, 0},
 492         {1, 1},
 493         {-1, -1},
 494 };
 495
 496 static const s8
 497 queue_priority_mapping[][2] = {
 498         /* {event queue no, Priority} */
 499         {0, 3},
 500         {1, 7},
 501         {-1, -1},
 502 };
 503
 504 static struct edma_soc_info dm644x_edma_info[] = {
 505         {
 506                 .n_channel              = 64,
 507                 .n_region               = 4,
 508                 .n_slot                 = 128,
 509                 .n_tc                   = 2,
 510                 .n_cc                   = 1,
 511                 .noevent                = dma_chan_dm644x_no_event,
 512                 .queue_tc_mapping       = queue_tc_mapping,
 513                 .queue_priority_mapping = queue_priority_mapping,
 514         },
 515 };
 516
 517 static struct resource edma_resources[] = {
 518         {
 519                 .name   = "edma_cc0",
 520                 .start  = 0x01c00000,
 521                 .end    = 0x01c00000 + SZ_64K - 1,
 522                 .flags  = IORESOURCE_MEM,
 523         },
 524         {
 525                 .name   = "edma_tc0",
 526                 .start  = 0x01c10000,
 527                 .end    = 0x01c10000 + SZ_1K - 1,
 528                 .flags  = IORESOURCE_MEM,
 529         },
 530         {
 531                 .name   = "edma_tc1",
 532                 .start  = 0x01c10400,
 533                 .end    = 0x01c10400 + SZ_1K - 1,
 534                 .flags  = IORESOURCE_MEM,
 535         },
 536         {
 537                 .name   = "edma0",
 538                 .start  = IRQ_CCINT0,
 539                 .flags  = IORESOURCE_IRQ,
 540         },
 541         {
 542                 .name   = "edma0_err",
 543                 .start  = IRQ_CCERRINT,
 544                 .flags  = IORESOURCE_IRQ,
 545         },
 546         /* not using TC*_ERR */
 547 };
 548
 549 static struct platform_device dm644x_edma_device = {
 550         .name                   = "edma",
 551         .id                     = 0,
 552         .dev.platform_data      = dm644x_edma_info,
 553         .num_resources          = ARRAY_SIZE(edma_resources),
 554         .resource               = edma_resources,
 555 };
 556
 557 /* DM6446 EVM uses ASP0; line-out is a pair of RCA jacks */
 558 static struct resource dm644x_asp_resources[] = {
 559         {
 560                 .start  = DAVINCI_ASP0_BASE,
 561                 .end    = DAVINCI_ASP0_BASE + SZ_8K - 1,
 562                 .flags  = IORESOURCE_MEM,
 563         },
 564         {
 565                 .start  = DAVINCI_DMA_ASP0_TX,
 566                 .end    = DAVINCI_DMA_ASP0_TX,
 567                 .flags  = IORESOURCE_DMA,
 568         },
 569         {
 570                 .start  = DAVINCI_DMA_ASP0_RX,
 571                 .end    = DAVINCI_DMA_ASP0_RX,
 572                 .flags  = IORESOURCE_DMA,
 573         },
 574 };
 575
 576 static struct platform_device dm644x_asp_device = {
 577         .name           = "davinci-asp",
 578         .id             = -1,
 579         .num_resources  = ARRAY_SIZE(dm644x_asp_resources),
 580         .resource       = dm644x_asp_resources,
 581 };
 582
 583 static struct resource dm644x_vpss_resources[] = {
 584         {
 585                 /* VPSS Base address */
 586                 .name           = "vpss",
 587                 .start          = 0x01c73400,
 588                 .end            = 0x01c73400 + 0xff,
 589                 .flags          = IORESOURCE_MEM,
 590         },
 591 };
 592
 593 static struct platform_device dm644x_vpss_device = {
 594         .name                   = "vpss",
 595         .id                     = -1,
 596         .dev.platform_data      = "dm644x_vpss",
 597         .num_resources          = ARRAY_SIZE(dm644x_vpss_resources),
 598         .resource               = dm644x_vpss_resources,
 599 };
 600
 601 static struct resource vpfe_resources[] = {
 602         {
 603                 .start          = IRQ_VDINT0,
 604                 .end            = IRQ_VDINT0,
 605                 .flags          = IORESOURCE_IRQ,
 606         },
 607         {
 608                 .start          = IRQ_VDINT1,
 609                 .end            = IRQ_VDINT1,
 610                 .flags          = IORESOURCE_IRQ,
 611         },
 612         {
 613                 .start          = 0x01c70400,
 614                 .end            = 0x01c70400 + 0xff,
 615                 .flags          = IORESOURCE_MEM,
 616         },
 617 };
 618
 619 static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32);
 620 static struct platform_device vpfe_capture_dev = {
 621         .name           = CAPTURE_DRV_NAME,
 622         .id             = -1,
 623         .num_resources  = ARRAY_SIZE(vpfe_resources),
 624         .resource       = vpfe_resources,
 625         .dev = {
 626                 .dma_mask               = &vpfe_capture_dma_mask,
 627                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 628         },
 629 };
 630
 631 void dm644x_set_vpfe_config(struct vpfe_config *cfg)
 632 {
 633         vpfe_capture_dev.dev.platform_data = cfg;
 634 }
 635
 636 /*----------------------------------------------------------------------*/
 637
 638 static struct map_desc dm644x_io_desc[] = {
 639         {
 640                 .virtual        = IO_VIRT,
 641                 .pfn            = __phys_to_pfn(IO_PHYS),
 642                 .length         = IO_SIZE,
 643                 .type           = MT_DEVICE
 644         },
 645         {
 646                 .virtual        = SRAM_VIRT,
 647                 .pfn            = __phys_to_pfn(0x00008000),
 648                 .length         = SZ_16K,
 649                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 650                 .type           = MT_DEVICE,
 651         },
 652 };
 653
 654 /* Contents of JTAG ID register used to identify exact cpu type */
 655 static struct davinci_id dm644x_ids[] = {
 656         {
 657                 .variant        = 0x0,
 658                 .part_no        = 0xb700,
 659                 .manufacturer   = 0x017,
 660                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 661                 .name           = "dm6446",
 662         },
 663         {
 664                 .variant        = 0x1,
 665                 .part_no        = 0xb700,
 666                 .manufacturer   = 0x017,
 667                 .cpu_id         = DAVINCI_CPU_ID_DM6446,
 668                 .name           = "dm6446a",
 669         },
 670 };
 671
 672 static void __iomem *dm644x_psc_bases[] = {
 673         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 674 };
 675
 676 /*
 677  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 678  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 679  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 680  * T1_TOP: Timer 1, top   :  <unused>
 681  */
 682 struct davinci_timer_info dm644x_timer_info = {
 683         .timers         = davinci_timer_instance,
 684         .clockevent_id  = T0_BOT,
 685         .clocksource_id = T0_TOP,
 686 };
 687
 688 static struct plat_serial8250_port dm644x_serial_platform_data[] = {
 689         {
 690                 .mapbase        = DAVINCI_UART0_BASE,
 691                 .irq            = IRQ_UARTINT0,
 692                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 693                                   UPF_IOREMAP,
 694                 .iotype         = UPIO_MEM,
 695                 .regshift       = 2,
 696         },
 697         {
 698                 .mapbase        = DAVINCI_UART1_BASE,
 699                 .irq            = IRQ_UARTINT1,
 700                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 701                                   UPF_IOREMAP,
 702                 .iotype         = UPIO_MEM,
 703                 .regshift       = 2,
 704         },
 705         {
 706                 .mapbase        = DAVINCI_UART2_BASE,
 707                 .irq            = IRQ_UARTINT2,
 708                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 709                                   UPF_IOREMAP,
 710                 .iotype         = UPIO_MEM,
 711                 .regshift       = 2,
 712         },
 713         {
 714                 .flags          = 0
 715         },
 716 };
 717
 718 static struct platform_device dm644x_serial_device = {
 719         .name                   = "serial8250",
 720         .id                     = PLAT8250_DEV_PLATFORM,
 721         .dev                    = {
 722                 .platform_data  = dm644x_serial_platform_data,
 723         },
 724 };
 725
 726 static struct davinci_soc_info davinci_soc_info_dm644x = {
 727         .io_desc                = dm644x_io_desc,
 728         .io_desc_num            = ARRAY_SIZE(dm644x_io_desc),
 729         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 730         .ids                    = dm644x_ids,
 731         .ids_num                = ARRAY_SIZE(dm644x_ids),
 732         .cpu_clks               = dm644x_clks,
 733         .psc_bases              = dm644x_psc_bases,
 734         .psc_bases_num          = ARRAY_SIZE(dm644x_psc_bases),
 735         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 736         .pinmux_pins            = dm644x_pins,
 737         .pinmux_pins_num        = ARRAY_SIZE(dm644x_pins),
 738         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 739         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 740         .intc_irq_prios         = dm644x_default_priorities,
 741         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 742         .timer_info             = &dm644x_timer_info,
 743         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 744         .gpio_num               = 71,
 745         .gpio_irq               = IRQ_GPIOBNK0,
 746         .serial_dev             = &dm644x_serial_device,
 747         .emac_pdata             = &dm644x_emac_pdata,
 748         .sram_dma               = 0x00008000,
 749         .sram_len               = SZ_16K,
 750 };
 751
 752 void __init dm644x_init_asp(struct snd_platform_data *pdata)
 753 {
 754         davinci_cfg_reg(DM644X_MCBSP);
 755         dm644x_asp_device.dev.platform_data = pdata;
 756         platform_device_register(&dm644x_asp_device);
 757 }
 758
 759 void __init dm644x_init(void)
 760 {
 761         davinci_common_init(&davinci_soc_info_dm644x);
 762 }
 763
 764 static int __init dm644x_init_devices(void)
 765 {
 766         if (!cpu_is_davinci_dm644x())
 767                 return 0;
 768
 769         platform_device_register(&dm644x_edma_device);
 770         platform_device_register(&dm644x_emac_device);
 771         platform_device_register(&dm644x_vpss_device);
 772         platform_device_register(&vpfe_capture_dev);
 773
 774         return 0;
 775 }
 776 postcore_initcall(dm644x_init_devices);