arch/arm/mach-w90x900/time.c

   1 /*
   2  * linux/arch/arm/mach-w90x900/time.c
   3  *
   4  * Based on linux/arch/arm/plat-s3c24xx/time.c by Ben Dooks
   5  *
   6  * Copyright (c) 2009 Nuvoton technology corporation
   7  * All rights reserved.
   8  *
   9  * Wan ZongShun <mcuos.com@gmail.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation; either version 2 of the License, or
  14  * (at your option) any later version.
  15  *
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/sched.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/err.h>
  23 #include <linux/clk.h>
  24 #include <linux/io.h>
  25 #include <linux/leds.h>
  26 #include <linux/clocksource.h>
  27 #include <linux/clockchips.h>
  28
  29 #include <asm/mach-types.h>
  30 #include <asm/mach/irq.h>
  31 #include <asm/mach/time.h>
  32
  33 #include <mach/map.h>
  34 #include <mach/regs-timer.h>
  35
  36 #define RESETINT        0x1f
  37 #define PERIOD          (0x01 << 27)
  38 #define ONESHOT         (0x00 << 27)
  39 #define COUNTEN         (0x01 << 30)
  40 #define INTEN           (0x01 << 29)
  41
  42 #define TICKS_PER_SEC   100
  43 #define PRESCALE        0x63 /* Divider = prescale + 1 */
  44
  45 unsigned int timer0_load;
  46
  47 static void nuc900_clockevent_setmode(enum clock_event_mode mode,
  48                 struct clock_event_device *clk)
  49 {
  50         unsigned int val;
  51
  52         val = __raw_readl(REG_TCSR0);
  53         val &= ~(0x03 << 27);
  54
  55         switch (mode) {
  56         case CLOCK_EVT_MODE_PERIODIC:
  57                 __raw_writel(timer0_load, REG_TICR0);
  58                 val |= (PERIOD | COUNTEN | INTEN | PRESCALE);
  59                 break;
  60
  61         case CLOCK_EVT_MODE_ONESHOT:
  62                 val |= (ONESHOT | COUNTEN | INTEN | PRESCALE);
  63                 break;
  64
  65         case CLOCK_EVT_MODE_UNUSED:
  66         case CLOCK_EVT_MODE_SHUTDOWN:
  67         case CLOCK_EVT_MODE_RESUME:
  68                 break;
  69         }
  70
  71         __raw_writel(val, REG_TCSR0);
  72 }
  73
  74 static int nuc900_clockevent_setnextevent(unsigned long evt,
  75                 struct clock_event_device *clk)
  76 {
  77         unsigned int val;
  78
  79         __raw_writel(evt, REG_TICR0);
  80
  81         val = __raw_readl(REG_TCSR0);
  82         val |= (COUNTEN | INTEN | PRESCALE);
  83         __raw_writel(val, REG_TCSR0);
  84
  85         return 0;
  86 }
  87
  88 static struct clock_event_device nuc900_clockevent_device = {
  89         .name           = "nuc900-timer0",
  90         .shift          = 32,
  91         .features       = CLOCK_EVT_MODE_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
  92         .set_mode       = nuc900_clockevent_setmode,
  93         .set_next_event = nuc900_clockevent_setnextevent,
  94         .rating         = 300,
  95 };
  96
  97 /*IRQ handler for the timer*/
  98
  99 static irqreturn_t nuc900_timer0_interrupt(int irq, void *dev_id)
 100 {
 101         struct clock_event_device *evt = &nuc900_clockevent_device;
 102
 103         __raw_writel(0x01, REG_TISR); /* clear TIF0 */
 104
 105         evt->event_handler(evt);
 106         return IRQ_HANDLED;
 107 }
 108
 109 static struct irqaction nuc900_timer0_irq = {
 110         .name           = "nuc900-timer0",
 111         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 112         .handler        = nuc900_timer0_interrupt,
 113 };
 114
 115 static void __init nuc900_clockevents_init(unsigned int rate)
 116 {
 117         nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
 118                                         nuc900_clockevent_device.shift);
 119         nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
 120                                         &nuc900_clockevent_device);
 121         nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
 122                                         &nuc900_clockevent_device);
 123         nuc900_clockevent_device.cpumask = cpumask_of(0);
 124
 125         clockevents_register_device(&nuc900_clockevent_device);
 126 }
 127
 128 static cycle_t nuc900_get_cycles(struct clocksource *cs)
 129 {
 130         return ~__raw_readl(REG_TDR1);
 131 }
 132
 133 static struct clocksource clocksource_nuc900 = {
 134         .name   = "nuc900-timer1",
 135         .rating = 200,
 136         .read   = nuc900_get_cycles,
 137         .mask   = CLOCKSOURCE_MASK(32),
 138         .shift  = 20,
 139         .flags  = CLOCK_SOURCE_IS_CONTINUOUS,
 140 };
 141
 142 static void __init nuc900_clocksource_init(unsigned int rate)
 143 {
 144         unsigned int val;
 145
 146         __raw_writel(0xffffffff, REG_TICR1);
 147
 148         val = __raw_readl(REG_TCSR1);
 149         val |= (COUNTEN | PERIOD);
 150         __raw_writel(val, REG_TCSR1);
 151
 152         clocksource_nuc900.mult =
 153                 clocksource_khz2mult((rate / 1000), clocksource_nuc900.shift);
 154         clocksource_register(&clocksource_nuc900);
 155 }
 156
 157 static void __init nuc900_timer_init(void)
 158 {
 159         struct clk *ck_ext = clk_get(NULL, "ext");
 160         unsigned int    rate;
 161
 162         BUG_ON(IS_ERR(ck_ext));
 163
 164         rate = clk_get_rate(ck_ext);
 165         clk_put(ck_ext);
 166         rate = rate / (PRESCALE + 0x01);
 167
 168          /* set a known state */
 169         __raw_writel(0x00, REG_TCSR0);
 170         __raw_writel(0x00, REG_TCSR1);
 171         __raw_writel(RESETINT, REG_TISR);
 172         timer0_load = (rate / TICKS_PER_SEC);
 173
 174         setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
 175
 176         nuc900_clocksource_init(rate);
 177         nuc900_clockevents_init(rate);
 178 }
 179
 180 struct sys_timer nuc900_timer = {
 181         .init           = nuc900_timer_init,
 182 };