arch/arm/plat-mxc/clock.c

   1 /*
   2  * Based on arch/arm/plat-omap/clock.c
   3  *
   4  * Copyright (C) 2004 - 2005 Nokia corporation
   5  * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
   7  * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
   8  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License
  12  * as published by the Free Software Foundation; either version 2
  13  * of the License, or (at your option) any later version.
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  22  * MA  02110-1301, USA.
  23  */
  24
  25 /* #define DEBUG */
  26
  27 #include <linux/clk.h>
  28 #include <linux/err.h>
  29 #include <linux/errno.h>
  30 #include <linux/init.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/module.h>
  35 #include <linux/mutex.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/proc_fs.h>
  38 #include <linux/semaphore.h>
  39 #include <linux/string.h>
  40
  41 #include <mach/clock.h>
  42 #include <mach/hardware.h>
  43
  44 static LIST_HEAD(clocks);
  45 static DEFINE_MUTEX(clocks_mutex);
  46
  47 /*-------------------------------------------------------------------------
  48  * Standard clock functions defined in include/linux/clk.h
  49  *-------------------------------------------------------------------------*/
  50
  51 static void __clk_disable(struct clk *clk)
  52 {
  53         if (clk == NULL || IS_ERR(clk))
  54                 return;
  55
  56         __clk_disable(clk->parent);
  57         __clk_disable(clk->secondary);
  58
  59         if (!(--clk->usecount) && clk->disable)
  60                 clk->disable(clk);
  61 }
  62
  63 static int __clk_enable(struct clk *clk)
  64 {
  65         if (clk == NULL || IS_ERR(clk))
  66                 return -EINVAL;
  67
  68         __clk_enable(clk->parent);
  69         __clk_enable(clk->secondary);
  70
  71         if (clk->usecount++ == 0 && clk->enable)
  72                 clk->enable(clk);
  73
  74         return 0;
  75 }
  76
  77 /* This function increments the reference count on the clock and enables the
  78  * clock if not already enabled. The parent clock tree is recursively enabled
  79  */
  80 int clk_enable(struct clk *clk)
  81 {
  82         int ret = 0;
  83
  84         if (clk == NULL || IS_ERR(clk))
  85                 return -EINVAL;
  86
  87         mutex_lock(&clocks_mutex);
  88         ret = __clk_enable(clk);
  89         mutex_unlock(&clocks_mutex);
  90
  91         return ret;
  92 }
  93 EXPORT_SYMBOL(clk_enable);
  94
  95 /* This function decrements the reference count on the clock and disables
  96  * the clock when reference count is 0. The parent clock tree is
  97  * recursively disabled
  98  */
  99 void clk_disable(struct clk *clk)
 100 {
 101         if (clk == NULL || IS_ERR(clk))
 102                 return;
 103
 104         mutex_lock(&clocks_mutex);
 105         __clk_disable(clk);
 106         mutex_unlock(&clocks_mutex);
 107 }
 108 EXPORT_SYMBOL(clk_disable);
 109
 110 /* Retrieve the *current* clock rate. If the clock itself
 111  * does not provide a special calculation routine, ask
 112  * its parent and so on, until one is able to return
 113  * a valid clock rate
 114  */
 115 unsigned long clk_get_rate(struct clk *clk)
 116 {
 117         if (clk == NULL || IS_ERR(clk))
 118                 return 0UL;
 119
 120         if (clk->get_rate)
 121                 return clk->get_rate(clk);
 122
 123         return clk_get_rate(clk->parent);
 124 }
 125 EXPORT_SYMBOL(clk_get_rate);
 126
 127 /* Round the requested clock rate to the nearest supported
 128  * rate that is less than or equal to the requested rate.
 129  * This is dependent on the clock's current parent.
 130  */
 131 long clk_round_rate(struct clk *clk, unsigned long rate)
 132 {
 133         if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
 134                 return 0;
 135
 136         return clk->round_rate(clk, rate);
 137 }
 138 EXPORT_SYMBOL(clk_round_rate);
 139
 140 /* Set the clock to the requested clock rate. The rate must
 141  * match a supported rate exactly based on what clk_round_rate returns
 142  */
 143 int clk_set_rate(struct clk *clk, unsigned long rate)
 144 {
 145         int ret = -EINVAL;
 146
 147         if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
 148                 return ret;
 149
 150         mutex_lock(&clocks_mutex);
 151         ret = clk->set_rate(clk, rate);
 152         mutex_unlock(&clocks_mutex);
 153
 154         return ret;
 155 }
 156 EXPORT_SYMBOL(clk_set_rate);
 157
 158 /* Set the clock's parent to another clock source */
 159 int clk_set_parent(struct clk *clk, struct clk *parent)
 160 {
 161         int ret = -EINVAL;
 162
 163         if (clk == NULL || IS_ERR(clk) || parent == NULL ||
 164             IS_ERR(parent) || clk->set_parent == NULL)
 165                 return ret;
 166
 167         mutex_lock(&clocks_mutex);
 168         ret = clk->set_parent(clk, parent);
 169         if (ret == 0)
 170                 clk->parent = parent;
 171         mutex_unlock(&clocks_mutex);
 172
 173         return ret;
 174 }
 175 EXPORT_SYMBOL(clk_set_parent);
 176
 177 /* Retrieve the clock's parent clock source */
 178 struct clk *clk_get_parent(struct clk *clk)
 179 {
 180         struct clk *ret = NULL;
 181
 182         if (clk == NULL || IS_ERR(clk))
 183                 return ret;
 184
 185         return clk->parent;
 186 }
 187 EXPORT_SYMBOL(clk_get_parent);
 188
 189 /*
 190  * Get the resulting clock rate from a PLL register value and the input
 191  * frequency. PLLs with this register layout can at least be found on
 192  * MX1, MX21, MX27 and MX31
 193  *
 194  *                  mfi + mfn / (mfd + 1)
 195  *  f = 2 * f_ref * --------------------
 196  *                        pd + 1
 197  */
 198 unsigned long mxc_decode_pll(unsigned int reg_val, u32 freq)
 199 {
 200         long long ll;
 201         int mfn_abs;
 202         unsigned int mfi, mfn, mfd, pd;
 203
 204         mfi = (reg_val >> 10) & 0xf;
 205         mfn = reg_val & 0x3ff;
 206         mfd = (reg_val >> 16) & 0x3ff;
 207         pd =  (reg_val >> 26) & 0xf;
 208
 209         mfi = mfi <= 5 ? 5 : mfi;
 210
 211         mfn_abs = mfn;
 212
 213         /* On all i.MXs except i.MX1 and i.MX21 mfn is a 10bit
 214          * 2's complements number
 215          */
 216         if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
 217                 mfn_abs = 0x400 - mfn;
 218
 219         freq *= 2;
 220         freq /= pd + 1;
 221
 222         ll = (unsigned long long)freq * mfn_abs;
 223
 224         do_div(ll, mfd + 1);
 225
 226         if (!cpu_is_mx1() && !cpu_is_mx21() && mfn >= 0x200)
 227                 ll = -ll;
 228
 229         ll = (freq * mfi) + ll;
 230
 231         return ll;
 232 }