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ALSA: ASoC: TLV320AIC3X: Modify only interface related bits in aic3x_set_dai_fmt
[linux-ginger.git] / drivers / net / cpmac.c
blob7f3f62e1b1134f2c816770f61fcc4dd0d54139b7
1 /*
2 * Copyright (C) 2006, 2007 Eugene Konev
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
17 */
18
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/moduleparam.h>
22
23 #include <linux/sched.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/errno.h>
27 #include <linux/types.h>
28 #include <linux/delay.h>
29 #include <linux/version.h>
30
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/skbuff.h>
35 #include <linux/mii.h>
36 #include <linux/phy.h>
37 #include <linux/phy_fixed.h>
38 #include <linux/platform_device.h>
39 #include <linux/dma-mapping.h>
40 #include <asm/gpio.h>
41 #include <asm/atomic.h>
42
43 MODULE_AUTHOR("Eugene Konev <ejka@imfi.kspu.ru>");
44 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
45 MODULE_LICENSE("GPL");
46 MODULE_ALIAS("platform:cpmac");
47
48 static int debug_level = 8;
49 static int dumb_switch;
50
51 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
52 module_param(debug_level, int, 0444);
53 module_param(dumb_switch, int, 0444);
54
55 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
56 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
57
58 #define CPMAC_VERSION "0.5.0"
59 /* frame size + 802.1q tag */
60 #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4)
61 #define CPMAC_QUEUES 8
62
63 /* Ethernet registers */
64 #define CPMAC_TX_CONTROL 0x0004
65 #define CPMAC_TX_TEARDOWN 0x0008
66 #define CPMAC_RX_CONTROL 0x0014
67 #define CPMAC_RX_TEARDOWN 0x0018
68 #define CPMAC_MBP 0x0100
69 # define MBP_RXPASSCRC 0x40000000
70 # define MBP_RXQOS 0x20000000
71 # define MBP_RXNOCHAIN 0x10000000
72 # define MBP_RXCMF 0x01000000
73 # define MBP_RXSHORT 0x00800000
74 # define MBP_RXCEF 0x00400000
75 # define MBP_RXPROMISC 0x00200000
76 # define MBP_PROMISCCHAN(channel) (((channel) & 0x7) << 16)
77 # define MBP_RXBCAST 0x00002000
78 # define MBP_BCASTCHAN(channel) (((channel) & 0x7) << 8)
79 # define MBP_RXMCAST 0x00000020
80 # define MBP_MCASTCHAN(channel) ((channel) & 0x7)
81 #define CPMAC_UNICAST_ENABLE 0x0104
82 #define CPMAC_UNICAST_CLEAR 0x0108
83 #define CPMAC_MAX_LENGTH 0x010c
84 #define CPMAC_BUFFER_OFFSET 0x0110
85 #define CPMAC_MAC_CONTROL 0x0160
86 # define MAC_TXPTYPE 0x00000200
87 # define MAC_TXPACE 0x00000040
88 # define MAC_MII 0x00000020
89 # define MAC_TXFLOW 0x00000010
90 # define MAC_RXFLOW 0x00000008
91 # define MAC_MTEST 0x00000004
92 # define MAC_LOOPBACK 0x00000002
93 # define MAC_FDX 0x00000001
94 #define CPMAC_MAC_STATUS 0x0164
95 # define MAC_STATUS_QOS 0x00000004
96 # define MAC_STATUS_RXFLOW 0x00000002
97 # define MAC_STATUS_TXFLOW 0x00000001
98 #define CPMAC_TX_INT_ENABLE 0x0178
99 #define CPMAC_TX_INT_CLEAR 0x017c
100 #define CPMAC_MAC_INT_VECTOR 0x0180
101 # define MAC_INT_STATUS 0x00080000
102 # define MAC_INT_HOST 0x00040000
103 # define MAC_INT_RX 0x00020000
104 # define MAC_INT_TX 0x00010000
105 #define CPMAC_MAC_EOI_VECTOR 0x0184
106 #define CPMAC_RX_INT_ENABLE 0x0198
107 #define CPMAC_RX_INT_CLEAR 0x019c
108 #define CPMAC_MAC_INT_ENABLE 0x01a8
109 #define CPMAC_MAC_INT_CLEAR 0x01ac
110 #define CPMAC_MAC_ADDR_LO(channel) (0x01b0 + (channel) * 4)
111 #define CPMAC_MAC_ADDR_MID 0x01d0
112 #define CPMAC_MAC_ADDR_HI 0x01d4
113 #define CPMAC_MAC_HASH_LO 0x01d8
114 #define CPMAC_MAC_HASH_HI 0x01dc
115 #define CPMAC_TX_PTR(channel) (0x0600 + (channel) * 4)
116 #define CPMAC_RX_PTR(channel) (0x0620 + (channel) * 4)
117 #define CPMAC_TX_ACK(channel) (0x0640 + (channel) * 4)
118 #define CPMAC_RX_ACK(channel) (0x0660 + (channel) * 4)
119 #define CPMAC_REG_END 0x0680
120 /*
121 * Rx/Tx statistics
122 * TODO: use some of them to fill stats in cpmac_stats()
123 */
124 #define CPMAC_STATS_RX_GOOD 0x0200
125 #define CPMAC_STATS_RX_BCAST 0x0204
126 #define CPMAC_STATS_RX_MCAST 0x0208
127 #define CPMAC_STATS_RX_PAUSE 0x020c
128 #define CPMAC_STATS_RX_CRC 0x0210
129 #define CPMAC_STATS_RX_ALIGN 0x0214
130 #define CPMAC_STATS_RX_OVER 0x0218
131 #define CPMAC_STATS_RX_JABBER 0x021c
132 #define CPMAC_STATS_RX_UNDER 0x0220
133 #define CPMAC_STATS_RX_FRAG 0x0224
134 #define CPMAC_STATS_RX_FILTER 0x0228
135 #define CPMAC_STATS_RX_QOSFILTER 0x022c
136 #define CPMAC_STATS_RX_OCTETS 0x0230
137
138 #define CPMAC_STATS_TX_GOOD 0x0234
139 #define CPMAC_STATS_TX_BCAST 0x0238
140 #define CPMAC_STATS_TX_MCAST 0x023c
141 #define CPMAC_STATS_TX_PAUSE 0x0240
142 #define CPMAC_STATS_TX_DEFER 0x0244
143 #define CPMAC_STATS_TX_COLLISION 0x0248
144 #define CPMAC_STATS_TX_SINGLECOLL 0x024c
145 #define CPMAC_STATS_TX_MULTICOLL 0x0250
146 #define CPMAC_STATS_TX_EXCESSCOLL 0x0254
147 #define CPMAC_STATS_TX_LATECOLL 0x0258
148 #define CPMAC_STATS_TX_UNDERRUN 0x025c
149 #define CPMAC_STATS_TX_CARRIERSENSE 0x0260
150 #define CPMAC_STATS_TX_OCTETS 0x0264
151
152 #define cpmac_read(base, reg) (readl((void __iomem *)(base) + (reg)))
153 #define cpmac_write(base, reg, val) (writel(val, (void __iomem *)(base) + \
154 (reg)))
155
156 /* MDIO bus */
157 #define CPMAC_MDIO_VERSION 0x0000
158 #define CPMAC_MDIO_CONTROL 0x0004
159 # define MDIOC_IDLE 0x80000000
160 # define MDIOC_ENABLE 0x40000000
161 # define MDIOC_PREAMBLE 0x00100000
162 # define MDIOC_FAULT 0x00080000
163 # define MDIOC_FAULTDETECT 0x00040000
164 # define MDIOC_INTTEST 0x00020000
165 # define MDIOC_CLKDIV(div) ((div) & 0xff)
166 #define CPMAC_MDIO_ALIVE 0x0008
167 #define CPMAC_MDIO_LINK 0x000c
168 #define CPMAC_MDIO_ACCESS(channel) (0x0080 + (channel) * 8)
169 # define MDIO_BUSY 0x80000000
170 # define MDIO_WRITE 0x40000000
171 # define MDIO_REG(reg) (((reg) & 0x1f) << 21)
172 # define MDIO_PHY(phy) (((phy) & 0x1f) << 16)
173 # define MDIO_DATA(data) ((data) & 0xffff)
174 #define CPMAC_MDIO_PHYSEL(channel) (0x0084 + (channel) * 8)
175 # define PHYSEL_LINKSEL 0x00000040
176 # define PHYSEL_LINKINT 0x00000020
177
178 struct cpmac_desc {
179 u32 hw_next;
180 u32 hw_data;
181 u16 buflen;
182 u16 bufflags;
183 u16 datalen;
184 u16 dataflags;
185 #define CPMAC_SOP 0x8000
186 #define CPMAC_EOP 0x4000
187 #define CPMAC_OWN 0x2000
188 #define CPMAC_EOQ 0x1000
189 struct sk_buff *skb;
190 struct cpmac_desc *next;
191 struct cpmac_desc *prev;
192 dma_addr_t mapping;
193 dma_addr_t data_mapping;
194 };
195
196 struct cpmac_priv {
197 spinlock_t lock;
198 spinlock_t rx_lock;
199 struct cpmac_desc *rx_head;
200 int ring_size;
201 struct cpmac_desc *desc_ring;
202 dma_addr_t dma_ring;
203 void __iomem *regs;
204 struct mii_bus *mii_bus;
205 struct phy_device *phy;
206 char phy_name[BUS_ID_SIZE];
207 int oldlink, oldspeed, oldduplex;
208 u32 msg_enable;
209 struct net_device *dev;
210 struct work_struct reset_work;
211 struct platform_device *pdev;
212 struct napi_struct napi;
213 atomic_t reset_pending;
214 };
215
216 static irqreturn_t cpmac_irq(int, void *);
217 static void cpmac_hw_start(struct net_device *dev);
218 static void cpmac_hw_stop(struct net_device *dev);
219 static int cpmac_stop(struct net_device *dev);
220 static int cpmac_open(struct net_device *dev);
221
222 static void cpmac_dump_regs(struct net_device *dev)
223 {
224 int i;
225 struct cpmac_priv *priv = netdev_priv(dev);
226 for (i = 0; i < CPMAC_REG_END; i += 4) {
227 if (i % 16 == 0) {
228 if (i)
229 printk("\n");
230 printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
231 priv->regs + i);
232 }
233 printk(" %08x", cpmac_read(priv->regs, i));
234 }
235 printk("\n");
236 }
237
238 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
239 {
240 int i;
241 printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
242 for (i = 0; i < sizeof(*desc) / 4; i++)
243 printk(" %08x", ((u32 *)desc)[i]);
244 printk("\n");
245 }
246
247 static void cpmac_dump_all_desc(struct net_device *dev)
248 {
249 struct cpmac_priv *priv = netdev_priv(dev);
250 struct cpmac_desc *dump = priv->rx_head;
251 do {
252 cpmac_dump_desc(dev, dump);
253 dump = dump->next;
254 } while (dump != priv->rx_head);
255 }
256
257 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
258 {
259 int i;
260 printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
261 for (i = 0; i < skb->len; i++) {
262 if (i % 16 == 0) {
263 if (i)
264 printk("\n");
265 printk(KERN_DEBUG "%s: data[%p]:", dev->name,
266 skb->data + i);
267 }
268 printk(" %02x", ((u8 *)skb->data)[i]);
269 }
270 printk("\n");
271 }
272
273 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
274 {
275 u32 val;
276
277 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
278 cpu_relax();
279 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
280 MDIO_PHY(phy_id));
281 while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
282 cpu_relax();
283 return MDIO_DATA(val);
284 }
285
286 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
287 int reg, u16 val)
288 {
289 while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
290 cpu_relax();
291 cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
292 MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
293 return 0;
294 }
295
296 static int cpmac_mdio_reset(struct mii_bus *bus)
297 {
298 ar7_device_reset(AR7_RESET_BIT_MDIO);
299 cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
300 MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
301 return 0;
302 }
303
304 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
305
306 static struct mii_bus cpmac_mii = {
307 .name = "cpmac-mii",
308 .read = cpmac_mdio_read,
309 .write = cpmac_mdio_write,
310 .reset = cpmac_mdio_reset,
311 .irq = mii_irqs,
312 };
313
314 static int cpmac_config(struct net_device *dev, struct ifmap *map)
315 {
316 if (dev->flags & IFF_UP)
317 return -EBUSY;
318
319 /* Don't allow changing the I/O address */
320 if (map->base_addr != dev->base_addr)
321 return -EOPNOTSUPP;
322
323 /* ignore other fields */
324 return 0;
325 }
326
327 static void cpmac_set_multicast_list(struct net_device *dev)
328 {
329 struct dev_mc_list *iter;
330 int i;
331 u8 tmp;
332 u32 mbp, bit, hash[2] = { 0, };
333 struct cpmac_priv *priv = netdev_priv(dev);
334
335 mbp = cpmac_read(priv->regs, CPMAC_MBP);
336 if (dev->flags & IFF_PROMISC) {
337 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
338 MBP_RXPROMISC);
339 } else {
340 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
341 if (dev->flags & IFF_ALLMULTI) {
342 /* enable all multicast mode */
343 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
344 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
345 } else {
346 /*
347 * cpmac uses some strange mac address hashing
348 * (not crc32)
349 */
350 for (i = 0, iter = dev->mc_list; i < dev->mc_count;
351 i++, iter = iter->next) {
352 bit = 0;
353 tmp = iter->dmi_addr[0];
354 bit ^= (tmp >> 2) ^ (tmp << 4);
355 tmp = iter->dmi_addr[1];
356 bit ^= (tmp >> 4) ^ (tmp << 2);
357 tmp = iter->dmi_addr[2];
358 bit ^= (tmp >> 6) ^ tmp;
359 tmp = iter->dmi_addr[3];
360 bit ^= (tmp >> 2) ^ (tmp << 4);
361 tmp = iter->dmi_addr[4];
362 bit ^= (tmp >> 4) ^ (tmp << 2);
363 tmp = iter->dmi_addr[5];
364 bit ^= (tmp >> 6) ^ tmp;
365 bit &= 0x3f;
366 hash[bit / 32] |= 1 << (bit % 32);
367 }
368
369 cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
370 cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
371 }
372 }
373 }
374
375 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
376 struct cpmac_desc *desc)
377 {
378 struct sk_buff *skb, *result = NULL;
379
380 if (unlikely(netif_msg_hw(priv)))
381 cpmac_dump_desc(priv->dev, desc);
382 cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
383 if (unlikely(!desc->datalen)) {
384 if (netif_msg_rx_err(priv) && net_ratelimit())
385 printk(KERN_WARNING "%s: rx: spurious interrupt\n",
386 priv->dev->name);
387 return NULL;
388 }
389
390 skb = netdev_alloc_skb(priv->dev, CPMAC_SKB_SIZE);
391 if (likely(skb)) {
392 skb_reserve(skb, 2);
393 skb_put(desc->skb, desc->datalen);
394 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
395 desc->skb->ip_summed = CHECKSUM_NONE;
396 priv->dev->stats.rx_packets++;
397 priv->dev->stats.rx_bytes += desc->datalen;
398 result = desc->skb;
399 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
400 CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
401 desc->skb = skb;
402 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
403 CPMAC_SKB_SIZE,
404 DMA_FROM_DEVICE);
405 desc->hw_data = (u32)desc->data_mapping;
406 if (unlikely(netif_msg_pktdata(priv))) {
407 printk(KERN_DEBUG "%s: received packet:\n",
408 priv->dev->name);
409 cpmac_dump_skb(priv->dev, result);
410 }
411 } else {
412 if (netif_msg_rx_err(priv) && net_ratelimit())
413 printk(KERN_WARNING
414 "%s: low on skbs, dropping packet\n",
415 priv->dev->name);
416 priv->dev->stats.rx_dropped++;
417 }
418
419 desc->buflen = CPMAC_SKB_SIZE;
420 desc->dataflags = CPMAC_OWN;
421
422 return result;
423 }
424
425 static int cpmac_poll(struct napi_struct *napi, int budget)
426 {
427 struct sk_buff *skb;
428 struct cpmac_desc *desc, *restart;
429 struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
430 int received = 0, processed = 0;
431
432 spin_lock(&priv->rx_lock);
433 if (unlikely(!priv->rx_head)) {
434 if (netif_msg_rx_err(priv) && net_ratelimit())
435 printk(KERN_WARNING "%s: rx: polling, but no queue\n",
436 priv->dev->name);
437 spin_unlock(&priv->rx_lock);
438 netif_rx_complete(priv->dev, napi);
439 return 0;
440 }
441
442 desc = priv->rx_head;
443 restart = NULL;
444 while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
445 processed++;
446
447 if ((desc->dataflags & CPMAC_EOQ) != 0) {
448 /* The last update to eoq->hw_next didn't happen
449 * soon enough, and the receiver stopped here.
450 *Remember this descriptor so we can restart
451 * the receiver after freeing some space.
452 */
453 if (unlikely(restart)) {
454 if (netif_msg_rx_err(priv))
455 printk(KERN_ERR "%s: poll found a"
456 " duplicate EOQ: %p and %p\n",
457 priv->dev->name, restart, desc);
458 goto fatal_error;
459 }
460
461 restart = desc->next;
462 }
463
464 skb = cpmac_rx_one(priv, desc);
465 if (likely(skb)) {
466 netif_receive_skb(skb);
467 received++;
468 }
469 desc = desc->next;
470 }
471
472 if (desc != priv->rx_head) {
473 /* We freed some buffers, but not the whole ring,
474 * add what we did free to the rx list */
475 desc->prev->hw_next = (u32)0;
476 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
477 }
478
479 /* Optimization: If we did not actually process an EOQ (perhaps because
480 * of quota limits), check to see if the tail of the queue has EOQ set.
481 * We should immediately restart in that case so that the receiver can
482 * restart and run in parallel with more packet processing.
483 * This lets us handle slightly larger bursts before running
484 * out of ring space (assuming dev->weight < ring_size) */
485
486 if (!restart &&
487 (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
488 == CPMAC_EOQ &&
489 (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
490 /* reset EOQ so the poll loop (above) doesn't try to
491 * restart this when it eventually gets to this descriptor.
492 */
493 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
494 restart = priv->rx_head;
495 }
496
497 if (restart) {
498 priv->dev->stats.rx_errors++;
499 priv->dev->stats.rx_fifo_errors++;
500 if (netif_msg_rx_err(priv) && net_ratelimit())
501 printk(KERN_WARNING "%s: rx dma ring overrun\n",
502 priv->dev->name);
503
504 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
505 if (netif_msg_drv(priv))
506 printk(KERN_ERR "%s: cpmac_poll is trying to "
507 "restart rx from a descriptor that's "
508 "not free: %p\n",
509 priv->dev->name, restart);
510 goto fatal_error;
511 }
512
513 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
514 }
515
516 priv->rx_head = desc;
517 spin_unlock(&priv->rx_lock);
518 if (unlikely(netif_msg_rx_status(priv)))
519 printk(KERN_DEBUG "%s: poll processed %d packets\n",
520 priv->dev->name, received);
521 if (processed == 0) {
522 /* we ran out of packets to read,
523 * revert to interrupt-driven mode */
524 netif_rx_complete(priv->dev, napi);
525 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
526 return 0;
527 }
528
529 return 1;
530
531 fatal_error:
532 /* Something went horribly wrong.
533 * Reset hardware to try to recover rather than wedging. */
534
535 if (netif_msg_drv(priv)) {
536 printk(KERN_ERR "%s: cpmac_poll is confused. "
537 "Resetting hardware\n", priv->dev->name);
538 cpmac_dump_all_desc(priv->dev);
539 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
540 priv->dev->name,
541 cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
542 cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
543 }
544
545 spin_unlock(&priv->rx_lock);
546 netif_rx_complete(priv->dev, napi);
547 netif_stop_queue(priv->dev);
548 napi_disable(&priv->napi);
549
550 atomic_inc(&priv->reset_pending);
551 cpmac_hw_stop(priv->dev);
552 if (!schedule_work(&priv->reset_work))
553 atomic_dec(&priv->reset_pending);
554 return 0;
555
556 }
557
558 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
559 {
560 int queue, len;
561 struct cpmac_desc *desc;
562 struct cpmac_priv *priv = netdev_priv(dev);
563
564 if (unlikely(atomic_read(&priv->reset_pending)))
565 return NETDEV_TX_BUSY;
566
567 if (unlikely(skb_padto(skb, ETH_ZLEN)))
568 return NETDEV_TX_OK;
569
570 len = max(skb->len, ETH_ZLEN);
571 queue = skb_get_queue_mapping(skb);
572 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
573 netif_stop_subqueue(dev, queue);
574 #else
575 netif_stop_queue(dev);
576 #endif
577
578 desc = &priv->desc_ring[queue];
579 if (unlikely(desc->dataflags & CPMAC_OWN)) {
580 if (netif_msg_tx_err(priv) && net_ratelimit())
581 printk(KERN_WARNING "%s: tx dma ring full\n",
582 dev->name);
583 return NETDEV_TX_BUSY;
584 }
585
586 spin_lock(&priv->lock);
587 dev->trans_start = jiffies;
588 spin_unlock(&priv->lock);
589 desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
590 desc->skb = skb;
591 desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
592 DMA_TO_DEVICE);
593 desc->hw_data = (u32)desc->data_mapping;
594 desc->datalen = len;
595 desc->buflen = len;
596 if (unlikely(netif_msg_tx_queued(priv)))
597 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
598 skb->len);
599 if (unlikely(netif_msg_hw(priv)))
600 cpmac_dump_desc(dev, desc);
601 if (unlikely(netif_msg_pktdata(priv)))
602 cpmac_dump_skb(dev, skb);
603 cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
604
605 return NETDEV_TX_OK;
606 }
607
608 static void cpmac_end_xmit(struct net_device *dev, int queue)
609 {
610 struct cpmac_desc *desc;
611 struct cpmac_priv *priv = netdev_priv(dev);
612
613 desc = &priv->desc_ring[queue];
614 cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
615 if (likely(desc->skb)) {
616 spin_lock(&priv->lock);
617 dev->stats.tx_packets++;
618 dev->stats.tx_bytes += desc->skb->len;
619 spin_unlock(&priv->lock);
620 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
621 DMA_TO_DEVICE);
622
623 if (unlikely(netif_msg_tx_done(priv)))
624 printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
625 desc->skb, desc->skb->len);
626
627 dev_kfree_skb_irq(desc->skb);
628 desc->skb = NULL;
629 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
630 if (netif_subqueue_stopped(dev, queue))
631 netif_wake_subqueue(dev, queue);
632 #else
633 if (netif_queue_stopped(dev))
634 netif_wake_queue(dev);
635 #endif
636 } else {
637 if (netif_msg_tx_err(priv) && net_ratelimit())
638 printk(KERN_WARNING
639 "%s: end_xmit: spurious interrupt\n", dev->name);
640 #ifdef CONFIG_NETDEVICES_MULTIQUEUE
641 if (netif_subqueue_stopped(dev, queue))
642 netif_wake_subqueue(dev, queue);
643 #else
644 if (netif_queue_stopped(dev))
645 netif_wake_queue(dev);
646 #endif
647 }
648 }
649
650 static void cpmac_hw_stop(struct net_device *dev)
651 {
652 int i;
653 struct cpmac_priv *priv = netdev_priv(dev);
654 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
655
656 ar7_device_reset(pdata->reset_bit);
657 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
658 cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
659 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
660 cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
661 for (i = 0; i < 8; i++) {
662 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
663 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
664 }
665 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
666 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
667 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
668 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
669 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
670 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
671 }
672
673 static void cpmac_hw_start(struct net_device *dev)
674 {
675 int i;
676 struct cpmac_priv *priv = netdev_priv(dev);
677 struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
678
679 ar7_device_reset(pdata->reset_bit);
680 for (i = 0; i < 8; i++) {
681 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
682 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
683 }
684 cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
685
686 cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
687 MBP_RXMCAST);
688 cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
689 for (i = 0; i < 8; i++)
690 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
691 cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
692 cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
693 (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
694 (dev->dev_addr[3] << 24));
695 cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
696 cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
697 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
698 cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
699 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
700 cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
701 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
702 cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
703 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
704
705 cpmac_write(priv->regs, CPMAC_RX_CONTROL,
706 cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
707 cpmac_write(priv->regs, CPMAC_TX_CONTROL,
708 cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
709 cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
710 cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
711 MAC_FDX);
712 }
713
714 static void cpmac_clear_rx(struct net_device *dev)
715 {
716 struct cpmac_priv *priv = netdev_priv(dev);
717 struct cpmac_desc *desc;
718 int i;
719 if (unlikely(!priv->rx_head))
720 return;
721 desc = priv->rx_head;
722 for (i = 0; i < priv->ring_size; i++) {
723 if ((desc->dataflags & CPMAC_OWN) == 0) {
724 if (netif_msg_rx_err(priv) && net_ratelimit())
725 printk(KERN_WARNING "%s: packet dropped\n",
726 dev->name);
727 if (unlikely(netif_msg_hw(priv)))
728 cpmac_dump_desc(dev, desc);
729 desc->dataflags = CPMAC_OWN;
730 dev->stats.rx_dropped++;
731 }
732 desc->hw_next = desc->next->mapping;
733 desc = desc->next;
734 }
735 priv->rx_head->prev->hw_next = 0;
736 }
737
738 static void cpmac_clear_tx(struct net_device *dev)
739 {
740 struct cpmac_priv *priv = netdev_priv(dev);
741 int i;
742 if (unlikely(!priv->desc_ring))
743 return;
744 for (i = 0; i < CPMAC_QUEUES; i++) {
745 priv->desc_ring[i].dataflags = 0;
746 if (priv->desc_ring[i].skb) {
747 dev_kfree_skb_any(priv->desc_ring[i].skb);
748 priv->desc_ring[i].skb = NULL;
749 }
750 }
751 }
752
753 static void cpmac_hw_error(struct work_struct *work)
754 {
755 int i;
756 struct cpmac_priv *priv =
757 container_of(work, struct cpmac_priv, reset_work);
758
759 spin_lock(&priv->rx_lock);
760 cpmac_clear_rx(priv->dev);
761 spin_unlock(&priv->rx_lock);
762 cpmac_clear_tx(priv->dev);
763 cpmac_hw_start(priv->dev);
764 barrier();
765 atomic_dec(&priv->reset_pending);
766
767 for (i = 0; i < CPMAC_QUEUES; i++)
768 netif_wake_subqueue(priv->dev, i);
769 netif_wake_queue(priv->dev);
770 cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
771 }
772
773 static void cpmac_check_status(struct net_device *dev)
774 {
775 struct cpmac_priv *priv = netdev_priv(dev);
776
777 u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
778 int rx_channel = (macstatus >> 8) & 7;
779 int rx_code = (macstatus >> 12) & 15;
780 int tx_channel = (macstatus >> 16) & 7;
781 int tx_code = (macstatus >> 20) & 15;
782
783 if (rx_code || tx_code) {
784 if (netif_msg_drv(priv) && net_ratelimit()) {
785 /* Can't find any documentation on what these
786 *error codes actually are. So just log them and hope..
787 */
788 if (rx_code)
789 printk(KERN_WARNING "%s: host error %d on rx "
790 "channel %d (macstatus %08x), resetting\n",
791 dev->name, rx_code, rx_channel, macstatus);
792 if (tx_code)
793 printk(KERN_WARNING "%s: host error %d on tx "
794 "channel %d (macstatus %08x), resetting\n",
795 dev->name, tx_code, tx_channel, macstatus);
796 }
797
798 netif_stop_queue(dev);
799 cpmac_hw_stop(dev);
800 if (schedule_work(&priv->reset_work))
801 atomic_inc(&priv->reset_pending);
802 if (unlikely(netif_msg_hw(priv)))
803 cpmac_dump_regs(dev);
804 }
805 cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
806 }
807
808 static irqreturn_t cpmac_irq(int irq, void *dev_id)
809 {
810 struct net_device *dev = dev_id;
811 struct cpmac_priv *priv;
812 int queue;
813 u32 status;
814
815 priv = netdev_priv(dev);
816
817 status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
818
819 if (unlikely(netif_msg_intr(priv)))
820 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
821 status);
822
823 if (status & MAC_INT_TX)
824 cpmac_end_xmit(dev, (status & 7));
825
826 if (status & MAC_INT_RX) {
827 queue = (status >> 8) & 7;
828 if (netif_rx_schedule_prep(dev, &priv->napi)) {
829 cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
830 __netif_rx_schedule(dev, &priv->napi);
831 }
832 }
833
834 cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
835
836 if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
837 cpmac_check_status(dev);
838
839 return IRQ_HANDLED;
840 }
841
842 static void cpmac_tx_timeout(struct net_device *dev)
843 {
844 int i;
845 struct cpmac_priv *priv = netdev_priv(dev);
846
847 spin_lock(&priv->lock);
848 dev->stats.tx_errors++;
849 spin_unlock(&priv->lock);
850 if (netif_msg_tx_err(priv) && net_ratelimit())
851 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
852
853 atomic_inc(&priv->reset_pending);
854 barrier();
855 cpmac_clear_tx(dev);
856 barrier();
857 atomic_dec(&priv->reset_pending);
858
859 netif_wake_queue(priv->dev);
860 for (i = 0; i < CPMAC_QUEUES; i++)
861 netif_wake_subqueue(dev, i);
862 }
863
864 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
865 {
866 struct cpmac_priv *priv = netdev_priv(dev);
867 if (!(netif_running(dev)))
868 return -EINVAL;
869 if (!priv->phy)
870 return -EINVAL;
871 if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
872 (cmd == SIOCSMIIREG))
873 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
874
875 return -EOPNOTSUPP;
876 }
877
878 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
879 {
880 struct cpmac_priv *priv = netdev_priv(dev);
881
882 if (priv->phy)
883 return phy_ethtool_gset(priv->phy, cmd);
884
885 return -EINVAL;
886 }
887
888 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
889 {
890 struct cpmac_priv *priv = netdev_priv(dev);
891
892 if (!capable(CAP_NET_ADMIN))
893 return -EPERM;
894
895 if (priv->phy)
896 return phy_ethtool_sset(priv->phy, cmd);
897
898 return -EINVAL;
899 }
900
901 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
902 {
903 struct cpmac_priv *priv = netdev_priv(dev);
904
905 ring->rx_max_pending = 1024;
906 ring->rx_mini_max_pending = 1;
907 ring->rx_jumbo_max_pending = 1;
908 ring->tx_max_pending = 1;
909
910 ring->rx_pending = priv->ring_size;
911 ring->rx_mini_pending = 1;
912 ring->rx_jumbo_pending = 1;
913 ring->tx_pending = 1;
914 }
915
916 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
917 {
918 struct cpmac_priv *priv = netdev_priv(dev);
919
920 if (netif_running(dev))
921 return -EBUSY;
922 priv->ring_size = ring->rx_pending;
923 return 0;
924 }
925
926 static void cpmac_get_drvinfo(struct net_device *dev,
927 struct ethtool_drvinfo *info)
928 {
929 strcpy(info->driver, "cpmac");
930 strcpy(info->version, CPMAC_VERSION);
931 info->fw_version[0] = '\0';
932 sprintf(info->bus_info, "%s", "cpmac");
933 info->regdump_len = 0;
934 }
935
936 static const struct ethtool_ops cpmac_ethtool_ops = {
937 .get_settings = cpmac_get_settings,
938 .set_settings = cpmac_set_settings,
939 .get_drvinfo = cpmac_get_drvinfo,
940 .get_link = ethtool_op_get_link,
941 .get_ringparam = cpmac_get_ringparam,
942 .set_ringparam = cpmac_set_ringparam,
943 };
944
945 static void cpmac_adjust_link(struct net_device *dev)
946 {
947 struct cpmac_priv *priv = netdev_priv(dev);
948 int new_state = 0;
949
950 spin_lock(&priv->lock);
951 if (priv->phy->link) {
952 netif_start_queue(dev);
953 if (priv->phy->duplex != priv->oldduplex) {
954 new_state = 1;
955 priv->oldduplex = priv->phy->duplex;
956 }
957
958 if (priv->phy->speed != priv->oldspeed) {
959 new_state = 1;
960 priv->oldspeed = priv->phy->speed;
961 }
962
963 if (!priv->oldlink) {
964 new_state = 1;
965 priv->oldlink = 1;
966 netif_schedule(dev);
967 }
968 } else if (priv->oldlink) {
969 netif_stop_queue(dev);
970 new_state = 1;
971 priv->oldlink = 0;
972 priv->oldspeed = 0;
973 priv->oldduplex = -1;
974 }
975
976 if (new_state && netif_msg_link(priv) && net_ratelimit())
977 phy_print_status(priv->phy);
978
979 spin_unlock(&priv->lock);
980 }
981
982 static int cpmac_open(struct net_device *dev)
983 {
984 int i, size, res;
985 struct cpmac_priv *priv = netdev_priv(dev);
986 struct resource *mem;
987 struct cpmac_desc *desc;
988 struct sk_buff *skb;
989
990 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
991 if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
992 if (netif_msg_drv(priv))
993 printk(KERN_ERR "%s: failed to request registers\n",
994 dev->name);
995 res = -ENXIO;
996 goto fail_reserve;
997 }
998
999 priv->regs = ioremap(mem->start, mem->end - mem->start);
1000 if (!priv->regs) {
1001 if (netif_msg_drv(priv))
1002 printk(KERN_ERR "%s: failed to remap registers\n",
1003 dev->name);
1004 res = -ENXIO;
1005 goto fail_remap;
1006 }
1007
1008 size = priv->ring_size + CPMAC_QUEUES;
1009 priv->desc_ring = dma_alloc_coherent(&dev->dev,
1010 sizeof(struct cpmac_desc) * size,
1011 &priv->dma_ring,
1012 GFP_KERNEL);
1013 if (!priv->desc_ring) {
1014 res = -ENOMEM;
1015 goto fail_alloc;
1016 }
1017
1018 for (i = 0; i < size; i++)
1019 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
1020
1021 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1022 for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
1023 skb = netdev_alloc_skb(dev, CPMAC_SKB_SIZE);
1024 if (unlikely(!skb)) {
1025 res = -ENOMEM;
1026 goto fail_desc;
1027 }
1028 skb_reserve(skb, 2);
1029 desc->skb = skb;
1030 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
1031 CPMAC_SKB_SIZE,
1032 DMA_FROM_DEVICE);
1033 desc->hw_data = (u32)desc->data_mapping;
1034 desc->buflen = CPMAC_SKB_SIZE;
1035 desc->dataflags = CPMAC_OWN;
1036 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1037 desc->next->prev = desc;
1038 desc->hw_next = (u32)desc->next->mapping;
1039 }
1040
1041 priv->rx_head->prev->hw_next = (u32)0;
1042
1043 if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
1044 dev->name, dev))) {
1045 if (netif_msg_drv(priv))
1046 printk(KERN_ERR "%s: failed to obtain irq\n",
1047 dev->name);
1048 goto fail_irq;
1049 }
1050
1051 atomic_set(&priv->reset_pending, 0);
1052 INIT_WORK(&priv->reset_work, cpmac_hw_error);
1053 cpmac_hw_start(dev);
1054
1055 napi_enable(&priv->napi);
1056 priv->phy->state = PHY_CHANGELINK;
1057 phy_start(priv->phy);
1058
1059 return 0;
1060
1061 fail_irq:
1062 fail_desc:
1063 for (i = 0; i < priv->ring_size; i++) {
1064 if (priv->rx_head[i].skb) {
1065 dma_unmap_single(&dev->dev,
1066 priv->rx_head[i].data_mapping,
1067 CPMAC_SKB_SIZE,
1068 DMA_FROM_DEVICE);
1069 kfree_skb(priv->rx_head[i].skb);
1070 }
1071 }
1072 fail_alloc:
1073 kfree(priv->desc_ring);
1074 iounmap(priv->regs);
1075
1076 fail_remap:
1077 release_mem_region(mem->start, mem->end - mem->start);
1078
1079 fail_reserve:
1080 return res;
1081 }
1082
1083 static int cpmac_stop(struct net_device *dev)
1084 {
1085 int i;
1086 struct cpmac_priv *priv = netdev_priv(dev);
1087 struct resource *mem;
1088
1089 netif_stop_queue(dev);
1090
1091 cancel_work_sync(&priv->reset_work);
1092 napi_disable(&priv->napi);
1093 phy_stop(priv->phy);
1094
1095 cpmac_hw_stop(dev);
1096
1097 for (i = 0; i < 8; i++)
1098 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1099 cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1100 cpmac_write(priv->regs, CPMAC_MBP, 0);
1101
1102 free_irq(dev->irq, dev);
1103 iounmap(priv->regs);
1104 mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1105 release_mem_region(mem->start, mem->end - mem->start);
1106 priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1107 for (i = 0; i < priv->ring_size; i++) {
1108 if (priv->rx_head[i].skb) {
1109 dma_unmap_single(&dev->dev,
1110 priv->rx_head[i].data_mapping,
1111 CPMAC_SKB_SIZE,
1112 DMA_FROM_DEVICE);
1113 kfree_skb(priv->rx_head[i].skb);
1114 }
1115 }
1116
1117 dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1118 (CPMAC_QUEUES + priv->ring_size),
1119 priv->desc_ring, priv->dma_ring);
1120 return 0;
1121 }
1122
1123 static int external_switch;
1124
1125 static int __devinit cpmac_probe(struct platform_device *pdev)
1126 {
1127 int rc, phy_id, i;
1128 char *mdio_bus_id = "0";
1129 struct resource *mem;
1130 struct cpmac_priv *priv;
1131 struct net_device *dev;
1132 struct plat_cpmac_data *pdata;
1133 DECLARE_MAC_BUF(mac);
1134
1135 pdata = pdev->dev.platform_data;
1136
1137 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1138 if (!(pdata->phy_mask & (1 << phy_id)))
1139 continue;
1140 if (!cpmac_mii.phy_map[phy_id])
1141 continue;
1142 break;
1143 }
1144
1145 if (phy_id == PHY_MAX_ADDR) {
1146 if (external_switch || dumb_switch) {
1147 mdio_bus_id = 0; /* fixed phys bus */
1148 phy_id = pdev->id;
1149 } else {
1150 dev_err(&pdev->dev, "no PHY present\n");
1151 return -ENODEV;
1152 }
1153 }
1154
1155 dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1156
1157 if (!dev) {
1158 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1159 return -ENOMEM;
1160 }
1161
1162 platform_set_drvdata(pdev, dev);
1163 priv = netdev_priv(dev);
1164
1165 priv->pdev = pdev;
1166 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1167 if (!mem) {
1168 rc = -ENODEV;
1169 goto fail;
1170 }
1171
1172 dev->irq = platform_get_irq_byname(pdev, "irq");
1173
1174 dev->open = cpmac_open;
1175 dev->stop = cpmac_stop;
1176 dev->set_config = cpmac_config;
1177 dev->hard_start_xmit = cpmac_start_xmit;
1178 dev->do_ioctl = cpmac_ioctl;
1179 dev->set_multicast_list = cpmac_set_multicast_list;
1180 dev->tx_timeout = cpmac_tx_timeout;
1181 dev->ethtool_ops = &cpmac_ethtool_ops;
1182 dev->features |= NETIF_F_MULTI_QUEUE;
1183
1184 netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1185
1186 spin_lock_init(&priv->lock);
1187 spin_lock_init(&priv->rx_lock);
1188 priv->dev = dev;
1189 priv->ring_size = 64;
1190 priv->msg_enable = netif_msg_init(debug_level, 0xff);
1191 memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr));
1192
1193 priv->phy = phy_connect(dev, cpmac_mii.phy_map[phy_id]->dev.bus_id,
1194 &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII);
1195 if (IS_ERR(priv->phy)) {
1196 if (netif_msg_drv(priv))
1197 printk(KERN_ERR "%s: Could not attach to PHY\n",
1198 dev->name);
1199 return PTR_ERR(priv->phy);
1200 }
1201
1202 if ((rc = register_netdev(dev))) {
1203 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1204 dev->name);
1205 goto fail;
1206 }
1207
1208 if (netif_msg_probe(priv)) {
1209 printk(KERN_INFO
1210 "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1211 "mac: %s)\n", dev->name, (void *)mem->start, dev->irq,
1212 priv->phy_name, print_mac(mac, dev->dev_addr));
1213 }
1214 return 0;
1215
1216 fail:
1217 free_netdev(dev);
1218 return rc;
1219 }
1220
1221 static int __devexit cpmac_remove(struct platform_device *pdev)
1222 {
1223 struct net_device *dev = platform_get_drvdata(pdev);
1224 unregister_netdev(dev);
1225 free_netdev(dev);
1226 return 0;
1227 }
1228
1229 static struct platform_driver cpmac_driver = {
1230 .driver.name = "cpmac",
1231 .driver.owner = THIS_MODULE,
1232 .probe = cpmac_probe,
1233 .remove = __devexit_p(cpmac_remove),
1234 };
1235
1236 int __devinit cpmac_init(void)
1237 {
1238 u32 mask;
1239 int i, res;
1240
1241 cpmac_mii.priv = ioremap(AR7_REGS_MDIO, 256);
1242
1243 if (!cpmac_mii.priv) {
1244 printk(KERN_ERR "Can't ioremap mdio registers\n");
1245 return -ENXIO;
1246 }
1247
1248 #warning FIXME: unhardcode gpio&reset bits
1249 ar7_gpio_disable(26);
1250 ar7_gpio_disable(27);
1251 ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1252 ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1253 ar7_device_reset(AR7_RESET_BIT_EPHY);
1254
1255 cpmac_mii.reset(&cpmac_mii);
1256
1257 for (i = 0; i < 300000; i++)
1258 if ((mask = cpmac_read(cpmac_mii.priv, CPMAC_MDIO_ALIVE)))
1259 break;
1260 else
1261 cpu_relax();
1262
1263 mask &= 0x7fffffff;
1264 if (mask & (mask - 1)) {
1265 external_switch = 1;
1266 mask = 0;
1267 }
1268
1269 cpmac_mii.phy_mask = ~(mask | 0x80000000);
1270 snprintf(cpmac_mii.id, MII_BUS_ID_SIZE, "0");
1271
1272 res = mdiobus_register(&cpmac_mii);
1273 if (res)
1274 goto fail_mii;
1275
1276 res = platform_driver_register(&cpmac_driver);
1277 if (res)
1278 goto fail_cpmac;
1279
1280 return 0;
1281
1282 fail_cpmac:
1283 mdiobus_unregister(&cpmac_mii);
1284
1285 fail_mii:
1286 iounmap(cpmac_mii.priv);
1287
1288 return res;
1289 }
1290
1291 void __devexit cpmac_exit(void)
1292 {
1293 platform_driver_unregister(&cpmac_driver);
1294 mdiobus_unregister(&cpmac_mii);
1295 iounmap(cpmac_mii.priv);
1296 }
1297
1298 module_init(cpmac_init);
1299 module_exit(cpmac_exit);
Linux for Ginger Game Console