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ALSA: ASoC: TLV320AIC3X: Modify only interface related bits in aic3x_set_dai_fmt
[linux-ginger.git] / drivers / net / ibm_newemac / mal.c
blob10c267b2b9610b1e446a4fe32e4deba9c5700976
1 /*
2 * drivers/net/ibm_newemac/mal.c
3 *
4 * Memory Access Layer (MAL) support
5 *
6 * Copyright 2007 Benjamin Herrenschmidt, IBM Corp.
7 * <benh@kernel.crashing.org>
8 *
9 * Based on the arch/ppc version of the driver:
10 *
11 * Copyright (c) 2004, 2005 Zultys Technologies.
12 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
13 *
14 * Based on original work by
15 * Benjamin Herrenschmidt <benh@kernel.crashing.org>,
16 * David Gibson <hermes@gibson.dropbear.id.au>,
17 *
18 * Armin Kuster <akuster@mvista.com>
19 * Copyright 2002 MontaVista Softare Inc.
20 *
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2 of the License, or (at your
24 * option) any later version.
25 *
26 */
27
28 #include <linux/delay.h>
29
30 #include "core.h"
31
32 static int mal_count;
33
34 int __devinit mal_register_commac(struct mal_instance *mal,
35 struct mal_commac *commac)
36 {
37 unsigned long flags;
38
39 spin_lock_irqsave(&mal->lock, flags);
40
41 MAL_DBG(mal, "reg(%08x, %08x)" NL,
42 commac->tx_chan_mask, commac->rx_chan_mask);
43
44 /* Don't let multiple commacs claim the same channel(s) */
45 if ((mal->tx_chan_mask & commac->tx_chan_mask) ||
46 (mal->rx_chan_mask & commac->rx_chan_mask)) {
47 spin_unlock_irqrestore(&mal->lock, flags);
48 printk(KERN_WARNING "mal%d: COMMAC channels conflict!\n",
49 mal->index);
50 return -EBUSY;
51 }
52
53 if (list_empty(&mal->list))
54 napi_enable(&mal->napi);
55 mal->tx_chan_mask |= commac->tx_chan_mask;
56 mal->rx_chan_mask |= commac->rx_chan_mask;
57 list_add(&commac->list, &mal->list);
58
59 spin_unlock_irqrestore(&mal->lock, flags);
60
61 return 0;
62 }
63
64 void mal_unregister_commac(struct mal_instance *mal,
65 struct mal_commac *commac)
66 {
67 unsigned long flags;
68
69 spin_lock_irqsave(&mal->lock, flags);
70
71 MAL_DBG(mal, "unreg(%08x, %08x)" NL,
72 commac->tx_chan_mask, commac->rx_chan_mask);
73
74 mal->tx_chan_mask &= ~commac->tx_chan_mask;
75 mal->rx_chan_mask &= ~commac->rx_chan_mask;
76 list_del_init(&commac->list);
77 if (list_empty(&mal->list))
78 napi_disable(&mal->napi);
79
80 spin_unlock_irqrestore(&mal->lock, flags);
81 }
82
83 int mal_set_rcbs(struct mal_instance *mal, int channel, unsigned long size)
84 {
85 BUG_ON(channel < 0 || channel >= mal->num_rx_chans ||
86 size > MAL_MAX_RX_SIZE);
87
88 MAL_DBG(mal, "set_rbcs(%d, %lu)" NL, channel, size);
89
90 if (size & 0xf) {
91 printk(KERN_WARNING
92 "mal%d: incorrect RX size %lu for the channel %d\n",
93 mal->index, size, channel);
94 return -EINVAL;
95 }
96
97 set_mal_dcrn(mal, MAL_RCBS(channel), size >> 4);
98 return 0;
99 }
100
101 int mal_tx_bd_offset(struct mal_instance *mal, int channel)
102 {
103 BUG_ON(channel < 0 || channel >= mal->num_tx_chans);
104
105 return channel * NUM_TX_BUFF;
106 }
107
108 int mal_rx_bd_offset(struct mal_instance *mal, int channel)
109 {
110 BUG_ON(channel < 0 || channel >= mal->num_rx_chans);
111 return mal->num_tx_chans * NUM_TX_BUFF + channel * NUM_RX_BUFF;
112 }
113
114 void mal_enable_tx_channel(struct mal_instance *mal, int channel)
115 {
116 unsigned long flags;
117
118 spin_lock_irqsave(&mal->lock, flags);
119
120 MAL_DBG(mal, "enable_tx(%d)" NL, channel);
121
122 set_mal_dcrn(mal, MAL_TXCASR,
123 get_mal_dcrn(mal, MAL_TXCASR) | MAL_CHAN_MASK(channel));
124
125 spin_unlock_irqrestore(&mal->lock, flags);
126 }
127
128 void mal_disable_tx_channel(struct mal_instance *mal, int channel)
129 {
130 set_mal_dcrn(mal, MAL_TXCARR, MAL_CHAN_MASK(channel));
131
132 MAL_DBG(mal, "disable_tx(%d)" NL, channel);
133 }
134
135 void mal_enable_rx_channel(struct mal_instance *mal, int channel)
136 {
137 unsigned long flags;
138
139 /*
140 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
141 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
142 * for the bitmask
143 */
144 if (!(channel % 8))
145 channel >>= 3;
146
147 spin_lock_irqsave(&mal->lock, flags);
148
149 MAL_DBG(mal, "enable_rx(%d)" NL, channel);
150
151 set_mal_dcrn(mal, MAL_RXCASR,
152 get_mal_dcrn(mal, MAL_RXCASR) | MAL_CHAN_MASK(channel));
153
154 spin_unlock_irqrestore(&mal->lock, flags);
155 }
156
157 void mal_disable_rx_channel(struct mal_instance *mal, int channel)
158 {
159 /*
160 * On some 4xx PPC's (e.g. 460EX/GT), the rx channel is a multiple
161 * of 8, but enabling in MAL_RXCASR needs the divided by 8 value
162 * for the bitmask
163 */
164 if (!(channel % 8))
165 channel >>= 3;
166
167 set_mal_dcrn(mal, MAL_RXCARR, MAL_CHAN_MASK(channel));
168
169 MAL_DBG(mal, "disable_rx(%d)" NL, channel);
170 }
171
172 void mal_poll_add(struct mal_instance *mal, struct mal_commac *commac)
173 {
174 unsigned long flags;
175
176 spin_lock_irqsave(&mal->lock, flags);
177
178 MAL_DBG(mal, "poll_add(%p)" NL, commac);
179
180 /* starts disabled */
181 set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
182
183 list_add_tail(&commac->poll_list, &mal->poll_list);
184
185 spin_unlock_irqrestore(&mal->lock, flags);
186 }
187
188 void mal_poll_del(struct mal_instance *mal, struct mal_commac *commac)
189 {
190 unsigned long flags;
191
192 spin_lock_irqsave(&mal->lock, flags);
193
194 MAL_DBG(mal, "poll_del(%p)" NL, commac);
195
196 list_del(&commac->poll_list);
197
198 spin_unlock_irqrestore(&mal->lock, flags);
199 }
200
201 /* synchronized by mal_poll() */
202 static inline void mal_enable_eob_irq(struct mal_instance *mal)
203 {
204 MAL_DBG2(mal, "enable_irq" NL);
205
206 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
207 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) | MAL_CFG_EOPIE);
208 }
209
210 /* synchronized by NAPI state */
211 static inline void mal_disable_eob_irq(struct mal_instance *mal)
212 {
213 // XXX might want to cache MAL_CFG as the DCR read can be slooooow
214 set_mal_dcrn(mal, MAL_CFG, get_mal_dcrn(mal, MAL_CFG) & ~MAL_CFG_EOPIE);
215
216 MAL_DBG2(mal, "disable_irq" NL);
217 }
218
219 static irqreturn_t mal_serr(int irq, void *dev_instance)
220 {
221 struct mal_instance *mal = dev_instance;
222
223 u32 esr = get_mal_dcrn(mal, MAL_ESR);
224
225 /* Clear the error status register */
226 set_mal_dcrn(mal, MAL_ESR, esr);
227
228 MAL_DBG(mal, "SERR %08x" NL, esr);
229
230 if (esr & MAL_ESR_EVB) {
231 if (esr & MAL_ESR_DE) {
232 /* We ignore Descriptor error,
233 * TXDE or RXDE interrupt will be generated anyway.
234 */
235 return IRQ_HANDLED;
236 }
237
238 if (esr & MAL_ESR_PEIN) {
239 /* PLB error, it's probably buggy hardware or
240 * incorrect physical address in BD (i.e. bug)
241 */
242 if (net_ratelimit())
243 printk(KERN_ERR
244 "mal%d: system error, "
245 "PLB (ESR = 0x%08x)\n",
246 mal->index, esr);
247 return IRQ_HANDLED;
248 }
249
250 /* OPB error, it's probably buggy hardware or incorrect
251 * EBC setup
252 */
253 if (net_ratelimit())
254 printk(KERN_ERR
255 "mal%d: system error, OPB (ESR = 0x%08x)\n",
256 mal->index, esr);
257 }
258 return IRQ_HANDLED;
259 }
260
261 static inline void mal_schedule_poll(struct mal_instance *mal)
262 {
263 if (likely(napi_schedule_prep(&mal->napi))) {
264 MAL_DBG2(mal, "schedule_poll" NL);
265 mal_disable_eob_irq(mal);
266 __napi_schedule(&mal->napi);
267 } else
268 MAL_DBG2(mal, "already in poll" NL);
269 }
270
271 static irqreturn_t mal_txeob(int irq, void *dev_instance)
272 {
273 struct mal_instance *mal = dev_instance;
274
275 u32 r = get_mal_dcrn(mal, MAL_TXEOBISR);
276
277 MAL_DBG2(mal, "txeob %08x" NL, r);
278
279 mal_schedule_poll(mal);
280 set_mal_dcrn(mal, MAL_TXEOBISR, r);
281
282 return IRQ_HANDLED;
283 }
284
285 static irqreturn_t mal_rxeob(int irq, void *dev_instance)
286 {
287 struct mal_instance *mal = dev_instance;
288
289 u32 r = get_mal_dcrn(mal, MAL_RXEOBISR);
290
291 MAL_DBG2(mal, "rxeob %08x" NL, r);
292
293 mal_schedule_poll(mal);
294 set_mal_dcrn(mal, MAL_RXEOBISR, r);
295
296 return IRQ_HANDLED;
297 }
298
299 static irqreturn_t mal_txde(int irq, void *dev_instance)
300 {
301 struct mal_instance *mal = dev_instance;
302
303 u32 deir = get_mal_dcrn(mal, MAL_TXDEIR);
304 set_mal_dcrn(mal, MAL_TXDEIR, deir);
305
306 MAL_DBG(mal, "txde %08x" NL, deir);
307
308 if (net_ratelimit())
309 printk(KERN_ERR
310 "mal%d: TX descriptor error (TXDEIR = 0x%08x)\n",
311 mal->index, deir);
312
313 return IRQ_HANDLED;
314 }
315
316 static irqreturn_t mal_rxde(int irq, void *dev_instance)
317 {
318 struct mal_instance *mal = dev_instance;
319 struct list_head *l;
320
321 u32 deir = get_mal_dcrn(mal, MAL_RXDEIR);
322
323 MAL_DBG(mal, "rxde %08x" NL, deir);
324
325 list_for_each(l, &mal->list) {
326 struct mal_commac *mc = list_entry(l, struct mal_commac, list);
327 if (deir & mc->rx_chan_mask) {
328 set_bit(MAL_COMMAC_RX_STOPPED, &mc->flags);
329 mc->ops->rxde(mc->dev);
330 }
331 }
332
333 mal_schedule_poll(mal);
334 set_mal_dcrn(mal, MAL_RXDEIR, deir);
335
336 return IRQ_HANDLED;
337 }
338
339 void mal_poll_disable(struct mal_instance *mal, struct mal_commac *commac)
340 {
341 /* Spinlock-type semantics: only one caller disable poll at a time */
342 while (test_and_set_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags))
343 msleep(1);
344
345 /* Synchronize with the MAL NAPI poller */
346 napi_synchronize(&mal->napi);
347 }
348
349 void mal_poll_enable(struct mal_instance *mal, struct mal_commac *commac)
350 {
351 smp_wmb();
352 clear_bit(MAL_COMMAC_POLL_DISABLED, &commac->flags);
353
354 /* Feels better to trigger a poll here to catch up with events that
355 * may have happened on this channel while disabled. It will most
356 * probably be delayed until the next interrupt but that's mostly a
357 * non-issue in the context where this is called.
358 */
359 napi_schedule(&mal->napi);
360 }
361
362 static int mal_poll(struct napi_struct *napi, int budget)
363 {
364 struct mal_instance *mal = container_of(napi, struct mal_instance, napi);
365 struct list_head *l;
366 int received = 0;
367 unsigned long flags;
368
369 MAL_DBG2(mal, "poll(%d)" NL, budget);
370 again:
371 /* Process TX skbs */
372 list_for_each(l, &mal->poll_list) {
373 struct mal_commac *mc =
374 list_entry(l, struct mal_commac, poll_list);
375 mc->ops->poll_tx(mc->dev);
376 }
377
378 /* Process RX skbs.
379 *
380 * We _might_ need something more smart here to enforce polling
381 * fairness.
382 */
383 list_for_each(l, &mal->poll_list) {
384 struct mal_commac *mc =
385 list_entry(l, struct mal_commac, poll_list);
386 int n;
387 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
388 continue;
389 n = mc->ops->poll_rx(mc->dev, budget);
390 if (n) {
391 received += n;
392 budget -= n;
393 if (budget <= 0)
394 goto more_work; // XXX What if this is the last one ?
395 }
396 }
397
398 /* We need to disable IRQs to protect from RXDE IRQ here */
399 spin_lock_irqsave(&mal->lock, flags);
400 __napi_complete(napi);
401 mal_enable_eob_irq(mal);
402 spin_unlock_irqrestore(&mal->lock, flags);
403
404 /* Check for "rotting" packet(s) */
405 list_for_each(l, &mal->poll_list) {
406 struct mal_commac *mc =
407 list_entry(l, struct mal_commac, poll_list);
408 if (unlikely(test_bit(MAL_COMMAC_POLL_DISABLED, &mc->flags)))
409 continue;
410 if (unlikely(mc->ops->peek_rx(mc->dev) ||
411 test_bit(MAL_COMMAC_RX_STOPPED, &mc->flags))) {
412 MAL_DBG2(mal, "rotting packet" NL);
413 if (napi_reschedule(napi))
414 mal_disable_eob_irq(mal);
415 else
416 MAL_DBG2(mal, "already in poll list" NL);
417
418 if (budget > 0)
419 goto again;
420 else
421 goto more_work;
422 }
423 mc->ops->poll_tx(mc->dev);
424 }
425
426 more_work:
427 MAL_DBG2(mal, "poll() %d <- %d" NL, budget, received);
428 return received;
429 }
430
431 static void mal_reset(struct mal_instance *mal)
432 {
433 int n = 10;
434
435 MAL_DBG(mal, "reset" NL);
436
437 set_mal_dcrn(mal, MAL_CFG, MAL_CFG_SR);
438
439 /* Wait for reset to complete (1 system clock) */
440 while ((get_mal_dcrn(mal, MAL_CFG) & MAL_CFG_SR) && n)
441 --n;
442
443 if (unlikely(!n))
444 printk(KERN_ERR "mal%d: reset timeout\n", mal->index);
445 }
446
447 int mal_get_regs_len(struct mal_instance *mal)
448 {
449 return sizeof(struct emac_ethtool_regs_subhdr) +
450 sizeof(struct mal_regs);
451 }
452
453 void *mal_dump_regs(struct mal_instance *mal, void *buf)
454 {
455 struct emac_ethtool_regs_subhdr *hdr = buf;
456 struct mal_regs *regs = (struct mal_regs *)(hdr + 1);
457 int i;
458
459 hdr->version = mal->version;
460 hdr->index = mal->index;
461
462 regs->tx_count = mal->num_tx_chans;
463 regs->rx_count = mal->num_rx_chans;
464
465 regs->cfg = get_mal_dcrn(mal, MAL_CFG);
466 regs->esr = get_mal_dcrn(mal, MAL_ESR);
467 regs->ier = get_mal_dcrn(mal, MAL_IER);
468 regs->tx_casr = get_mal_dcrn(mal, MAL_TXCASR);
469 regs->tx_carr = get_mal_dcrn(mal, MAL_TXCARR);
470 regs->tx_eobisr = get_mal_dcrn(mal, MAL_TXEOBISR);
471 regs->tx_deir = get_mal_dcrn(mal, MAL_TXDEIR);
472 regs->rx_casr = get_mal_dcrn(mal, MAL_RXCASR);
473 regs->rx_carr = get_mal_dcrn(mal, MAL_RXCARR);
474 regs->rx_eobisr = get_mal_dcrn(mal, MAL_RXEOBISR);
475 regs->rx_deir = get_mal_dcrn(mal, MAL_RXDEIR);
476
477 for (i = 0; i < regs->tx_count; ++i)
478 regs->tx_ctpr[i] = get_mal_dcrn(mal, MAL_TXCTPR(i));
479
480 for (i = 0; i < regs->rx_count; ++i) {
481 regs->rx_ctpr[i] = get_mal_dcrn(mal, MAL_RXCTPR(i));
482 regs->rcbs[i] = get_mal_dcrn(mal, MAL_RCBS(i));
483 }
484 return regs + 1;
485 }
486
487 static int __devinit mal_probe(struct of_device *ofdev,
488 const struct of_device_id *match)
489 {
490 struct mal_instance *mal;
491 int err = 0, i, bd_size;
492 int index = mal_count++;
493 unsigned int dcr_base;
494 const u32 *prop;
495 u32 cfg;
496
497 mal = kzalloc(sizeof(struct mal_instance), GFP_KERNEL);
498 if (!mal) {
499 printk(KERN_ERR
500 "mal%d: out of memory allocating MAL structure!\n",
501 index);
502 return -ENOMEM;
503 }
504 mal->index = index;
505 mal->ofdev = ofdev;
506 mal->version = of_device_is_compatible(ofdev->node, "ibm,mcmal2") ? 2 : 1;
507
508 MAL_DBG(mal, "probe" NL);
509
510 prop = of_get_property(ofdev->node, "num-tx-chans", NULL);
511 if (prop == NULL) {
512 printk(KERN_ERR
513 "mal%d: can't find MAL num-tx-chans property!\n",
514 index);
515 err = -ENODEV;
516 goto fail;
517 }
518 mal->num_tx_chans = prop[0];
519
520 prop = of_get_property(ofdev->node, "num-rx-chans", NULL);
521 if (prop == NULL) {
522 printk(KERN_ERR
523 "mal%d: can't find MAL num-rx-chans property!\n",
524 index);
525 err = -ENODEV;
526 goto fail;
527 }
528 mal->num_rx_chans = prop[0];
529
530 dcr_base = dcr_resource_start(ofdev->node, 0);
531 if (dcr_base == 0) {
532 printk(KERN_ERR
533 "mal%d: can't find DCR resource!\n", index);
534 err = -ENODEV;
535 goto fail;
536 }
537 mal->dcr_host = dcr_map(ofdev->node, dcr_base, 0x100);
538 if (!DCR_MAP_OK(mal->dcr_host)) {
539 printk(KERN_ERR
540 "mal%d: failed to map DCRs !\n", index);
541 err = -ENODEV;
542 goto fail;
543 }
544
545 mal->txeob_irq = irq_of_parse_and_map(ofdev->node, 0);
546 mal->rxeob_irq = irq_of_parse_and_map(ofdev->node, 1);
547 mal->serr_irq = irq_of_parse_and_map(ofdev->node, 2);
548 mal->txde_irq = irq_of_parse_and_map(ofdev->node, 3);
549 mal->rxde_irq = irq_of_parse_and_map(ofdev->node, 4);
550 if (mal->txeob_irq == NO_IRQ || mal->rxeob_irq == NO_IRQ ||
551 mal->serr_irq == NO_IRQ || mal->txde_irq == NO_IRQ ||
552 mal->rxde_irq == NO_IRQ) {
553 printk(KERN_ERR
554 "mal%d: failed to map interrupts !\n", index);
555 err = -ENODEV;
556 goto fail_unmap;
557 }
558
559 INIT_LIST_HEAD(&mal->poll_list);
560 INIT_LIST_HEAD(&mal->list);
561 spin_lock_init(&mal->lock);
562
563 netif_napi_add(NULL, &mal->napi, mal_poll,
564 CONFIG_IBM_NEW_EMAC_POLL_WEIGHT);
565
566 /* Load power-on reset defaults */
567 mal_reset(mal);
568
569 /* Set the MAL configuration register */
570 cfg = (mal->version == 2) ? MAL2_CFG_DEFAULT : MAL1_CFG_DEFAULT;
571 cfg |= MAL_CFG_PLBB | MAL_CFG_OPBBL | MAL_CFG_LEA;
572
573 /* Current Axon is not happy with priority being non-0, it can
574 * deadlock, fix it up here
575 */
576 if (of_device_is_compatible(ofdev->node, "ibm,mcmal-axon"))
577 cfg &= ~(MAL2_CFG_RPP_10 | MAL2_CFG_WPP_10);
578
579 /* Apply configuration */
580 set_mal_dcrn(mal, MAL_CFG, cfg);
581
582 /* Allocate space for BD rings */
583 BUG_ON(mal->num_tx_chans <= 0 || mal->num_tx_chans > 32);
584 BUG_ON(mal->num_rx_chans <= 0 || mal->num_rx_chans > 32);
585
586 bd_size = sizeof(struct mal_descriptor) *
587 (NUM_TX_BUFF * mal->num_tx_chans +
588 NUM_RX_BUFF * mal->num_rx_chans);
589 mal->bd_virt =
590 dma_alloc_coherent(&ofdev->dev, bd_size, &mal->bd_dma,
591 GFP_KERNEL);
592 if (mal->bd_virt == NULL) {
593 printk(KERN_ERR
594 "mal%d: out of memory allocating RX/TX descriptors!\n",
595 index);
596 err = -ENOMEM;
597 goto fail_unmap;
598 }
599 memset(mal->bd_virt, 0, bd_size);
600
601 for (i = 0; i < mal->num_tx_chans; ++i)
602 set_mal_dcrn(mal, MAL_TXCTPR(i), mal->bd_dma +
603 sizeof(struct mal_descriptor) *
604 mal_tx_bd_offset(mal, i));
605
606 for (i = 0; i < mal->num_rx_chans; ++i)
607 set_mal_dcrn(mal, MAL_RXCTPR(i), mal->bd_dma +
608 sizeof(struct mal_descriptor) *
609 mal_rx_bd_offset(mal, i));
610
611 err = request_irq(mal->serr_irq, mal_serr, 0, "MAL SERR", mal);
612 if (err)
613 goto fail2;
614 err = request_irq(mal->txde_irq, mal_txde, 0, "MAL TX DE", mal);
615 if (err)
616 goto fail3;
617 err = request_irq(mal->txeob_irq, mal_txeob, 0, "MAL TX EOB", mal);
618 if (err)
619 goto fail4;
620 err = request_irq(mal->rxde_irq, mal_rxde, 0, "MAL RX DE", mal);
621 if (err)
622 goto fail5;
623 err = request_irq(mal->rxeob_irq, mal_rxeob, 0, "MAL RX EOB", mal);
624 if (err)
625 goto fail6;
626
627 /* Enable all MAL SERR interrupt sources */
628 if (mal->version == 2)
629 set_mal_dcrn(mal, MAL_IER, MAL2_IER_EVENTS);
630 else
631 set_mal_dcrn(mal, MAL_IER, MAL1_IER_EVENTS);
632
633 /* Enable EOB interrupt */
634 mal_enable_eob_irq(mal);
635
636 printk(KERN_INFO
637 "MAL v%d %s, %d TX channels, %d RX channels\n",
638 mal->version, ofdev->node->full_name,
639 mal->num_tx_chans, mal->num_rx_chans);
640
641 /* Advertise this instance to the rest of the world */
642 wmb();
643 dev_set_drvdata(&ofdev->dev, mal);
644
645 mal_dbg_register(mal);
646
647 return 0;
648
649 fail6:
650 free_irq(mal->rxde_irq, mal);
651 fail5:
652 free_irq(mal->txeob_irq, mal);
653 fail4:
654 free_irq(mal->txde_irq, mal);
655 fail3:
656 free_irq(mal->serr_irq, mal);
657 fail2:
658 dma_free_coherent(&ofdev->dev, bd_size, mal->bd_virt, mal->bd_dma);
659 fail_unmap:
660 dcr_unmap(mal->dcr_host, 0x100);
661 fail:
662 kfree(mal);
663
664 return err;
665 }
666
667 static int __devexit mal_remove(struct of_device *ofdev)
668 {
669 struct mal_instance *mal = dev_get_drvdata(&ofdev->dev);
670
671 MAL_DBG(mal, "remove" NL);
672
673 /* Synchronize with scheduled polling */
674 napi_disable(&mal->napi);
675
676 if (!list_empty(&mal->list)) {
677 /* This is *very* bad */
678 printk(KERN_EMERG
679 "mal%d: commac list is not empty on remove!\n",
680 mal->index);
681 WARN_ON(1);
682 }
683
684 dev_set_drvdata(&ofdev->dev, NULL);
685
686 free_irq(mal->serr_irq, mal);
687 free_irq(mal->txde_irq, mal);
688 free_irq(mal->txeob_irq, mal);
689 free_irq(mal->rxde_irq, mal);
690 free_irq(mal->rxeob_irq, mal);
691
692 mal_reset(mal);
693
694 mal_dbg_unregister(mal);
695
696 dma_free_coherent(&ofdev->dev,
697 sizeof(struct mal_descriptor) *
698 (NUM_TX_BUFF * mal->num_tx_chans +
699 NUM_RX_BUFF * mal->num_rx_chans), mal->bd_virt,
700 mal->bd_dma);
701 kfree(mal);
702
703 return 0;
704 }
705
706 static struct of_device_id mal_platform_match[] =
707 {
708 {
709 .compatible = "ibm,mcmal",
710 },
711 {
712 .compatible = "ibm,mcmal2",
713 },
714 /* Backward compat */
715 {
716 .type = "mcmal-dma",
717 .compatible = "ibm,mcmal",
718 },
719 {
720 .type = "mcmal-dma",
721 .compatible = "ibm,mcmal2",
722 },
723 {},
724 };
725
726 static struct of_platform_driver mal_of_driver = {
727 .name = "mcmal",
728 .match_table = mal_platform_match,
729
730 .probe = mal_probe,
731 .remove = mal_remove,
732 };
733
734 int __init mal_init(void)
735 {
736 return of_register_platform_driver(&mal_of_driver);
737 }
738
739 void mal_exit(void)
740 {
741 of_unregister_platform_driver(&mal_of_driver);
742 }
Linux for Ginger Game Console