drivers/net/meth.c

   1 /*
   2  * meth.c -- O2 Builtin 10/100 Ethernet driver
   3  *
   4  * Copyright (C) 2001-2003 Ilya Volynets
   5  *
   6  *      This program is free software; you can redistribute it and/or
   7  *      modify it under the terms of the GNU General Public License
   8  *      as published by the Free Software Foundation; either version
   9  *      2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/slab.h>
  18 #include <linux/errno.h>
  19 #include <linux/types.h>
  20 #include <linux/interrupt.h>
  21
  22 #include <linux/in.h>
  23 #include <linux/in6.h>
  24 #include <linux/device.h> /* struct device, et al */
  25 #include <linux/netdevice.h>   /* struct device, and other headers */
  26 #include <linux/etherdevice.h> /* eth_type_trans */
  27 #include <linux/ip.h>          /* struct iphdr */
  28 #include <linux/tcp.h>         /* struct tcphdr */
  29 #include <linux/skbuff.h>
  30 #include <linux/mii.h>         /* MII definitions */
  31
  32 #include <asm/ip32/mace.h>
  33 #include <asm/ip32/ip32_ints.h>
  34
  35 #include <asm/io.h>
  36
  37 #include "meth.h"
  38
  39 #ifndef MFE_DEBUG
  40 #define MFE_DEBUG 0
  41 #endif
  42
  43 #if MFE_DEBUG>=1
  44 #define DPRINTK(str,args...) printk(KERN_DEBUG "meth: %s: " str, __FUNCTION__ , ## args)
  45 #define MFE_RX_DEBUG 2
  46 #else
  47 #define DPRINTK(str,args...)
  48 #define MFE_RX_DEBUG 0
  49 #endif
  50
  51
  52 static const char *meth_str="SGI O2 Fast Ethernet";
  53
  54 #define HAVE_TX_TIMEOUT
  55 /* The maximum time waited (in jiffies) before assuming a Tx failed. (400ms) */
  56 #define TX_TIMEOUT (400*HZ/1000)
  57
  58 #ifdef HAVE_TX_TIMEOUT
  59 static int timeout = TX_TIMEOUT;
  60 module_param(timeout, int, 0);
  61 #endif
  62
  63 /*
  64  * This structure is private to each device. It is used to pass
  65  * packets in and out, so there is place for a packet
  66  */
  67 struct meth_private {
  68         /* in-memory copy of MAC Control register */
  69         unsigned long mac_ctrl;
  70         /* in-memory copy of DMA Control register */
  71         unsigned long dma_ctrl;
  72         /* address of PHY, used by mdio_* functions, initialized in mdio_probe */
  73         unsigned long phy_addr;
  74         tx_packet *tx_ring;
  75         dma_addr_t tx_ring_dma;
  76         struct sk_buff *tx_skbs[TX_RING_ENTRIES];
  77         dma_addr_t tx_skb_dmas[TX_RING_ENTRIES];
  78         unsigned long tx_read, tx_write, tx_count;
  79
  80         rx_packet *rx_ring[RX_RING_ENTRIES];
  81         dma_addr_t rx_ring_dmas[RX_RING_ENTRIES];
  82         struct sk_buff *rx_skbs[RX_RING_ENTRIES];
  83         unsigned long rx_write;
  84
  85         spinlock_t meth_lock;
  86 };
  87
  88 static void meth_tx_timeout(struct net_device *dev);
  89 static irqreturn_t meth_interrupt(int irq, void *dev_id);
  90
  91 /* global, initialized in ip32-setup.c */
  92 char o2meth_eaddr[8]={0,0,0,0,0,0,0,0};
  93
  94 static inline void load_eaddr(struct net_device *dev)
  95 {
  96         int i;
  97         DECLARE_MAC_BUF(mac);
  98         u64 macaddr;
  99
 100         DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr));
 101         macaddr = 0;
 102         for (i = 0; i < 6; i++)
 103                 macaddr |= dev->dev_addr[i] << ((5 - i) * 8);
 104
 105         mace->eth.mac_addr = macaddr;
 106 }
 107
 108 /*
 109  * Waits for BUSY status of mdio bus to clear
 110  */
 111 #define WAIT_FOR_PHY(___rval)                                   \
 112         while ((___rval = mace->eth.phy_data) & MDIO_BUSY) {    \
 113                 udelay(25);                                     \
 114         }
 115 /*read phy register, return value read */
 116 static unsigned long mdio_read(struct meth_private *priv, unsigned long phyreg)
 117 {
 118         unsigned long rval;
 119         WAIT_FOR_PHY(rval);
 120         mace->eth.phy_regs = (priv->phy_addr << 5) | (phyreg & 0x1f);
 121         udelay(25);
 122         mace->eth.phy_trans_go = 1;
 123         udelay(25);
 124         WAIT_FOR_PHY(rval);
 125         return rval & MDIO_DATA_MASK;
 126 }
 127
 128 static int mdio_probe(struct meth_private *priv)
 129 {
 130         int i;
 131         unsigned long p2, p3;
 132         /* check if phy is detected already */
 133         if(priv->phy_addr>=0&&priv->phy_addr<32)
 134                 return 0;
 135         spin_lock(&priv->meth_lock);
 136         for (i=0;i<32;++i){
 137                 priv->phy_addr=i;
 138                 p2=mdio_read(priv,2);
 139                 p3=mdio_read(priv,3);
 140 #if MFE_DEBUG>=2
 141                 switch ((p2<<12)|(p3>>4)){
 142                 case PHY_QS6612X:
 143                         DPRINTK("PHY is QS6612X\n");
 144                         break;
 145                 case PHY_ICS1889:
 146                         DPRINTK("PHY is ICS1889\n");
 147                         break;
 148                 case PHY_ICS1890:
 149                         DPRINTK("PHY is ICS1890\n");
 150                         break;
 151                 case PHY_DP83840:
 152                         DPRINTK("PHY is DP83840\n");
 153                         break;
 154                 }
 155 #endif
 156                 if(p2!=0xffff&&p2!=0x0000){
 157                         DPRINTK("PHY code: %x\n",(p2<<12)|(p3>>4));
 158                         break;
 159                 }
 160         }
 161         spin_unlock(&priv->meth_lock);
 162         if(priv->phy_addr<32) {
 163                 return 0;
 164         }
 165         DPRINTK("Oopsie! PHY is not known!\n");
 166         priv->phy_addr=-1;
 167         return -ENODEV;
 168 }
 169
 170 static void meth_check_link(struct net_device *dev)
 171 {
 172         struct meth_private *priv = netdev_priv(dev);
 173         unsigned long mii_advertising = mdio_read(priv, 4);
 174         unsigned long mii_partner = mdio_read(priv, 5);
 175         unsigned long negotiated = mii_advertising & mii_partner;
 176         unsigned long duplex, speed;
 177
 178         if (mii_partner == 0xffff)
 179                 return;
 180
 181         speed = (negotiated & 0x0380) ? METH_100MBIT : 0;
 182         duplex = ((negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040) ?
 183                  METH_PHY_FDX : 0;
 184
 185         if ((priv->mac_ctrl & METH_PHY_FDX) ^ duplex) {
 186                 DPRINTK("Setting %s-duplex\n", duplex ? "full" : "half");
 187                 if (duplex)
 188                         priv->mac_ctrl |= METH_PHY_FDX;
 189                 else
 190                         priv->mac_ctrl &= ~METH_PHY_FDX;
 191                 mace->eth.mac_ctrl = priv->mac_ctrl;
 192         }
 193
 194         if ((priv->mac_ctrl & METH_100MBIT) ^ speed) {
 195                 DPRINTK("Setting %dMbs mode\n", speed ? 100 : 10);
 196                 if (duplex)
 197                         priv->mac_ctrl |= METH_100MBIT;
 198                 else
 199                         priv->mac_ctrl &= ~METH_100MBIT;
 200                 mace->eth.mac_ctrl = priv->mac_ctrl;
 201         }
 202 }
 203
 204
 205 static int meth_init_tx_ring(struct meth_private *priv)
 206 {
 207         /* Init TX ring */
 208         priv->tx_ring = dma_alloc_coherent(NULL, TX_RING_BUFFER_SIZE,
 209                                            &priv->tx_ring_dma, GFP_ATOMIC);
 210         if (!priv->tx_ring)
 211                 return -ENOMEM;
 212         memset(priv->tx_ring, 0, TX_RING_BUFFER_SIZE);
 213         priv->tx_count = priv->tx_read = priv->tx_write = 0;
 214         mace->eth.tx_ring_base = priv->tx_ring_dma;
 215         /* Now init skb save area */
 216         memset(priv->tx_skbs, 0, sizeof(priv->tx_skbs));
 217         memset(priv->tx_skb_dmas, 0, sizeof(priv->tx_skb_dmas));
 218         return 0;
 219 }
 220
 221 static int meth_init_rx_ring(struct meth_private *priv)
 222 {
 223         int i;
 224
 225         for (i = 0; i < RX_RING_ENTRIES; i++) {
 226                 priv->rx_skbs[i] = alloc_skb(METH_RX_BUFF_SIZE, 0);
 227                 /* 8byte status vector + 3quad padding + 2byte padding,
 228                  * to put data on 64bit aligned boundary */
 229                 skb_reserve(priv->rx_skbs[i],METH_RX_HEAD);
 230                 priv->rx_ring[i]=(rx_packet*)(priv->rx_skbs[i]->head);
 231                 /* I'll need to re-sync it after each RX */
 232                 priv->rx_ring_dmas[i] =
 233                         dma_map_single(NULL, priv->rx_ring[i],
 234                                        METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
 235                 mace->eth.rx_fifo = priv->rx_ring_dmas[i];
 236         }
 237         priv->rx_write = 0;
 238         return 0;
 239 }
 240 static void meth_free_tx_ring(struct meth_private *priv)
 241 {
 242         int i;
 243
 244         /* Remove any pending skb */
 245         for (i = 0; i < TX_RING_ENTRIES; i++) {
 246                 if (priv->tx_skbs[i])
 247                         dev_kfree_skb(priv->tx_skbs[i]);
 248                 priv->tx_skbs[i] = NULL;
 249         }
 250         dma_free_coherent(NULL, TX_RING_BUFFER_SIZE, priv->tx_ring,
 251                           priv->tx_ring_dma);
 252 }
 253
 254 /* Presumes RX DMA engine is stopped, and RX fifo ring is reset */
 255 static void meth_free_rx_ring(struct meth_private *priv)
 256 {
 257         int i;
 258
 259         for (i = 0; i < RX_RING_ENTRIES; i++) {
 260                 dma_unmap_single(NULL, priv->rx_ring_dmas[i],
 261                                  METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
 262                 priv->rx_ring[i] = 0;
 263                 priv->rx_ring_dmas[i] = 0;
 264                 kfree_skb(priv->rx_skbs[i]);
 265         }
 266 }
 267
 268 int meth_reset(struct net_device *dev)
 269 {
 270         struct meth_private *priv = netdev_priv(dev);
 271
 272         /* Reset card */
 273         mace->eth.mac_ctrl = SGI_MAC_RESET;
 274         udelay(1);
 275         mace->eth.mac_ctrl = 0;
 276         udelay(25);
 277
 278         /* Load ethernet address */
 279         load_eaddr(dev);
 280         /* Should load some "errata", but later */
 281
 282         /* Check for device */
 283         if (mdio_probe(priv) < 0) {
 284                 DPRINTK("Unable to find PHY\n");
 285                 return -ENODEV;
 286         }
 287
 288         /* Initial mode: 10 | Half-duplex | Accept normal packets */
 289         priv->mac_ctrl = METH_ACCEPT_MCAST | METH_DEFAULT_IPG;
 290         if (dev->flags | IFF_PROMISC)
 291                 priv->mac_ctrl |= METH_PROMISC;
 292         mace->eth.mac_ctrl = priv->mac_ctrl;
 293
 294         /* Autonegotiate speed and duplex mode */
 295         meth_check_link(dev);
 296
 297         /* Now set dma control, but don't enable DMA, yet */
 298         priv->dma_ctrl = (4 << METH_RX_OFFSET_SHIFT) |
 299                          (RX_RING_ENTRIES << METH_RX_DEPTH_SHIFT);
 300         mace->eth.dma_ctrl = priv->dma_ctrl;
 301
 302         return 0;
 303 }
 304
 305 /*============End Helper Routines=====================*/
 306
 307 /*
 308  * Open and close
 309  */
 310 static int meth_open(struct net_device *dev)
 311 {
 312         struct meth_private *priv = netdev_priv(dev);
 313         int ret;
 314
 315         priv->phy_addr = -1;    /* No PHY is known yet... */
 316
 317         /* Initialize the hardware */
 318         ret = meth_reset(dev);
 319         if (ret < 0)
 320                 return ret;
 321
 322         /* Allocate the ring buffers */
 323         ret = meth_init_tx_ring(priv);
 324         if (ret < 0)
 325                 return ret;
 326         ret = meth_init_rx_ring(priv);
 327         if (ret < 0)
 328                 goto out_free_tx_ring;
 329
 330         ret = request_irq(dev->irq, meth_interrupt, 0, meth_str, dev);
 331         if (ret) {
 332                 printk(KERN_ERR "%s: Can't get irq %d\n", dev->name, dev->irq);
 333                 goto out_free_rx_ring;
 334         }
 335
 336         /* Start DMA */
 337         priv->dma_ctrl |= METH_DMA_TX_EN | /*METH_DMA_TX_INT_EN |*/
 338                           METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
 339         mace->eth.dma_ctrl = priv->dma_ctrl;
 340
 341         DPRINTK("About to start queue\n");
 342         netif_start_queue(dev);
 343
 344         return 0;
 345
 346 out_free_rx_ring:
 347         meth_free_rx_ring(priv);
 348 out_free_tx_ring:
 349         meth_free_tx_ring(priv);
 350
 351         return ret;
 352 }
 353
 354 static int meth_release(struct net_device *dev)
 355 {
 356         struct meth_private *priv = netdev_priv(dev);
 357
 358         DPRINTK("Stopping queue\n");
 359         netif_stop_queue(dev); /* can't transmit any more */
 360         /* shut down DMA */
 361         priv->dma_ctrl &= ~(METH_DMA_TX_EN | METH_DMA_TX_INT_EN |
 362                             METH_DMA_RX_EN | METH_DMA_RX_INT_EN);
 363         mace->eth.dma_ctrl = priv->dma_ctrl;
 364         free_irq(dev->irq, dev);
 365         meth_free_tx_ring(priv);
 366         meth_free_rx_ring(priv);
 367
 368         return 0;
 369 }
 370
 371 /*
 372  * Receive a packet: retrieve, encapsulate and pass over to upper levels
 373  */
 374 static void meth_rx(struct net_device* dev, unsigned long int_status)
 375 {
 376         struct sk_buff *skb;
 377         unsigned long status;
 378         struct meth_private *priv = netdev_priv(dev);
 379         unsigned long fifo_rptr = (int_status & METH_INT_RX_RPTR_MASK) >> 8;
 380
 381         spin_lock(&priv->meth_lock);
 382         priv->dma_ctrl &= ~METH_DMA_RX_INT_EN;
 383         mace->eth.dma_ctrl = priv->dma_ctrl;
 384         spin_unlock(&priv->meth_lock);
 385
 386         if (int_status & METH_INT_RX_UNDERFLOW) {
 387                 fifo_rptr = (fifo_rptr - 1) & 0x0f;
 388         }
 389         while (priv->rx_write != fifo_rptr) {
 390                 dma_unmap_single(NULL, priv->rx_ring_dmas[priv->rx_write],
 391                                  METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
 392                 status = priv->rx_ring[priv->rx_write]->status.raw;
 393 #if MFE_DEBUG
 394                 if (!(status & METH_RX_ST_VALID)) {
 395                         DPRINTK("Not received? status=%016lx\n",status);
 396                 }
 397 #endif
 398                 if ((!(status & METH_RX_STATUS_ERRORS)) && (status & METH_RX_ST_VALID)) {
 399                         int len = (status & 0xffff) - 4; /* omit CRC */
 400                         /* length sanity check */
 401                         if (len < 60 || len > 1518) {
 402                                 printk(KERN_DEBUG "%s: bogus packet size: %ld, status=%#2lx.\n",
 403                                        dev->name, priv->rx_write,
 404                                        priv->rx_ring[priv->rx_write]->status.raw);
 405                                 dev->stats.rx_errors++;
 406                                 dev->stats.rx_length_errors++;
 407                                 skb = priv->rx_skbs[priv->rx_write];
 408                         } else {
 409                                 skb = alloc_skb(METH_RX_BUFF_SIZE, GFP_ATOMIC);
 410                                 if (!skb) {
 411                                         /* Ouch! No memory! Drop packet on the floor */
 412                                         DPRINTK("No mem: dropping packet\n");
 413                                         dev->stats.rx_dropped++;
 414                                         skb = priv->rx_skbs[priv->rx_write];
 415                                 } else {
 416                                         struct sk_buff *skb_c = priv->rx_skbs[priv->rx_write];
 417                                         /* 8byte status vector + 3quad padding + 2byte padding,
 418                                          * to put data on 64bit aligned boundary */
 419                                         skb_reserve(skb, METH_RX_HEAD);
 420                                         /* Write metadata, and then pass to the receive level */
 421                                         skb_put(skb_c, len);
 422                                         priv->rx_skbs[priv->rx_write] = skb;
 423                                         skb_c->protocol = eth_type_trans(skb_c, dev);
 424                                         dev->last_rx = jiffies;
 425                                         dev->stats.rx_packets++;
 426                                         dev->stats.rx_bytes += len;
 427                                         netif_rx(skb_c);
 428                                 }
 429                         }
 430                 } else {
 431                         dev->stats.rx_errors++;
 432                         skb=priv->rx_skbs[priv->rx_write];
 433 #if MFE_DEBUG>0
 434                         printk(KERN_WARNING "meth: RX error: status=0x%016lx\n",status);
 435                         if(status&METH_RX_ST_RCV_CODE_VIOLATION)
 436                                 printk(KERN_WARNING "Receive Code Violation\n");
 437                         if(status&METH_RX_ST_CRC_ERR)
 438                                 printk(KERN_WARNING "CRC error\n");
 439                         if(status&METH_RX_ST_INV_PREAMBLE_CTX)
 440                                 printk(KERN_WARNING "Invalid Preamble Context\n");
 441                         if(status&METH_RX_ST_LONG_EVT_SEEN)
 442                                 printk(KERN_WARNING "Long Event Seen...\n");
 443                         if(status&METH_RX_ST_BAD_PACKET)
 444                                 printk(KERN_WARNING "Bad Packet\n");
 445                         if(status&METH_RX_ST_CARRIER_EVT_SEEN)
 446                                 printk(KERN_WARNING "Carrier Event Seen\n");
 447 #endif
 448                 }
 449                 priv->rx_ring[priv->rx_write] = (rx_packet*)skb->head;
 450                 priv->rx_ring[priv->rx_write]->status.raw = 0;
 451                 priv->rx_ring_dmas[priv->rx_write] =
 452                         dma_map_single(NULL, priv->rx_ring[priv->rx_write],
 453                                        METH_RX_BUFF_SIZE, DMA_FROM_DEVICE);
 454                 mace->eth.rx_fifo = priv->rx_ring_dmas[priv->rx_write];
 455                 ADVANCE_RX_PTR(priv->rx_write);
 456         }
 457         spin_lock(&priv->meth_lock);
 458         /* In case there was underflow, and Rx DMA was disabled */
 459         priv->dma_ctrl |= METH_DMA_RX_INT_EN | METH_DMA_RX_EN;
 460         mace->eth.dma_ctrl = priv->dma_ctrl;
 461         mace->eth.int_stat = METH_INT_RX_THRESHOLD;
 462         spin_unlock(&priv->meth_lock);
 463 }
 464
 465 static int meth_tx_full(struct net_device *dev)
 466 {
 467         struct meth_private *priv = netdev_priv(dev);
 468
 469         return (priv->tx_count >= TX_RING_ENTRIES - 1);
 470 }
 471
 472 static void meth_tx_cleanup(struct net_device* dev, unsigned long int_status)
 473 {
 474         struct meth_private *priv = netdev_priv(dev);
 475         unsigned long status;
 476         struct sk_buff *skb;
 477         unsigned long rptr = (int_status&TX_INFO_RPTR) >> 16;
 478
 479         spin_lock(&priv->meth_lock);
 480
 481         /* Stop DMA notification */
 482         priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
 483         mace->eth.dma_ctrl = priv->dma_ctrl;
 484
 485         while (priv->tx_read != rptr) {
 486                 skb = priv->tx_skbs[priv->tx_read];
 487                 status = priv->tx_ring[priv->tx_read].header.raw;
 488 #if MFE_DEBUG>=1
 489                 if (priv->tx_read == priv->tx_write)
 490                         DPRINTK("Auchi! tx_read=%d,tx_write=%d,rptr=%d?\n", priv->tx_read, priv->tx_write,rptr);
 491 #endif
 492                 if (status & METH_TX_ST_DONE) {
 493                         if (status & METH_TX_ST_SUCCESS){
 494                                 dev->stats.tx_packets++;
 495                                 dev->stats.tx_bytes += skb->len;
 496                         } else {
 497                                 dev->stats.tx_errors++;
 498 #if MFE_DEBUG>=1
 499                                 DPRINTK("TX error: status=%016lx <",status);
 500                                 if(status & METH_TX_ST_SUCCESS)
 501                                         printk(" SUCCESS");
 502                                 if(status & METH_TX_ST_TOOLONG)
 503                                         printk(" TOOLONG");
 504                                 if(status & METH_TX_ST_UNDERRUN)
 505                                         printk(" UNDERRUN");
 506                                 if(status & METH_TX_ST_EXCCOLL)
 507                                         printk(" EXCCOLL");
 508                                 if(status & METH_TX_ST_DEFER)
 509                                         printk(" DEFER");
 510                                 if(status & METH_TX_ST_LATECOLL)
 511                                         printk(" LATECOLL");
 512                                 printk(" >\n");
 513 #endif
 514                         }
 515                 } else {
 516                         DPRINTK("RPTR points us here, but packet not done?\n");
 517                         break;
 518                 }
 519                 dev_kfree_skb_irq(skb);
 520                 priv->tx_skbs[priv->tx_read] = NULL;
 521                 priv->tx_ring[priv->tx_read].header.raw = 0;
 522                 priv->tx_read = (priv->tx_read+1)&(TX_RING_ENTRIES-1);
 523                 priv->tx_count--;
 524         }
 525
 526         /* wake up queue if it was stopped */
 527         if (netif_queue_stopped(dev) && !meth_tx_full(dev)) {
 528                 netif_wake_queue(dev);
 529         }
 530
 531         mace->eth.int_stat = METH_INT_TX_EMPTY | METH_INT_TX_PKT;
 532         spin_unlock(&priv->meth_lock);
 533 }
 534
 535 static void meth_error(struct net_device* dev, unsigned status)
 536 {
 537         struct meth_private *priv = netdev_priv(dev);
 538
 539         printk(KERN_WARNING "meth: error status: 0x%08x\n",status);
 540         /* check for errors too... */
 541         if (status & (METH_INT_TX_LINK_FAIL))
 542                 printk(KERN_WARNING "meth: link failure\n");
 543         /* Should I do full reset in this case? */
 544         if (status & (METH_INT_MEM_ERROR))
 545                 printk(KERN_WARNING "meth: memory error\n");
 546         if (status & (METH_INT_TX_ABORT))
 547                 printk(KERN_WARNING "meth: aborted\n");
 548         if (status & (METH_INT_RX_OVERFLOW))
 549                 printk(KERN_WARNING "meth: Rx overflow\n");
 550         if (status & (METH_INT_RX_UNDERFLOW)) {
 551                 printk(KERN_WARNING "meth: Rx underflow\n");
 552                 spin_lock(&priv->meth_lock);
 553                 mace->eth.int_stat = METH_INT_RX_UNDERFLOW;
 554                 /* more underflow interrupts will be delivered,
 555                  * effectively throwing us into an infinite loop.
 556                  *  Thus I stop processing Rx in this case. */
 557                 priv->dma_ctrl &= ~METH_DMA_RX_EN;
 558                 mace->eth.dma_ctrl = priv->dma_ctrl;
 559                 DPRINTK("Disabled meth Rx DMA temporarily\n");
 560                 spin_unlock(&priv->meth_lock);
 561         }
 562         mace->eth.int_stat = METH_INT_ERROR;
 563 }
 564
 565 /*
 566  * The typical interrupt entry point
 567  */
 568 static irqreturn_t meth_interrupt(int irq, void *dev_id)
 569 {
 570         struct net_device *dev = (struct net_device *)dev_id;
 571         struct meth_private *priv = netdev_priv(dev);
 572         unsigned long status;
 573
 574         status = mace->eth.int_stat;
 575         while (status & 0xff) {
 576                 /* First handle errors - if we get Rx underflow,
 577                  * Rx DMA will be disabled, and Rx handler will reenable
 578                  * it. I don't think it's possible to get Rx underflow,
 579                  * without getting Rx interrupt */
 580                 if (status & METH_INT_ERROR) {
 581                         meth_error(dev, status);
 582                 }
 583                 if (status & (METH_INT_TX_EMPTY | METH_INT_TX_PKT)) {
 584                         /* a transmission is over: free the skb */
 585                         meth_tx_cleanup(dev, status);
 586                 }
 587                 if (status & METH_INT_RX_THRESHOLD) {
 588                         if (!(priv->dma_ctrl & METH_DMA_RX_INT_EN))
 589                                 break;
 590                         /* send it to meth_rx for handling */
 591                         meth_rx(dev, status);
 592                 }
 593                 status = mace->eth.int_stat;
 594         }
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 /*
 600  * Transmits packets that fit into TX descriptor (are <=120B)
 601  */
 602 static void meth_tx_short_prepare(struct meth_private *priv,
 603                                   struct sk_buff *skb)
 604 {
 605         tx_packet *desc = &priv->tx_ring[priv->tx_write];
 606         int len = (skb->len < ETH_ZLEN) ? ETH_ZLEN : skb->len;
 607
 608         desc->header.raw = METH_TX_CMD_INT_EN | (len-1) | ((128-len) << 16);
 609         /* maybe I should set whole thing to 0 first... */
 610         skb_copy_from_linear_data(skb, desc->data.dt + (120 - len), skb->len);
 611         if (skb->len < len)
 612                 memset(desc->data.dt + 120 - len + skb->len, 0, len-skb->len);
 613 }
 614 #define TX_CATBUF1 BIT(25)
 615 static void meth_tx_1page_prepare(struct meth_private *priv,
 616                                   struct sk_buff *skb)
 617 {
 618         tx_packet *desc = &priv->tx_ring[priv->tx_write];
 619         void *buffer_data = (void *)(((unsigned long)skb->data + 7) & ~7);
 620         int unaligned_len = (int)((unsigned long)buffer_data - (unsigned long)skb->data);
 621         int buffer_len = skb->len - unaligned_len;
 622         dma_addr_t catbuf;
 623
 624         desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | (skb->len - 1);
 625
 626         /* unaligned part */
 627         if (unaligned_len) {
 628                 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
 629                               unaligned_len);
 630                 desc->header.raw |= (128 - unaligned_len) << 16;
 631         }
 632
 633         /* first page */
 634         catbuf = dma_map_single(NULL, buffer_data, buffer_len,
 635                                 DMA_TO_DEVICE);
 636         desc->data.cat_buf[0].form.start_addr = catbuf >> 3;
 637         desc->data.cat_buf[0].form.len = buffer_len - 1;
 638 }
 639 #define TX_CATBUF2 BIT(26)
 640 static void meth_tx_2page_prepare(struct meth_private *priv,
 641                                   struct sk_buff *skb)
 642 {
 643         tx_packet *desc = &priv->tx_ring[priv->tx_write];
 644         void *buffer1_data = (void *)(((unsigned long)skb->data + 7) & ~7);
 645         void *buffer2_data = (void *)PAGE_ALIGN((unsigned long)skb->data);
 646         int unaligned_len = (int)((unsigned long)buffer1_data - (unsigned long)skb->data);
 647         int buffer1_len = (int)((unsigned long)buffer2_data - (unsigned long)buffer1_data);
 648         int buffer2_len = skb->len - buffer1_len - unaligned_len;
 649         dma_addr_t catbuf1, catbuf2;
 650
 651         desc->header.raw = METH_TX_CMD_INT_EN | TX_CATBUF1 | TX_CATBUF2| (skb->len - 1);
 652         /* unaligned part */
 653         if (unaligned_len){
 654                 skb_copy_from_linear_data(skb, desc->data.dt + (120 - unaligned_len),
 655                               unaligned_len);
 656                 desc->header.raw |= (128 - unaligned_len) << 16;
 657         }
 658
 659         /* first page */
 660         catbuf1 = dma_map_single(NULL, buffer1_data, buffer1_len,
 661                                  DMA_TO_DEVICE);
 662         desc->data.cat_buf[0].form.start_addr = catbuf1 >> 3;
 663         desc->data.cat_buf[0].form.len = buffer1_len - 1;
 664         /* second page */
 665         catbuf2 = dma_map_single(NULL, buffer2_data, buffer2_len,
 666                                  DMA_TO_DEVICE);
 667         desc->data.cat_buf[1].form.start_addr = catbuf2 >> 3;
 668         desc->data.cat_buf[1].form.len = buffer2_len - 1;
 669 }
 670
 671 static void meth_add_to_tx_ring(struct meth_private *priv, struct sk_buff *skb)
 672 {
 673         /* Remember the skb, so we can free it at interrupt time */
 674         priv->tx_skbs[priv->tx_write] = skb;
 675         if (skb->len <= 120) {
 676                 /* Whole packet fits into descriptor */
 677                 meth_tx_short_prepare(priv, skb);
 678         } else if (PAGE_ALIGN((unsigned long)skb->data) !=
 679                    PAGE_ALIGN((unsigned long)skb->data + skb->len - 1)) {
 680                 /* Packet crosses page boundary */
 681                 meth_tx_2page_prepare(priv, skb);
 682         } else {
 683                 /* Packet is in one page */
 684                 meth_tx_1page_prepare(priv, skb);
 685         }
 686         priv->tx_write = (priv->tx_write + 1) & (TX_RING_ENTRIES - 1);
 687         mace->eth.tx_info = priv->tx_write;
 688         priv->tx_count++;
 689 }
 690
 691 /*
 692  * Transmit a packet (called by the kernel)
 693  */
 694 static int meth_tx(struct sk_buff *skb, struct net_device *dev)
 695 {
 696         struct meth_private *priv = netdev_priv(dev);
 697         unsigned long flags;
 698
 699         spin_lock_irqsave(&priv->meth_lock, flags);
 700         /* Stop DMA notification */
 701         priv->dma_ctrl &= ~(METH_DMA_TX_INT_EN);
 702         mace->eth.dma_ctrl = priv->dma_ctrl;
 703
 704         meth_add_to_tx_ring(priv, skb);
 705         dev->trans_start = jiffies; /* save the timestamp */
 706
 707         /* If TX ring is full, tell the upper layer to stop sending packets */
 708         if (meth_tx_full(dev)) {
 709                 printk(KERN_DEBUG "TX full: stopping\n");
 710                 netif_stop_queue(dev);
 711         }
 712
 713         /* Restart DMA notification */
 714         priv->dma_ctrl |= METH_DMA_TX_INT_EN;
 715         mace->eth.dma_ctrl = priv->dma_ctrl;
 716
 717         spin_unlock_irqrestore(&priv->meth_lock, flags);
 718
 719         return 0;
 720 }
 721
 722 /*
 723  * Deal with a transmit timeout.
 724  */
 725 static void meth_tx_timeout(struct net_device *dev)
 726 {
 727         struct meth_private *priv = netdev_priv(dev);
 728         unsigned long flags;
 729
 730         printk(KERN_WARNING "%s: transmit timed out\n", dev->name);
 731
 732         /* Protect against concurrent rx interrupts */
 733         spin_lock_irqsave(&priv->meth_lock,flags);
 734
 735         /* Try to reset the interface. */
 736         meth_reset(dev);
 737
 738         dev->stats.tx_errors++;
 739
 740         /* Clear all rings */
 741         meth_free_tx_ring(priv);
 742         meth_free_rx_ring(priv);
 743         meth_init_tx_ring(priv);
 744         meth_init_rx_ring(priv);
 745
 746         /* Restart dma */
 747         priv->dma_ctrl |= METH_DMA_TX_EN | METH_DMA_RX_EN | METH_DMA_RX_INT_EN;
 748         mace->eth.dma_ctrl = priv->dma_ctrl;
 749
 750         /* Enable interrupt */
 751         spin_unlock_irqrestore(&priv->meth_lock, flags);
 752
 753         dev->trans_start = jiffies;
 754         netif_wake_queue(dev);
 755
 756         return;
 757 }
 758
 759 /*
 760  * Ioctl commands
 761  */
 762 static int meth_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
 763 {
 764         /* XXX Not yet implemented */
 765         switch(cmd) {
 766         case SIOCGMIIPHY:
 767         case SIOCGMIIREG:
 768         case SIOCSMIIREG:
 769         default:
 770                 return -EOPNOTSUPP;
 771         }
 772 }
 773
 774 /*
 775  * Return statistics to the caller
 776  */
 777 /*
 778  * The init function.
 779  */
 780 static int __init meth_probe(struct platform_device *pdev)
 781 {
 782         struct net_device *dev;
 783         struct meth_private *priv;
 784         int err;
 785
 786         dev = alloc_etherdev(sizeof(struct meth_private));
 787         if (!dev)
 788                 return -ENOMEM;
 789
 790         dev->open            = meth_open;
 791         dev->stop            = meth_release;
 792         dev->hard_start_xmit = meth_tx;
 793         dev->do_ioctl        = meth_ioctl;
 794 #ifdef HAVE_TX_TIMEOUT
 795         dev->tx_timeout      = meth_tx_timeout;
 796         dev->watchdog_timeo  = timeout;
 797 #endif
 798         dev->irq             = MACE_ETHERNET_IRQ;
 799         dev->base_addr       = (unsigned long)&mace->eth;
 800         memcpy(dev->dev_addr, o2meth_eaddr, 6);
 801
 802         priv = netdev_priv(dev);
 803         spin_lock_init(&priv->meth_lock);
 804         SET_NETDEV_DEV(dev, &pdev->dev);
 805
 806         err = register_netdev(dev);
 807         if (err) {
 808                 free_netdev(dev);
 809                 return err;
 810         }
 811
 812         printk(KERN_INFO "%s: SGI MACE Ethernet rev. %d\n",
 813                dev->name, (unsigned int)(mace->eth.mac_ctrl >> 29));
 814         return 0;
 815 }
 816
 817 static int __exit meth_remove(struct platform_device *pdev)
 818 {
 819         struct net_device *dev = platform_get_drvdata(pdev);
 820
 821         unregister_netdev(dev);
 822         free_netdev(dev);
 823         platform_set_drvdata(pdev, NULL);
 824
 825         return 0;
 826 }
 827
 828 static struct platform_driver meth_driver = {
 829         .probe  = meth_probe,
 830         .remove = __devexit_p(meth_remove),
 831         .driver = {
 832                 .name   = "meth",
 833                 .owner  = THIS_MODULE,
 834         }
 835 };
 836
 837 static int __init meth_init_module(void)
 838 {
 839         int err;
 840
 841         err = platform_driver_register(&meth_driver);
 842         if (err)
 843                 printk(KERN_ERR "Driver registration failed\n");
 844
 845         return err;
 846 }
 847
 848 static void __exit meth_exit_module(void)
 849 {
 850         platform_driver_unregister(&meth_driver);
 851 }
 852
 853 module_init(meth_init_module);
 854 module_exit(meth_exit_module);
 855
 856 MODULE_AUTHOR("Ilya Volynets <ilya@theIlya.com>");
 857 MODULE_DESCRIPTION("SGI O2 Builtin Fast Ethernet driver");
 858 MODULE_LICENSE("GPL");
 859 MODULE_ALIAS("platform:meth");