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ALSA: ASoC: TLV320AIC3X: Modify only interface related bits in aic3x_set_dai_fmt
[linux-ginger.git] / drivers / net / myri10ge / myri10ge.c
blobe0d76c75aea0f6af724da31864c1ab2c58a356c4
1 /*************************************************************************
2 * myri10ge.c: Myricom Myri-10G Ethernet driver.
3 *
4 * Copyright (C) 2005 - 2007 Myricom, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of Myricom, Inc. nor the names of its contributors
16 * may be used to endorse or promote products derived from this software
17 * without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 *
31 *
32 * If the eeprom on your board is not recent enough, you will need to get a
33 * newer firmware image at:
34 * http://www.myri.com/scs/download-Myri10GE.html
35 *
36 * Contact Information:
37 * <help@myri.com>
38 * Myricom, Inc., 325N Santa Anita Avenue, Arcadia, CA 91006
39 *************************************************************************/
40
41 #include <linux/tcp.h>
42 #include <linux/netdevice.h>
43 #include <linux/skbuff.h>
44 #include <linux/string.h>
45 #include <linux/module.h>
46 #include <linux/pci.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/etherdevice.h>
49 #include <linux/if_ether.h>
50 #include <linux/if_vlan.h>
51 #include <linux/inet_lro.h>
52 #include <linux/ip.h>
53 #include <linux/inet.h>
54 #include <linux/in.h>
55 #include <linux/ethtool.h>
56 #include <linux/firmware.h>
57 #include <linux/delay.h>
58 #include <linux/version.h>
59 #include <linux/timer.h>
60 #include <linux/vmalloc.h>
61 #include <linux/crc32.h>
62 #include <linux/moduleparam.h>
63 #include <linux/io.h>
64 #include <linux/log2.h>
65 #include <net/checksum.h>
66 #include <net/ip.h>
67 #include <net/tcp.h>
68 #include <asm/byteorder.h>
69 #include <asm/io.h>
70 #include <asm/processor.h>
71 #ifdef CONFIG_MTRR
72 #include <asm/mtrr.h>
73 #endif
74
75 #include "myri10ge_mcp.h"
76 #include "myri10ge_mcp_gen_header.h"
77
78 #define MYRI10GE_VERSION_STR "1.3.99-1.347"
79
80 MODULE_DESCRIPTION("Myricom 10G driver (10GbE)");
81 MODULE_AUTHOR("Maintainer: help@myri.com");
82 MODULE_VERSION(MYRI10GE_VERSION_STR);
83 MODULE_LICENSE("Dual BSD/GPL");
84
85 #define MYRI10GE_MAX_ETHER_MTU 9014
86
87 #define MYRI10GE_ETH_STOPPED 0
88 #define MYRI10GE_ETH_STOPPING 1
89 #define MYRI10GE_ETH_STARTING 2
90 #define MYRI10GE_ETH_RUNNING 3
91 #define MYRI10GE_ETH_OPEN_FAILED 4
92
93 #define MYRI10GE_EEPROM_STRINGS_SIZE 256
94 #define MYRI10GE_MAX_SEND_DESC_TSO ((65536 / 2048) * 2)
95 #define MYRI10GE_MAX_LRO_DESCRIPTORS 8
96 #define MYRI10GE_LRO_MAX_PKTS 64
97
98 #define MYRI10GE_NO_CONFIRM_DATA htonl(0xffffffff)
99 #define MYRI10GE_NO_RESPONSE_RESULT 0xffffffff
100
101 #define MYRI10GE_ALLOC_ORDER 0
102 #define MYRI10GE_ALLOC_SIZE ((1 << MYRI10GE_ALLOC_ORDER) * PAGE_SIZE)
103 #define MYRI10GE_MAX_FRAGS_PER_FRAME (MYRI10GE_MAX_ETHER_MTU/MYRI10GE_ALLOC_SIZE + 1)
104
105 struct myri10ge_rx_buffer_state {
106 struct page *page;
107 int page_offset;
108 DECLARE_PCI_UNMAP_ADDR(bus)
109 DECLARE_PCI_UNMAP_LEN(len)
110 };
111
112 struct myri10ge_tx_buffer_state {
113 struct sk_buff *skb;
114 int last;
115 DECLARE_PCI_UNMAP_ADDR(bus)
116 DECLARE_PCI_UNMAP_LEN(len)
117 };
118
119 struct myri10ge_cmd {
120 u32 data0;
121 u32 data1;
122 u32 data2;
123 };
124
125 struct myri10ge_rx_buf {
126 struct mcp_kreq_ether_recv __iomem *lanai; /* lanai ptr for recv ring */
127 u8 __iomem *wc_fifo; /* w/c rx dma addr fifo address */
128 struct mcp_kreq_ether_recv *shadow; /* host shadow of recv ring */
129 struct myri10ge_rx_buffer_state *info;
130 struct page *page;
131 dma_addr_t bus;
132 int page_offset;
133 int cnt;
134 int fill_cnt;
135 int alloc_fail;
136 int mask; /* number of rx slots -1 */
137 int watchdog_needed;
138 };
139
140 struct myri10ge_tx_buf {
141 struct mcp_kreq_ether_send __iomem *lanai; /* lanai ptr for sendq */
142 u8 __iomem *wc_fifo; /* w/c send fifo address */
143 struct mcp_kreq_ether_send *req_list; /* host shadow of sendq */
144 char *req_bytes;
145 struct myri10ge_tx_buffer_state *info;
146 int mask; /* number of transmit slots -1 */
147 int req ____cacheline_aligned; /* transmit slots submitted */
148 int pkt_start; /* packets started */
149 int stop_queue;
150 int linearized;
151 int done ____cacheline_aligned; /* transmit slots completed */
152 int pkt_done; /* packets completed */
153 int wake_queue;
154 };
155
156 struct myri10ge_rx_done {
157 struct mcp_slot *entry;
158 dma_addr_t bus;
159 int cnt;
160 int idx;
161 struct net_lro_mgr lro_mgr;
162 struct net_lro_desc lro_desc[MYRI10GE_MAX_LRO_DESCRIPTORS];
163 };
164
165 struct myri10ge_slice_netstats {
166 unsigned long rx_packets;
167 unsigned long tx_packets;
168 unsigned long rx_bytes;
169 unsigned long tx_bytes;
170 unsigned long rx_dropped;
171 unsigned long tx_dropped;
172 };
173
174 struct myri10ge_slice_state {
175 struct myri10ge_tx_buf tx; /* transmit ring */
176 struct myri10ge_rx_buf rx_small;
177 struct myri10ge_rx_buf rx_big;
178 struct myri10ge_rx_done rx_done;
179 struct net_device *dev;
180 struct napi_struct napi;
181 struct myri10ge_priv *mgp;
182 struct myri10ge_slice_netstats stats;
183 __be32 __iomem *irq_claim;
184 struct mcp_irq_data *fw_stats;
185 dma_addr_t fw_stats_bus;
186 int watchdog_tx_done;
187 int watchdog_tx_req;
188 };
189
190 struct myri10ge_priv {
191 struct myri10ge_slice_state ss;
192 int tx_boundary; /* boundary transmits cannot cross */
193 int running; /* running? */
194 int csum_flag; /* rx_csums? */
195 int small_bytes;
196 int big_bytes;
197 int max_intr_slots;
198 struct net_device *dev;
199 struct net_device_stats stats;
200 spinlock_t stats_lock;
201 u8 __iomem *sram;
202 int sram_size;
203 unsigned long board_span;
204 unsigned long iomem_base;
205 __be32 __iomem *irq_deassert;
206 char *mac_addr_string;
207 struct mcp_cmd_response *cmd;
208 dma_addr_t cmd_bus;
209 struct pci_dev *pdev;
210 int msi_enabled;
211 u32 link_state;
212 unsigned int rdma_tags_available;
213 int intr_coal_delay;
214 __be32 __iomem *intr_coal_delay_ptr;
215 int mtrr;
216 int wc_enabled;
217 int down_cnt;
218 wait_queue_head_t down_wq;
219 struct work_struct watchdog_work;
220 struct timer_list watchdog_timer;
221 int watchdog_resets;
222 int watchdog_pause;
223 int pause;
224 char *fw_name;
225 char eeprom_strings[MYRI10GE_EEPROM_STRINGS_SIZE];
226 char *product_code_string;
227 char fw_version[128];
228 int fw_ver_major;
229 int fw_ver_minor;
230 int fw_ver_tiny;
231 int adopted_rx_filter_bug;
232 u8 mac_addr[6]; /* eeprom mac address */
233 unsigned long serial_number;
234 int vendor_specific_offset;
235 int fw_multicast_support;
236 unsigned long features;
237 u32 max_tso6;
238 u32 read_dma;
239 u32 write_dma;
240 u32 read_write_dma;
241 u32 link_changes;
242 u32 msg_enable;
243 };
244
245 static char *myri10ge_fw_unaligned = "myri10ge_ethp_z8e.dat";
246 static char *myri10ge_fw_aligned = "myri10ge_eth_z8e.dat";
247
248 static char *myri10ge_fw_name = NULL;
249 module_param(myri10ge_fw_name, charp, S_IRUGO | S_IWUSR);
250 MODULE_PARM_DESC(myri10ge_fw_name, "Firmware image name");
251
252 static int myri10ge_ecrc_enable = 1;
253 module_param(myri10ge_ecrc_enable, int, S_IRUGO);
254 MODULE_PARM_DESC(myri10ge_ecrc_enable, "Enable Extended CRC on PCI-E");
255
256 static int myri10ge_small_bytes = -1; /* -1 == auto */
257 module_param(myri10ge_small_bytes, int, S_IRUGO | S_IWUSR);
258 MODULE_PARM_DESC(myri10ge_small_bytes, "Threshold of small packets");
259
260 static int myri10ge_msi = 1; /* enable msi by default */
261 module_param(myri10ge_msi, int, S_IRUGO | S_IWUSR);
262 MODULE_PARM_DESC(myri10ge_msi, "Enable Message Signalled Interrupts");
263
264 static int myri10ge_intr_coal_delay = 75;
265 module_param(myri10ge_intr_coal_delay, int, S_IRUGO);
266 MODULE_PARM_DESC(myri10ge_intr_coal_delay, "Interrupt coalescing delay");
267
268 static int myri10ge_flow_control = 1;
269 module_param(myri10ge_flow_control, int, S_IRUGO);
270 MODULE_PARM_DESC(myri10ge_flow_control, "Pause parameter");
271
272 static int myri10ge_deassert_wait = 1;
273 module_param(myri10ge_deassert_wait, int, S_IRUGO | S_IWUSR);
274 MODULE_PARM_DESC(myri10ge_deassert_wait,
275 "Wait when deasserting legacy interrupts");
276
277 static int myri10ge_force_firmware = 0;
278 module_param(myri10ge_force_firmware, int, S_IRUGO);
279 MODULE_PARM_DESC(myri10ge_force_firmware,
280 "Force firmware to assume aligned completions");
281
282 static int myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
283 module_param(myri10ge_initial_mtu, int, S_IRUGO);
284 MODULE_PARM_DESC(myri10ge_initial_mtu, "Initial MTU");
285
286 static int myri10ge_napi_weight = 64;
287 module_param(myri10ge_napi_weight, int, S_IRUGO);
288 MODULE_PARM_DESC(myri10ge_napi_weight, "Set NAPI weight");
289
290 static int myri10ge_watchdog_timeout = 1;
291 module_param(myri10ge_watchdog_timeout, int, S_IRUGO);
292 MODULE_PARM_DESC(myri10ge_watchdog_timeout, "Set watchdog timeout");
293
294 static int myri10ge_max_irq_loops = 1048576;
295 module_param(myri10ge_max_irq_loops, int, S_IRUGO);
296 MODULE_PARM_DESC(myri10ge_max_irq_loops,
297 "Set stuck legacy IRQ detection threshold");
298
299 #define MYRI10GE_MSG_DEFAULT NETIF_MSG_LINK
300
301 static int myri10ge_debug = -1; /* defaults above */
302 module_param(myri10ge_debug, int, 0);
303 MODULE_PARM_DESC(myri10ge_debug, "Debug level (0=none,...,16=all)");
304
305 static int myri10ge_lro = 1;
306 module_param(myri10ge_lro, int, S_IRUGO);
307 MODULE_PARM_DESC(myri10ge_lro, "Enable large receive offload");
308
309 static int myri10ge_lro_max_pkts = MYRI10GE_LRO_MAX_PKTS;
310 module_param(myri10ge_lro_max_pkts, int, S_IRUGO);
311 MODULE_PARM_DESC(myri10ge_lro_max_pkts,
312 "Number of LRO packets to be aggregated");
313
314 static int myri10ge_fill_thresh = 256;
315 module_param(myri10ge_fill_thresh, int, S_IRUGO | S_IWUSR);
316 MODULE_PARM_DESC(myri10ge_fill_thresh, "Number of empty rx slots allowed");
317
318 static int myri10ge_reset_recover = 1;
319
320 static int myri10ge_wcfifo = 0;
321 module_param(myri10ge_wcfifo, int, S_IRUGO);
322 MODULE_PARM_DESC(myri10ge_wcfifo, "Enable WC Fifo when WC is enabled");
323
324 #define MYRI10GE_FW_OFFSET 1024*1024
325 #define MYRI10GE_HIGHPART_TO_U32(X) \
326 (sizeof (X) == 8) ? ((u32)((u64)(X) >> 32)) : (0)
327 #define MYRI10GE_LOWPART_TO_U32(X) ((u32)(X))
328
329 #define myri10ge_pio_copy(to,from,size) __iowrite64_copy(to,from,size/8)
330
331 static void myri10ge_set_multicast_list(struct net_device *dev);
332 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev);
333
334 static inline void put_be32(__be32 val, __be32 __iomem * p)
335 {
336 __raw_writel((__force __u32) val, (__force void __iomem *)p);
337 }
338
339 static int
340 myri10ge_send_cmd(struct myri10ge_priv *mgp, u32 cmd,
341 struct myri10ge_cmd *data, int atomic)
342 {
343 struct mcp_cmd *buf;
344 char buf_bytes[sizeof(*buf) + 8];
345 struct mcp_cmd_response *response = mgp->cmd;
346 char __iomem *cmd_addr = mgp->sram + MXGEFW_ETH_CMD;
347 u32 dma_low, dma_high, result, value;
348 int sleep_total = 0;
349
350 /* ensure buf is aligned to 8 bytes */
351 buf = (struct mcp_cmd *)ALIGN((unsigned long)buf_bytes, 8);
352
353 buf->data0 = htonl(data->data0);
354 buf->data1 = htonl(data->data1);
355 buf->data2 = htonl(data->data2);
356 buf->cmd = htonl(cmd);
357 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
358 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
359
360 buf->response_addr.low = htonl(dma_low);
361 buf->response_addr.high = htonl(dma_high);
362 response->result = htonl(MYRI10GE_NO_RESPONSE_RESULT);
363 mb();
364 myri10ge_pio_copy(cmd_addr, buf, sizeof(*buf));
365
366 /* wait up to 15ms. Longest command is the DMA benchmark,
367 * which is capped at 5ms, but runs from a timeout handler
368 * that runs every 7.8ms. So a 15ms timeout leaves us with
369 * a 2.2ms margin
370 */
371 if (atomic) {
372 /* if atomic is set, do not sleep,
373 * and try to get the completion quickly
374 * (1ms will be enough for those commands) */
375 for (sleep_total = 0;
376 sleep_total < 1000
377 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
378 sleep_total += 10) {
379 udelay(10);
380 mb();
381 }
382 } else {
383 /* use msleep for most command */
384 for (sleep_total = 0;
385 sleep_total < 15
386 && response->result == htonl(MYRI10GE_NO_RESPONSE_RESULT);
387 sleep_total++)
388 msleep(1);
389 }
390
391 result = ntohl(response->result);
392 value = ntohl(response->data);
393 if (result != MYRI10GE_NO_RESPONSE_RESULT) {
394 if (result == 0) {
395 data->data0 = value;
396 return 0;
397 } else if (result == MXGEFW_CMD_UNKNOWN) {
398 return -ENOSYS;
399 } else if (result == MXGEFW_CMD_ERROR_UNALIGNED) {
400 return -E2BIG;
401 } else {
402 dev_err(&mgp->pdev->dev,
403 "command %d failed, result = %d\n",
404 cmd, result);
405 return -ENXIO;
406 }
407 }
408
409 dev_err(&mgp->pdev->dev, "command %d timed out, result = %d\n",
410 cmd, result);
411 return -EAGAIN;
412 }
413
414 /*
415 * The eeprom strings on the lanaiX have the format
416 * SN=x\0
417 * MAC=x:x:x:x:x:x\0
418 * PT:ddd mmm xx xx:xx:xx xx\0
419 * PV:ddd mmm xx xx:xx:xx xx\0
420 */
421 static int myri10ge_read_mac_addr(struct myri10ge_priv *mgp)
422 {
423 char *ptr, *limit;
424 int i;
425
426 ptr = mgp->eeprom_strings;
427 limit = mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE;
428
429 while (*ptr != '\0' && ptr < limit) {
430 if (memcmp(ptr, "MAC=", 4) == 0) {
431 ptr += 4;
432 mgp->mac_addr_string = ptr;
433 for (i = 0; i < 6; i++) {
434 if ((ptr + 2) > limit)
435 goto abort;
436 mgp->mac_addr[i] =
437 simple_strtoul(ptr, &ptr, 16);
438 ptr += 1;
439 }
440 }
441 if (memcmp(ptr, "PC=", 3) == 0) {
442 ptr += 3;
443 mgp->product_code_string = ptr;
444 }
445 if (memcmp((const void *)ptr, "SN=", 3) == 0) {
446 ptr += 3;
447 mgp->serial_number = simple_strtoul(ptr, &ptr, 10);
448 }
449 while (ptr < limit && *ptr++) ;
450 }
451
452 return 0;
453
454 abort:
455 dev_err(&mgp->pdev->dev, "failed to parse eeprom_strings\n");
456 return -ENXIO;
457 }
458
459 /*
460 * Enable or disable periodic RDMAs from the host to make certain
461 * chipsets resend dropped PCIe messages
462 */
463
464 static void myri10ge_dummy_rdma(struct myri10ge_priv *mgp, int enable)
465 {
466 char __iomem *submit;
467 __be32 buf[16] __attribute__ ((__aligned__(8)));
468 u32 dma_low, dma_high;
469 int i;
470
471 /* clear confirmation addr */
472 mgp->cmd->data = 0;
473 mb();
474
475 /* send a rdma command to the PCIe engine, and wait for the
476 * response in the confirmation address. The firmware should
477 * write a -1 there to indicate it is alive and well
478 */
479 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
480 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
481
482 buf[0] = htonl(dma_high); /* confirm addr MSW */
483 buf[1] = htonl(dma_low); /* confirm addr LSW */
484 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
485 buf[3] = htonl(dma_high); /* dummy addr MSW */
486 buf[4] = htonl(dma_low); /* dummy addr LSW */
487 buf[5] = htonl(enable); /* enable? */
488
489 submit = mgp->sram + MXGEFW_BOOT_DUMMY_RDMA;
490
491 myri10ge_pio_copy(submit, &buf, sizeof(buf));
492 for (i = 0; mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 20; i++)
493 msleep(1);
494 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA)
495 dev_err(&mgp->pdev->dev, "dummy rdma %s failed\n",
496 (enable ? "enable" : "disable"));
497 }
498
499 static int
500 myri10ge_validate_firmware(struct myri10ge_priv *mgp,
501 struct mcp_gen_header *hdr)
502 {
503 struct device *dev = &mgp->pdev->dev;
504
505 /* check firmware type */
506 if (ntohl(hdr->mcp_type) != MCP_TYPE_ETH) {
507 dev_err(dev, "Bad firmware type: 0x%x\n", ntohl(hdr->mcp_type));
508 return -EINVAL;
509 }
510
511 /* save firmware version for ethtool */
512 strncpy(mgp->fw_version, hdr->version, sizeof(mgp->fw_version));
513
514 sscanf(mgp->fw_version, "%d.%d.%d", &mgp->fw_ver_major,
515 &mgp->fw_ver_minor, &mgp->fw_ver_tiny);
516
517 if (!(mgp->fw_ver_major == MXGEFW_VERSION_MAJOR
518 && mgp->fw_ver_minor == MXGEFW_VERSION_MINOR)) {
519 dev_err(dev, "Found firmware version %s\n", mgp->fw_version);
520 dev_err(dev, "Driver needs %d.%d\n", MXGEFW_VERSION_MAJOR,
521 MXGEFW_VERSION_MINOR);
522 return -EINVAL;
523 }
524 return 0;
525 }
526
527 static int myri10ge_load_hotplug_firmware(struct myri10ge_priv *mgp, u32 * size)
528 {
529 unsigned crc, reread_crc;
530 const struct firmware *fw;
531 struct device *dev = &mgp->pdev->dev;
532 struct mcp_gen_header *hdr;
533 size_t hdr_offset;
534 int status;
535 unsigned i;
536
537 if ((status = request_firmware(&fw, mgp->fw_name, dev)) < 0) {
538 dev_err(dev, "Unable to load %s firmware image via hotplug\n",
539 mgp->fw_name);
540 status = -EINVAL;
541 goto abort_with_nothing;
542 }
543
544 /* check size */
545
546 if (fw->size >= mgp->sram_size - MYRI10GE_FW_OFFSET ||
547 fw->size < MCP_HEADER_PTR_OFFSET + 4) {
548 dev_err(dev, "Firmware size invalid:%d\n", (int)fw->size);
549 status = -EINVAL;
550 goto abort_with_fw;
551 }
552
553 /* check id */
554 hdr_offset = ntohl(*(__be32 *) (fw->data + MCP_HEADER_PTR_OFFSET));
555 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > fw->size) {
556 dev_err(dev, "Bad firmware file\n");
557 status = -EINVAL;
558 goto abort_with_fw;
559 }
560 hdr = (void *)(fw->data + hdr_offset);
561
562 status = myri10ge_validate_firmware(mgp, hdr);
563 if (status != 0)
564 goto abort_with_fw;
565
566 crc = crc32(~0, fw->data, fw->size);
567 for (i = 0; i < fw->size; i += 256) {
568 myri10ge_pio_copy(mgp->sram + MYRI10GE_FW_OFFSET + i,
569 fw->data + i,
570 min(256U, (unsigned)(fw->size - i)));
571 mb();
572 readb(mgp->sram);
573 }
574 /* corruption checking is good for parity recovery and buggy chipset */
575 memcpy_fromio(fw->data, mgp->sram + MYRI10GE_FW_OFFSET, fw->size);
576 reread_crc = crc32(~0, fw->data, fw->size);
577 if (crc != reread_crc) {
578 dev_err(dev, "CRC failed(fw-len=%u), got 0x%x (expect 0x%x)\n",
579 (unsigned)fw->size, reread_crc, crc);
580 status = -EIO;
581 goto abort_with_fw;
582 }
583 *size = (u32) fw->size;
584
585 abort_with_fw:
586 release_firmware(fw);
587
588 abort_with_nothing:
589 return status;
590 }
591
592 static int myri10ge_adopt_running_firmware(struct myri10ge_priv *mgp)
593 {
594 struct mcp_gen_header *hdr;
595 struct device *dev = &mgp->pdev->dev;
596 const size_t bytes = sizeof(struct mcp_gen_header);
597 size_t hdr_offset;
598 int status;
599
600 /* find running firmware header */
601 hdr_offset = swab32(readl(mgp->sram + MCP_HEADER_PTR_OFFSET));
602
603 if ((hdr_offset & 3) || hdr_offset + sizeof(*hdr) > mgp->sram_size) {
604 dev_err(dev, "Running firmware has bad header offset (%d)\n",
605 (int)hdr_offset);
606 return -EIO;
607 }
608
609 /* copy header of running firmware from SRAM to host memory to
610 * validate firmware */
611 hdr = kmalloc(bytes, GFP_KERNEL);
612 if (hdr == NULL) {
613 dev_err(dev, "could not malloc firmware hdr\n");
614 return -ENOMEM;
615 }
616 memcpy_fromio(hdr, mgp->sram + hdr_offset, bytes);
617 status = myri10ge_validate_firmware(mgp, hdr);
618 kfree(hdr);
619
620 /* check to see if adopted firmware has bug where adopting
621 * it will cause broadcasts to be filtered unless the NIC
622 * is kept in ALLMULTI mode */
623 if (mgp->fw_ver_major == 1 && mgp->fw_ver_minor == 4 &&
624 mgp->fw_ver_tiny >= 4 && mgp->fw_ver_tiny <= 11) {
625 mgp->adopted_rx_filter_bug = 1;
626 dev_warn(dev, "Adopting fw %d.%d.%d: "
627 "working around rx filter bug\n",
628 mgp->fw_ver_major, mgp->fw_ver_minor,
629 mgp->fw_ver_tiny);
630 }
631 return status;
632 }
633
634 static int myri10ge_get_firmware_capabilities(struct myri10ge_priv *mgp)
635 {
636 struct myri10ge_cmd cmd;
637 int status;
638
639 /* probe for IPv6 TSO support */
640 mgp->features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_TSO;
641 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
642 &cmd, 0);
643 if (status == 0) {
644 mgp->max_tso6 = cmd.data0;
645 mgp->features |= NETIF_F_TSO6;
646 }
647
648 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
649 if (status != 0) {
650 dev_err(&mgp->pdev->dev,
651 "failed MXGEFW_CMD_GET_RX_RING_SIZE\n");
652 return -ENXIO;
653 }
654
655 mgp->max_intr_slots = 2 * (cmd.data0 / sizeof(struct mcp_dma_addr));
656
657 return 0;
658 }
659
660 static int myri10ge_load_firmware(struct myri10ge_priv *mgp)
661 {
662 char __iomem *submit;
663 __be32 buf[16] __attribute__ ((__aligned__(8)));
664 u32 dma_low, dma_high, size;
665 int status, i;
666
667 size = 0;
668 status = myri10ge_load_hotplug_firmware(mgp, &size);
669 if (status) {
670 dev_warn(&mgp->pdev->dev, "hotplug firmware loading failed\n");
671
672 /* Do not attempt to adopt firmware if there
673 * was a bad crc */
674 if (status == -EIO)
675 return status;
676
677 status = myri10ge_adopt_running_firmware(mgp);
678 if (status != 0) {
679 dev_err(&mgp->pdev->dev,
680 "failed to adopt running firmware\n");
681 return status;
682 }
683 dev_info(&mgp->pdev->dev,
684 "Successfully adopted running firmware\n");
685 if (mgp->tx_boundary == 4096) {
686 dev_warn(&mgp->pdev->dev,
687 "Using firmware currently running on NIC"
688 ". For optimal\n");
689 dev_warn(&mgp->pdev->dev,
690 "performance consider loading optimized "
691 "firmware\n");
692 dev_warn(&mgp->pdev->dev, "via hotplug\n");
693 }
694
695 mgp->fw_name = "adopted";
696 mgp->tx_boundary = 2048;
697 myri10ge_dummy_rdma(mgp, 1);
698 status = myri10ge_get_firmware_capabilities(mgp);
699 return status;
700 }
701
702 /* clear confirmation addr */
703 mgp->cmd->data = 0;
704 mb();
705
706 /* send a reload command to the bootstrap MCP, and wait for the
707 * response in the confirmation address. The firmware should
708 * write a -1 there to indicate it is alive and well
709 */
710 dma_low = MYRI10GE_LOWPART_TO_U32(mgp->cmd_bus);
711 dma_high = MYRI10GE_HIGHPART_TO_U32(mgp->cmd_bus);
712
713 buf[0] = htonl(dma_high); /* confirm addr MSW */
714 buf[1] = htonl(dma_low); /* confirm addr LSW */
715 buf[2] = MYRI10GE_NO_CONFIRM_DATA; /* confirm data */
716
717 /* FIX: All newest firmware should un-protect the bottom of
718 * the sram before handoff. However, the very first interfaces
719 * do not. Therefore the handoff copy must skip the first 8 bytes
720 */
721 buf[3] = htonl(MYRI10GE_FW_OFFSET + 8); /* where the code starts */
722 buf[4] = htonl(size - 8); /* length of code */
723 buf[5] = htonl(8); /* where to copy to */
724 buf[6] = htonl(0); /* where to jump to */
725
726 submit = mgp->sram + MXGEFW_BOOT_HANDOFF;
727
728 myri10ge_pio_copy(submit, &buf, sizeof(buf));
729 mb();
730 msleep(1);
731 mb();
732 i = 0;
733 while (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA && i < 9) {
734 msleep(1 << i);
735 i++;
736 }
737 if (mgp->cmd->data != MYRI10GE_NO_CONFIRM_DATA) {
738 dev_err(&mgp->pdev->dev, "handoff failed\n");
739 return -ENXIO;
740 }
741 myri10ge_dummy_rdma(mgp, 1);
742 status = myri10ge_get_firmware_capabilities(mgp);
743
744 return status;
745 }
746
747 static int myri10ge_update_mac_address(struct myri10ge_priv *mgp, u8 * addr)
748 {
749 struct myri10ge_cmd cmd;
750 int status;
751
752 cmd.data0 = ((addr[0] << 24) | (addr[1] << 16)
753 | (addr[2] << 8) | addr[3]);
754
755 cmd.data1 = ((addr[4] << 8) | (addr[5]));
756
757 status = myri10ge_send_cmd(mgp, MXGEFW_SET_MAC_ADDRESS, &cmd, 0);
758 return status;
759 }
760
761 static int myri10ge_change_pause(struct myri10ge_priv *mgp, int pause)
762 {
763 struct myri10ge_cmd cmd;
764 int status, ctl;
765
766 ctl = pause ? MXGEFW_ENABLE_FLOW_CONTROL : MXGEFW_DISABLE_FLOW_CONTROL;
767 status = myri10ge_send_cmd(mgp, ctl, &cmd, 0);
768
769 if (status) {
770 printk(KERN_ERR
771 "myri10ge: %s: Failed to set flow control mode\n",
772 mgp->dev->name);
773 return status;
774 }
775 mgp->pause = pause;
776 return 0;
777 }
778
779 static void
780 myri10ge_change_promisc(struct myri10ge_priv *mgp, int promisc, int atomic)
781 {
782 struct myri10ge_cmd cmd;
783 int status, ctl;
784
785 ctl = promisc ? MXGEFW_ENABLE_PROMISC : MXGEFW_DISABLE_PROMISC;
786 status = myri10ge_send_cmd(mgp, ctl, &cmd, atomic);
787 if (status)
788 printk(KERN_ERR "myri10ge: %s: Failed to set promisc mode\n",
789 mgp->dev->name);
790 }
791
792 static int myri10ge_dma_test(struct myri10ge_priv *mgp, int test_type)
793 {
794 struct myri10ge_cmd cmd;
795 int status;
796 u32 len;
797 struct page *dmatest_page;
798 dma_addr_t dmatest_bus;
799 char *test = " ";
800
801 dmatest_page = alloc_page(GFP_KERNEL);
802 if (!dmatest_page)
803 return -ENOMEM;
804 dmatest_bus = pci_map_page(mgp->pdev, dmatest_page, 0, PAGE_SIZE,
805 DMA_BIDIRECTIONAL);
806
807 /* Run a small DMA test.
808 * The magic multipliers to the length tell the firmware
809 * to do DMA read, write, or read+write tests. The
810 * results are returned in cmd.data0. The upper 16
811 * bits or the return is the number of transfers completed.
812 * The lower 16 bits is the time in 0.5us ticks that the
813 * transfers took to complete.
814 */
815
816 len = mgp->tx_boundary;
817
818 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
819 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
820 cmd.data2 = len * 0x10000;
821 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
822 if (status != 0) {
823 test = "read";
824 goto abort;
825 }
826 mgp->read_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
827 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
828 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
829 cmd.data2 = len * 0x1;
830 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
831 if (status != 0) {
832 test = "write";
833 goto abort;
834 }
835 mgp->write_dma = ((cmd.data0 >> 16) * len * 2) / (cmd.data0 & 0xffff);
836
837 cmd.data0 = MYRI10GE_LOWPART_TO_U32(dmatest_bus);
838 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(dmatest_bus);
839 cmd.data2 = len * 0x10001;
840 status = myri10ge_send_cmd(mgp, test_type, &cmd, 0);
841 if (status != 0) {
842 test = "read/write";
843 goto abort;
844 }
845 mgp->read_write_dma = ((cmd.data0 >> 16) * len * 2 * 2) /
846 (cmd.data0 & 0xffff);
847
848 abort:
849 pci_unmap_page(mgp->pdev, dmatest_bus, PAGE_SIZE, DMA_BIDIRECTIONAL);
850 put_page(dmatest_page);
851
852 if (status != 0 && test_type != MXGEFW_CMD_UNALIGNED_TEST)
853 dev_warn(&mgp->pdev->dev, "DMA %s benchmark failed: %d\n",
854 test, status);
855
856 return status;
857 }
858
859 static int myri10ge_reset(struct myri10ge_priv *mgp)
860 {
861 struct myri10ge_cmd cmd;
862 int status;
863 size_t bytes;
864
865 /* try to send a reset command to the card to see if it
866 * is alive */
867 memset(&cmd, 0, sizeof(cmd));
868 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_RESET, &cmd, 0);
869 if (status != 0) {
870 dev_err(&mgp->pdev->dev, "failed reset\n");
871 return -ENXIO;
872 }
873
874 (void)myri10ge_dma_test(mgp, MXGEFW_DMA_TEST);
875
876 /* Now exchange information about interrupts */
877
878 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
879 memset(mgp->ss.rx_done.entry, 0, bytes);
880 cmd.data0 = (u32) bytes;
881 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_SIZE, &cmd, 0);
882 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.rx_done.bus);
883 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.rx_done.bus);
884 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_INTRQ_DMA, &cmd, 0);
885
886 status |=
887 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_ACK_OFFSET, &cmd, 0);
888 mgp->ss.irq_claim = (__iomem __be32 *) (mgp->sram + cmd.data0);
889 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_IRQ_DEASSERT_OFFSET,
890 &cmd, 0);
891 mgp->irq_deassert = (__iomem __be32 *) (mgp->sram + cmd.data0);
892
893 status |= myri10ge_send_cmd
894 (mgp, MXGEFW_CMD_GET_INTR_COAL_DELAY_OFFSET, &cmd, 0);
895 mgp->intr_coal_delay_ptr = (__iomem __be32 *) (mgp->sram + cmd.data0);
896 if (status != 0) {
897 dev_err(&mgp->pdev->dev, "failed set interrupt parameters\n");
898 return status;
899 }
900 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
901
902 memset(mgp->ss.rx_done.entry, 0, bytes);
903
904 /* reset mcp/driver shared state back to 0 */
905 mgp->ss.tx.req = 0;
906 mgp->ss.tx.done = 0;
907 mgp->ss.tx.pkt_start = 0;
908 mgp->ss.tx.pkt_done = 0;
909 mgp->ss.rx_big.cnt = 0;
910 mgp->ss.rx_small.cnt = 0;
911 mgp->ss.rx_done.idx = 0;
912 mgp->ss.rx_done.cnt = 0;
913 mgp->link_changes = 0;
914 status = myri10ge_update_mac_address(mgp, mgp->dev->dev_addr);
915 myri10ge_change_pause(mgp, mgp->pause);
916 myri10ge_set_multicast_list(mgp->dev);
917 return status;
918 }
919
920 static inline void
921 myri10ge_submit_8rx(struct mcp_kreq_ether_recv __iomem * dst,
922 struct mcp_kreq_ether_recv *src)
923 {
924 __be32 low;
925
926 low = src->addr_low;
927 src->addr_low = htonl(DMA_32BIT_MASK);
928 myri10ge_pio_copy(dst, src, 4 * sizeof(*src));
929 mb();
930 myri10ge_pio_copy(dst + 4, src + 4, 4 * sizeof(*src));
931 mb();
932 src->addr_low = low;
933 put_be32(low, &dst->addr_low);
934 mb();
935 }
936
937 static inline void myri10ge_vlan_ip_csum(struct sk_buff *skb, __wsum hw_csum)
938 {
939 struct vlan_hdr *vh = (struct vlan_hdr *)(skb->data);
940
941 if ((skb->protocol == htons(ETH_P_8021Q)) &&
942 (vh->h_vlan_encapsulated_proto == htons(ETH_P_IP) ||
943 vh->h_vlan_encapsulated_proto == htons(ETH_P_IPV6))) {
944 skb->csum = hw_csum;
945 skb->ip_summed = CHECKSUM_COMPLETE;
946 }
947 }
948
949 static inline void
950 myri10ge_rx_skb_build(struct sk_buff *skb, u8 * va,
951 struct skb_frag_struct *rx_frags, int len, int hlen)
952 {
953 struct skb_frag_struct *skb_frags;
954
955 skb->len = skb->data_len = len;
956 skb->truesize = len + sizeof(struct sk_buff);
957 /* attach the page(s) */
958
959 skb_frags = skb_shinfo(skb)->frags;
960 while (len > 0) {
961 memcpy(skb_frags, rx_frags, sizeof(*skb_frags));
962 len -= rx_frags->size;
963 skb_frags++;
964 rx_frags++;
965 skb_shinfo(skb)->nr_frags++;
966 }
967
968 /* pskb_may_pull is not available in irq context, but
969 * skb_pull() (for ether_pad and eth_type_trans()) requires
970 * the beginning of the packet in skb_headlen(), move it
971 * manually */
972 skb_copy_to_linear_data(skb, va, hlen);
973 skb_shinfo(skb)->frags[0].page_offset += hlen;
974 skb_shinfo(skb)->frags[0].size -= hlen;
975 skb->data_len -= hlen;
976 skb->tail += hlen;
977 skb_pull(skb, MXGEFW_PAD);
978 }
979
980 static void
981 myri10ge_alloc_rx_pages(struct myri10ge_priv *mgp, struct myri10ge_rx_buf *rx,
982 int bytes, int watchdog)
983 {
984 struct page *page;
985 int idx;
986
987 if (unlikely(rx->watchdog_needed && !watchdog))
988 return;
989
990 /* try to refill entire ring */
991 while (rx->fill_cnt != (rx->cnt + rx->mask + 1)) {
992 idx = rx->fill_cnt & rx->mask;
993 if (rx->page_offset + bytes <= MYRI10GE_ALLOC_SIZE) {
994 /* we can use part of previous page */
995 get_page(rx->page);
996 } else {
997 /* we need a new page */
998 page =
999 alloc_pages(GFP_ATOMIC | __GFP_COMP,
1000 MYRI10GE_ALLOC_ORDER);
1001 if (unlikely(page == NULL)) {
1002 if (rx->fill_cnt - rx->cnt < 16)
1003 rx->watchdog_needed = 1;
1004 return;
1005 }
1006 rx->page = page;
1007 rx->page_offset = 0;
1008 rx->bus = pci_map_page(mgp->pdev, page, 0,
1009 MYRI10GE_ALLOC_SIZE,
1010 PCI_DMA_FROMDEVICE);
1011 }
1012 rx->info[idx].page = rx->page;
1013 rx->info[idx].page_offset = rx->page_offset;
1014 /* note that this is the address of the start of the
1015 * page */
1016 pci_unmap_addr_set(&rx->info[idx], bus, rx->bus);
1017 rx->shadow[idx].addr_low =
1018 htonl(MYRI10GE_LOWPART_TO_U32(rx->bus) + rx->page_offset);
1019 rx->shadow[idx].addr_high =
1020 htonl(MYRI10GE_HIGHPART_TO_U32(rx->bus));
1021
1022 /* start next packet on a cacheline boundary */
1023 rx->page_offset += SKB_DATA_ALIGN(bytes);
1024
1025 #if MYRI10GE_ALLOC_SIZE > 4096
1026 /* don't cross a 4KB boundary */
1027 if ((rx->page_offset >> 12) !=
1028 ((rx->page_offset + bytes - 1) >> 12))
1029 rx->page_offset = (rx->page_offset + 4096) & ~4095;
1030 #endif
1031 rx->fill_cnt++;
1032
1033 /* copy 8 descriptors to the firmware at a time */
1034 if ((idx & 7) == 7) {
1035 if (rx->wc_fifo == NULL)
1036 myri10ge_submit_8rx(&rx->lanai[idx - 7],
1037 &rx->shadow[idx - 7]);
1038 else {
1039 mb();
1040 myri10ge_pio_copy(rx->wc_fifo,
1041 &rx->shadow[idx - 7], 64);
1042 }
1043 }
1044 }
1045 }
1046
1047 static inline void
1048 myri10ge_unmap_rx_page(struct pci_dev *pdev,
1049 struct myri10ge_rx_buffer_state *info, int bytes)
1050 {
1051 /* unmap the recvd page if we're the only or last user of it */
1052 if (bytes >= MYRI10GE_ALLOC_SIZE / 2 ||
1053 (info->page_offset + 2 * bytes) > MYRI10GE_ALLOC_SIZE) {
1054 pci_unmap_page(pdev, (pci_unmap_addr(info, bus)
1055 & ~(MYRI10GE_ALLOC_SIZE - 1)),
1056 MYRI10GE_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
1057 }
1058 }
1059
1060 #define MYRI10GE_HLEN 64 /* The number of bytes to copy from a
1061 * page into an skb */
1062
1063 static inline int
1064 myri10ge_rx_done(struct myri10ge_slice_state *ss, struct myri10ge_rx_buf *rx,
1065 int bytes, int len, __wsum csum)
1066 {
1067 struct myri10ge_priv *mgp = ss->mgp;
1068 struct sk_buff *skb;
1069 struct skb_frag_struct rx_frags[MYRI10GE_MAX_FRAGS_PER_FRAME];
1070 int i, idx, hlen, remainder;
1071 struct pci_dev *pdev = mgp->pdev;
1072 struct net_device *dev = mgp->dev;
1073 u8 *va;
1074
1075 len += MXGEFW_PAD;
1076 idx = rx->cnt & rx->mask;
1077 va = page_address(rx->info[idx].page) + rx->info[idx].page_offset;
1078 prefetch(va);
1079 /* Fill skb_frag_struct(s) with data from our receive */
1080 for (i = 0, remainder = len; remainder > 0; i++) {
1081 myri10ge_unmap_rx_page(pdev, &rx->info[idx], bytes);
1082 rx_frags[i].page = rx->info[idx].page;
1083 rx_frags[i].page_offset = rx->info[idx].page_offset;
1084 if (remainder < MYRI10GE_ALLOC_SIZE)
1085 rx_frags[i].size = remainder;
1086 else
1087 rx_frags[i].size = MYRI10GE_ALLOC_SIZE;
1088 rx->cnt++;
1089 idx = rx->cnt & rx->mask;
1090 remainder -= MYRI10GE_ALLOC_SIZE;
1091 }
1092
1093 if (mgp->csum_flag && myri10ge_lro) {
1094 rx_frags[0].page_offset += MXGEFW_PAD;
1095 rx_frags[0].size -= MXGEFW_PAD;
1096 len -= MXGEFW_PAD;
1097 lro_receive_frags(&ss->rx_done.lro_mgr, rx_frags,
1098 len, len,
1099 /* opaque, will come back in get_frag_header */
1100 (void *)(__force unsigned long)csum, csum);
1101 return 1;
1102 }
1103
1104 hlen = MYRI10GE_HLEN > len ? len : MYRI10GE_HLEN;
1105
1106 /* allocate an skb to attach the page(s) to. This is done
1107 * after trying LRO, so as to avoid skb allocation overheads */
1108
1109 skb = netdev_alloc_skb(dev, MYRI10GE_HLEN + 16);
1110 if (unlikely(skb == NULL)) {
1111 mgp->stats.rx_dropped++;
1112 do {
1113 i--;
1114 put_page(rx_frags[i].page);
1115 } while (i != 0);
1116 return 0;
1117 }
1118
1119 /* Attach the pages to the skb, and trim off any padding */
1120 myri10ge_rx_skb_build(skb, va, rx_frags, len, hlen);
1121 if (skb_shinfo(skb)->frags[0].size <= 0) {
1122 put_page(skb_shinfo(skb)->frags[0].page);
1123 skb_shinfo(skb)->nr_frags = 0;
1124 }
1125 skb->protocol = eth_type_trans(skb, dev);
1126
1127 if (mgp->csum_flag) {
1128 if ((skb->protocol == htons(ETH_P_IP)) ||
1129 (skb->protocol == htons(ETH_P_IPV6))) {
1130 skb->csum = csum;
1131 skb->ip_summed = CHECKSUM_COMPLETE;
1132 } else
1133 myri10ge_vlan_ip_csum(skb, csum);
1134 }
1135 netif_receive_skb(skb);
1136 dev->last_rx = jiffies;
1137 return 1;
1138 }
1139
1140 static inline void
1141 myri10ge_tx_done(struct myri10ge_slice_state *ss, int mcp_index)
1142 {
1143 struct pci_dev *pdev = ss->mgp->pdev;
1144 struct myri10ge_tx_buf *tx = &ss->tx;
1145 struct sk_buff *skb;
1146 int idx, len;
1147
1148 while (tx->pkt_done != mcp_index) {
1149 idx = tx->done & tx->mask;
1150 skb = tx->info[idx].skb;
1151
1152 /* Mark as free */
1153 tx->info[idx].skb = NULL;
1154 if (tx->info[idx].last) {
1155 tx->pkt_done++;
1156 tx->info[idx].last = 0;
1157 }
1158 tx->done++;
1159 len = pci_unmap_len(&tx->info[idx], len);
1160 pci_unmap_len_set(&tx->info[idx], len, 0);
1161 if (skb) {
1162 ss->stats.tx_bytes += skb->len;
1163 ss->stats.tx_packets++;
1164 dev_kfree_skb_irq(skb);
1165 if (len)
1166 pci_unmap_single(pdev,
1167 pci_unmap_addr(&tx->info[idx],
1168 bus), len,
1169 PCI_DMA_TODEVICE);
1170 } else {
1171 if (len)
1172 pci_unmap_page(pdev,
1173 pci_unmap_addr(&tx->info[idx],
1174 bus), len,
1175 PCI_DMA_TODEVICE);
1176 }
1177 }
1178 /* start the queue if we've stopped it */
1179 if (netif_queue_stopped(ss->dev)
1180 && tx->req - tx->done < (tx->mask >> 1)) {
1181 tx->wake_queue++;
1182 netif_wake_queue(ss->dev);
1183 }
1184 }
1185
1186 static inline int
1187 myri10ge_clean_rx_done(struct myri10ge_slice_state *ss, int budget)
1188 {
1189 struct myri10ge_rx_done *rx_done = &ss->rx_done;
1190 struct myri10ge_priv *mgp = ss->mgp;
1191 unsigned long rx_bytes = 0;
1192 unsigned long rx_packets = 0;
1193 unsigned long rx_ok;
1194
1195 int idx = rx_done->idx;
1196 int cnt = rx_done->cnt;
1197 int work_done = 0;
1198 u16 length;
1199 __wsum checksum;
1200
1201 while (rx_done->entry[idx].length != 0 && work_done < budget) {
1202 length = ntohs(rx_done->entry[idx].length);
1203 rx_done->entry[idx].length = 0;
1204 checksum = csum_unfold(rx_done->entry[idx].checksum);
1205 if (length <= mgp->small_bytes)
1206 rx_ok = myri10ge_rx_done(ss, &ss->rx_small,
1207 mgp->small_bytes,
1208 length, checksum);
1209 else
1210 rx_ok = myri10ge_rx_done(ss, &ss->rx_big,
1211 mgp->big_bytes,
1212 length, checksum);
1213 rx_packets += rx_ok;
1214 rx_bytes += rx_ok * (unsigned long)length;
1215 cnt++;
1216 idx = cnt & (mgp->max_intr_slots - 1);
1217 work_done++;
1218 }
1219 rx_done->idx = idx;
1220 rx_done->cnt = cnt;
1221 ss->stats.rx_packets += rx_packets;
1222 ss->stats.rx_bytes += rx_bytes;
1223
1224 if (myri10ge_lro)
1225 lro_flush_all(&rx_done->lro_mgr);
1226
1227 /* restock receive rings if needed */
1228 if (ss->rx_small.fill_cnt - ss->rx_small.cnt < myri10ge_fill_thresh)
1229 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1230 mgp->small_bytes + MXGEFW_PAD, 0);
1231 if (ss->rx_big.fill_cnt - ss->rx_big.cnt < myri10ge_fill_thresh)
1232 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1233
1234 return work_done;
1235 }
1236
1237 static inline void myri10ge_check_statblock(struct myri10ge_priv *mgp)
1238 {
1239 struct mcp_irq_data *stats = mgp->ss.fw_stats;
1240
1241 if (unlikely(stats->stats_updated)) {
1242 unsigned link_up = ntohl(stats->link_up);
1243 if (mgp->link_state != link_up) {
1244 mgp->link_state = link_up;
1245
1246 if (mgp->link_state == MXGEFW_LINK_UP) {
1247 if (netif_msg_link(mgp))
1248 printk(KERN_INFO
1249 "myri10ge: %s: link up\n",
1250 mgp->dev->name);
1251 netif_carrier_on(mgp->dev);
1252 mgp->link_changes++;
1253 } else {
1254 if (netif_msg_link(mgp))
1255 printk(KERN_INFO
1256 "myri10ge: %s: link %s\n",
1257 mgp->dev->name,
1258 (link_up == MXGEFW_LINK_MYRINET ?
1259 "mismatch (Myrinet detected)" :
1260 "down"));
1261 netif_carrier_off(mgp->dev);
1262 mgp->link_changes++;
1263 }
1264 }
1265 if (mgp->rdma_tags_available !=
1266 ntohl(stats->rdma_tags_available)) {
1267 mgp->rdma_tags_available =
1268 ntohl(stats->rdma_tags_available);
1269 printk(KERN_WARNING "myri10ge: %s: RDMA timed out! "
1270 "%d tags left\n", mgp->dev->name,
1271 mgp->rdma_tags_available);
1272 }
1273 mgp->down_cnt += stats->link_down;
1274 if (stats->link_down)
1275 wake_up(&mgp->down_wq);
1276 }
1277 }
1278
1279 static int myri10ge_poll(struct napi_struct *napi, int budget)
1280 {
1281 struct myri10ge_slice_state *ss =
1282 container_of(napi, struct myri10ge_slice_state, napi);
1283 struct net_device *netdev = ss->mgp->dev;
1284 int work_done;
1285
1286 /* process as many rx events as NAPI will allow */
1287 work_done = myri10ge_clean_rx_done(ss, budget);
1288
1289 if (work_done < budget) {
1290 netif_rx_complete(netdev, napi);
1291 put_be32(htonl(3), ss->irq_claim);
1292 }
1293 return work_done;
1294 }
1295
1296 static irqreturn_t myri10ge_intr(int irq, void *arg)
1297 {
1298 struct myri10ge_slice_state *ss = arg;
1299 struct myri10ge_priv *mgp = ss->mgp;
1300 struct mcp_irq_data *stats = ss->fw_stats;
1301 struct myri10ge_tx_buf *tx = &ss->tx;
1302 u32 send_done_count;
1303 int i;
1304
1305 /* make sure it is our IRQ, and that the DMA has finished */
1306 if (unlikely(!stats->valid))
1307 return (IRQ_NONE);
1308
1309 /* low bit indicates receives are present, so schedule
1310 * napi poll handler */
1311 if (stats->valid & 1)
1312 netif_rx_schedule(ss->dev, &ss->napi);
1313
1314 if (!mgp->msi_enabled) {
1315 put_be32(0, mgp->irq_deassert);
1316 if (!myri10ge_deassert_wait)
1317 stats->valid = 0;
1318 mb();
1319 } else
1320 stats->valid = 0;
1321
1322 /* Wait for IRQ line to go low, if using INTx */
1323 i = 0;
1324 while (1) {
1325 i++;
1326 /* check for transmit completes and receives */
1327 send_done_count = ntohl(stats->send_done_count);
1328 if (send_done_count != tx->pkt_done)
1329 myri10ge_tx_done(ss, (int)send_done_count);
1330 if (unlikely(i > myri10ge_max_irq_loops)) {
1331 printk(KERN_WARNING "myri10ge: %s: irq stuck?\n",
1332 mgp->dev->name);
1333 stats->valid = 0;
1334 schedule_work(&mgp->watchdog_work);
1335 }
1336 if (likely(stats->valid == 0))
1337 break;
1338 cpu_relax();
1339 barrier();
1340 }
1341
1342 myri10ge_check_statblock(mgp);
1343
1344 put_be32(htonl(3), ss->irq_claim + 1);
1345 return (IRQ_HANDLED);
1346 }
1347
1348 static int
1349 myri10ge_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
1350 {
1351 struct myri10ge_priv *mgp = netdev_priv(netdev);
1352 char *ptr;
1353 int i;
1354
1355 cmd->autoneg = AUTONEG_DISABLE;
1356 cmd->speed = SPEED_10000;
1357 cmd->duplex = DUPLEX_FULL;
1358
1359 /*
1360 * parse the product code to deterimine the interface type
1361 * (CX4, XFP, Quad Ribbon Fiber) by looking at the character
1362 * after the 3rd dash in the driver's cached copy of the
1363 * EEPROM's product code string.
1364 */
1365 ptr = mgp->product_code_string;
1366 if (ptr == NULL) {
1367 printk(KERN_ERR "myri10ge: %s: Missing product code\n",
1368 netdev->name);
1369 return 0;
1370 }
1371 for (i = 0; i < 3; i++, ptr++) {
1372 ptr = strchr(ptr, '-');
1373 if (ptr == NULL) {
1374 printk(KERN_ERR "myri10ge: %s: Invalid product "
1375 "code %s\n", netdev->name,
1376 mgp->product_code_string);
1377 return 0;
1378 }
1379 }
1380 if (*ptr == 'R' || *ptr == 'Q') {
1381 /* We've found either an XFP or quad ribbon fiber */
1382 cmd->port = PORT_FIBRE;
1383 }
1384 return 0;
1385 }
1386
1387 static void
1388 myri10ge_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info)
1389 {
1390 struct myri10ge_priv *mgp = netdev_priv(netdev);
1391
1392 strlcpy(info->driver, "myri10ge", sizeof(info->driver));
1393 strlcpy(info->version, MYRI10GE_VERSION_STR, sizeof(info->version));
1394 strlcpy(info->fw_version, mgp->fw_version, sizeof(info->fw_version));
1395 strlcpy(info->bus_info, pci_name(mgp->pdev), sizeof(info->bus_info));
1396 }
1397
1398 static int
1399 myri10ge_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1400 {
1401 struct myri10ge_priv *mgp = netdev_priv(netdev);
1402
1403 coal->rx_coalesce_usecs = mgp->intr_coal_delay;
1404 return 0;
1405 }
1406
1407 static int
1408 myri10ge_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coal)
1409 {
1410 struct myri10ge_priv *mgp = netdev_priv(netdev);
1411
1412 mgp->intr_coal_delay = coal->rx_coalesce_usecs;
1413 put_be32(htonl(mgp->intr_coal_delay), mgp->intr_coal_delay_ptr);
1414 return 0;
1415 }
1416
1417 static void
1418 myri10ge_get_pauseparam(struct net_device *netdev,
1419 struct ethtool_pauseparam *pause)
1420 {
1421 struct myri10ge_priv *mgp = netdev_priv(netdev);
1422
1423 pause->autoneg = 0;
1424 pause->rx_pause = mgp->pause;
1425 pause->tx_pause = mgp->pause;
1426 }
1427
1428 static int
1429 myri10ge_set_pauseparam(struct net_device *netdev,
1430 struct ethtool_pauseparam *pause)
1431 {
1432 struct myri10ge_priv *mgp = netdev_priv(netdev);
1433
1434 if (pause->tx_pause != mgp->pause)
1435 return myri10ge_change_pause(mgp, pause->tx_pause);
1436 if (pause->rx_pause != mgp->pause)
1437 return myri10ge_change_pause(mgp, pause->tx_pause);
1438 if (pause->autoneg != 0)
1439 return -EINVAL;
1440 return 0;
1441 }
1442
1443 static void
1444 myri10ge_get_ringparam(struct net_device *netdev,
1445 struct ethtool_ringparam *ring)
1446 {
1447 struct myri10ge_priv *mgp = netdev_priv(netdev);
1448
1449 ring->rx_mini_max_pending = mgp->ss.rx_small.mask + 1;
1450 ring->rx_max_pending = mgp->ss.rx_big.mask + 1;
1451 ring->rx_jumbo_max_pending = 0;
1452 ring->tx_max_pending = mgp->ss.rx_small.mask + 1;
1453 ring->rx_mini_pending = ring->rx_mini_max_pending;
1454 ring->rx_pending = ring->rx_max_pending;
1455 ring->rx_jumbo_pending = ring->rx_jumbo_max_pending;
1456 ring->tx_pending = ring->tx_max_pending;
1457 }
1458
1459 static u32 myri10ge_get_rx_csum(struct net_device *netdev)
1460 {
1461 struct myri10ge_priv *mgp = netdev_priv(netdev);
1462
1463 if (mgp->csum_flag)
1464 return 1;
1465 else
1466 return 0;
1467 }
1468
1469 static int myri10ge_set_rx_csum(struct net_device *netdev, u32 csum_enabled)
1470 {
1471 struct myri10ge_priv *mgp = netdev_priv(netdev);
1472
1473 if (csum_enabled)
1474 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
1475 else
1476 mgp->csum_flag = 0;
1477 return 0;
1478 }
1479
1480 static int myri10ge_set_tso(struct net_device *netdev, u32 tso_enabled)
1481 {
1482 struct myri10ge_priv *mgp = netdev_priv(netdev);
1483 unsigned long flags = mgp->features & (NETIF_F_TSO6 | NETIF_F_TSO);
1484
1485 if (tso_enabled)
1486 netdev->features |= flags;
1487 else
1488 netdev->features &= ~flags;
1489 return 0;
1490 }
1491
1492 static const char myri10ge_gstrings_main_stats[][ETH_GSTRING_LEN] = {
1493 "rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
1494 "tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
1495 "rx_length_errors", "rx_over_errors", "rx_crc_errors",
1496 "rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
1497 "tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
1498 "tx_heartbeat_errors", "tx_window_errors",
1499 /* device-specific stats */
1500 "tx_boundary", "WC", "irq", "MSI",
1501 "read_dma_bw_MBs", "write_dma_bw_MBs", "read_write_dma_bw_MBs",
1502 "serial_number", "watchdog_resets",
1503 "link_changes", "link_up", "dropped_link_overflow",
1504 "dropped_link_error_or_filtered",
1505 "dropped_pause", "dropped_bad_phy", "dropped_bad_crc32",
1506 "dropped_unicast_filtered", "dropped_multicast_filtered",
1507 "dropped_runt", "dropped_overrun", "dropped_no_small_buffer",
1508 "dropped_no_big_buffer"
1509 };
1510
1511 static const char myri10ge_gstrings_slice_stats[][ETH_GSTRING_LEN] = {
1512 "----------- slice ---------",
1513 "tx_pkt_start", "tx_pkt_done", "tx_req", "tx_done",
1514 "rx_small_cnt", "rx_big_cnt",
1515 "wake_queue", "stop_queue", "tx_linearized", "LRO aggregated",
1516 "LRO flushed",
1517 "LRO avg aggr", "LRO no_desc"
1518 };
1519
1520 #define MYRI10GE_NET_STATS_LEN 21
1521 #define MYRI10GE_MAIN_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_main_stats)
1522 #define MYRI10GE_SLICE_STATS_LEN ARRAY_SIZE(myri10ge_gstrings_slice_stats)
1523
1524 static void
1525 myri10ge_get_strings(struct net_device *netdev, u32 stringset, u8 * data)
1526 {
1527 switch (stringset) {
1528 case ETH_SS_STATS:
1529 memcpy(data, *myri10ge_gstrings_main_stats,
1530 sizeof(myri10ge_gstrings_main_stats));
1531 data += sizeof(myri10ge_gstrings_main_stats);
1532 memcpy(data, *myri10ge_gstrings_slice_stats,
1533 sizeof(myri10ge_gstrings_slice_stats));
1534 data += sizeof(myri10ge_gstrings_slice_stats);
1535 break;
1536 }
1537 }
1538
1539 static int myri10ge_get_sset_count(struct net_device *netdev, int sset)
1540 {
1541 switch (sset) {
1542 case ETH_SS_STATS:
1543 return MYRI10GE_MAIN_STATS_LEN + MYRI10GE_SLICE_STATS_LEN;
1544 default:
1545 return -EOPNOTSUPP;
1546 }
1547 }
1548
1549 static void
1550 myri10ge_get_ethtool_stats(struct net_device *netdev,
1551 struct ethtool_stats *stats, u64 * data)
1552 {
1553 struct myri10ge_priv *mgp = netdev_priv(netdev);
1554 struct myri10ge_slice_state *ss;
1555 int i;
1556
1557 for (i = 0; i < MYRI10GE_NET_STATS_LEN; i++)
1558 data[i] = ((unsigned long *)&mgp->stats)[i];
1559
1560 data[i++] = (unsigned int)mgp->tx_boundary;
1561 data[i++] = (unsigned int)mgp->wc_enabled;
1562 data[i++] = (unsigned int)mgp->pdev->irq;
1563 data[i++] = (unsigned int)mgp->msi_enabled;
1564 data[i++] = (unsigned int)mgp->read_dma;
1565 data[i++] = (unsigned int)mgp->write_dma;
1566 data[i++] = (unsigned int)mgp->read_write_dma;
1567 data[i++] = (unsigned int)mgp->serial_number;
1568 data[i++] = (unsigned int)mgp->watchdog_resets;
1569 data[i++] = (unsigned int)mgp->link_changes;
1570
1571 /* firmware stats are useful only in the first slice */
1572 ss = &mgp->ss;
1573 data[i++] = (unsigned int)ntohl(ss->fw_stats->link_up);
1574 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_link_overflow);
1575 data[i++] =
1576 (unsigned int)ntohl(ss->fw_stats->dropped_link_error_or_filtered);
1577 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_pause);
1578 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_phy);
1579 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_bad_crc32);
1580 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_unicast_filtered);
1581 data[i++] =
1582 (unsigned int)ntohl(ss->fw_stats->dropped_multicast_filtered);
1583 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_runt);
1584 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_overrun);
1585 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_small_buffer);
1586 data[i++] = (unsigned int)ntohl(ss->fw_stats->dropped_no_big_buffer);
1587
1588 data[i++] = 0;
1589 data[i++] = (unsigned int)ss->tx.pkt_start;
1590 data[i++] = (unsigned int)ss->tx.pkt_done;
1591 data[i++] = (unsigned int)ss->tx.req;
1592 data[i++] = (unsigned int)ss->tx.done;
1593 data[i++] = (unsigned int)ss->rx_small.cnt;
1594 data[i++] = (unsigned int)ss->rx_big.cnt;
1595 data[i++] = (unsigned int)ss->tx.wake_queue;
1596 data[i++] = (unsigned int)ss->tx.stop_queue;
1597 data[i++] = (unsigned int)ss->tx.linearized;
1598 data[i++] = ss->rx_done.lro_mgr.stats.aggregated;
1599 data[i++] = ss->rx_done.lro_mgr.stats.flushed;
1600 if (ss->rx_done.lro_mgr.stats.flushed)
1601 data[i++] = ss->rx_done.lro_mgr.stats.aggregated /
1602 ss->rx_done.lro_mgr.stats.flushed;
1603 else
1604 data[i++] = 0;
1605 data[i++] = ss->rx_done.lro_mgr.stats.no_desc;
1606 }
1607
1608 static void myri10ge_set_msglevel(struct net_device *netdev, u32 value)
1609 {
1610 struct myri10ge_priv *mgp = netdev_priv(netdev);
1611 mgp->msg_enable = value;
1612 }
1613
1614 static u32 myri10ge_get_msglevel(struct net_device *netdev)
1615 {
1616 struct myri10ge_priv *mgp = netdev_priv(netdev);
1617 return mgp->msg_enable;
1618 }
1619
1620 static const struct ethtool_ops myri10ge_ethtool_ops = {
1621 .get_settings = myri10ge_get_settings,
1622 .get_drvinfo = myri10ge_get_drvinfo,
1623 .get_coalesce = myri10ge_get_coalesce,
1624 .set_coalesce = myri10ge_set_coalesce,
1625 .get_pauseparam = myri10ge_get_pauseparam,
1626 .set_pauseparam = myri10ge_set_pauseparam,
1627 .get_ringparam = myri10ge_get_ringparam,
1628 .get_rx_csum = myri10ge_get_rx_csum,
1629 .set_rx_csum = myri10ge_set_rx_csum,
1630 .set_tx_csum = ethtool_op_set_tx_hw_csum,
1631 .set_sg = ethtool_op_set_sg,
1632 .set_tso = myri10ge_set_tso,
1633 .get_link = ethtool_op_get_link,
1634 .get_strings = myri10ge_get_strings,
1635 .get_sset_count = myri10ge_get_sset_count,
1636 .get_ethtool_stats = myri10ge_get_ethtool_stats,
1637 .set_msglevel = myri10ge_set_msglevel,
1638 .get_msglevel = myri10ge_get_msglevel
1639 };
1640
1641 static int myri10ge_allocate_rings(struct myri10ge_slice_state *ss)
1642 {
1643 struct myri10ge_priv *mgp = ss->mgp;
1644 struct myri10ge_cmd cmd;
1645 struct net_device *dev = mgp->dev;
1646 int tx_ring_size, rx_ring_size;
1647 int tx_ring_entries, rx_ring_entries;
1648 int i, status;
1649 size_t bytes;
1650
1651 /* get ring sizes */
1652 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_RING_SIZE, &cmd, 0);
1653 tx_ring_size = cmd.data0;
1654 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_RX_RING_SIZE, &cmd, 0);
1655 if (status != 0)
1656 return status;
1657 rx_ring_size = cmd.data0;
1658
1659 tx_ring_entries = tx_ring_size / sizeof(struct mcp_kreq_ether_send);
1660 rx_ring_entries = rx_ring_size / sizeof(struct mcp_dma_addr);
1661 ss->tx.mask = tx_ring_entries - 1;
1662 ss->rx_small.mask = ss->rx_big.mask = rx_ring_entries - 1;
1663
1664 status = -ENOMEM;
1665
1666 /* allocate the host shadow rings */
1667
1668 bytes = 8 + (MYRI10GE_MAX_SEND_DESC_TSO + 4)
1669 * sizeof(*ss->tx.req_list);
1670 ss->tx.req_bytes = kzalloc(bytes, GFP_KERNEL);
1671 if (ss->tx.req_bytes == NULL)
1672 goto abort_with_nothing;
1673
1674 /* ensure req_list entries are aligned to 8 bytes */
1675 ss->tx.req_list = (struct mcp_kreq_ether_send *)
1676 ALIGN((unsigned long)ss->tx.req_bytes, 8);
1677
1678 bytes = rx_ring_entries * sizeof(*ss->rx_small.shadow);
1679 ss->rx_small.shadow = kzalloc(bytes, GFP_KERNEL);
1680 if (ss->rx_small.shadow == NULL)
1681 goto abort_with_tx_req_bytes;
1682
1683 bytes = rx_ring_entries * sizeof(*ss->rx_big.shadow);
1684 ss->rx_big.shadow = kzalloc(bytes, GFP_KERNEL);
1685 if (ss->rx_big.shadow == NULL)
1686 goto abort_with_rx_small_shadow;
1687
1688 /* allocate the host info rings */
1689
1690 bytes = tx_ring_entries * sizeof(*ss->tx.info);
1691 ss->tx.info = kzalloc(bytes, GFP_KERNEL);
1692 if (ss->tx.info == NULL)
1693 goto abort_with_rx_big_shadow;
1694
1695 bytes = rx_ring_entries * sizeof(*ss->rx_small.info);
1696 ss->rx_small.info = kzalloc(bytes, GFP_KERNEL);
1697 if (ss->rx_small.info == NULL)
1698 goto abort_with_tx_info;
1699
1700 bytes = rx_ring_entries * sizeof(*ss->rx_big.info);
1701 ss->rx_big.info = kzalloc(bytes, GFP_KERNEL);
1702 if (ss->rx_big.info == NULL)
1703 goto abort_with_rx_small_info;
1704
1705 /* Fill the receive rings */
1706 ss->rx_big.cnt = 0;
1707 ss->rx_small.cnt = 0;
1708 ss->rx_big.fill_cnt = 0;
1709 ss->rx_small.fill_cnt = 0;
1710 ss->rx_small.page_offset = MYRI10GE_ALLOC_SIZE;
1711 ss->rx_big.page_offset = MYRI10GE_ALLOC_SIZE;
1712 ss->rx_small.watchdog_needed = 0;
1713 ss->rx_big.watchdog_needed = 0;
1714 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
1715 mgp->small_bytes + MXGEFW_PAD, 0);
1716
1717 if (ss->rx_small.fill_cnt < ss->rx_small.mask + 1) {
1718 printk(KERN_ERR "myri10ge: %s: alloced only %d small bufs\n",
1719 dev->name, ss->rx_small.fill_cnt);
1720 goto abort_with_rx_small_ring;
1721 }
1722
1723 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 0);
1724 if (ss->rx_big.fill_cnt < ss->rx_big.mask + 1) {
1725 printk(KERN_ERR "myri10ge: %s: alloced only %d big bufs\n",
1726 dev->name, ss->rx_big.fill_cnt);
1727 goto abort_with_rx_big_ring;
1728 }
1729
1730 return 0;
1731
1732 abort_with_rx_big_ring:
1733 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1734 int idx = i & ss->rx_big.mask;
1735 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1736 mgp->big_bytes);
1737 put_page(ss->rx_big.info[idx].page);
1738 }
1739
1740 abort_with_rx_small_ring:
1741 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1742 int idx = i & ss->rx_small.mask;
1743 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1744 mgp->small_bytes + MXGEFW_PAD);
1745 put_page(ss->rx_small.info[idx].page);
1746 }
1747
1748 kfree(ss->rx_big.info);
1749
1750 abort_with_rx_small_info:
1751 kfree(ss->rx_small.info);
1752
1753 abort_with_tx_info:
1754 kfree(ss->tx.info);
1755
1756 abort_with_rx_big_shadow:
1757 kfree(ss->rx_big.shadow);
1758
1759 abort_with_rx_small_shadow:
1760 kfree(ss->rx_small.shadow);
1761
1762 abort_with_tx_req_bytes:
1763 kfree(ss->tx.req_bytes);
1764 ss->tx.req_bytes = NULL;
1765 ss->tx.req_list = NULL;
1766
1767 abort_with_nothing:
1768 return status;
1769 }
1770
1771 static void myri10ge_free_rings(struct myri10ge_slice_state *ss)
1772 {
1773 struct myri10ge_priv *mgp = ss->mgp;
1774 struct sk_buff *skb;
1775 struct myri10ge_tx_buf *tx;
1776 int i, len, idx;
1777
1778 for (i = ss->rx_big.cnt; i < ss->rx_big.fill_cnt; i++) {
1779 idx = i & ss->rx_big.mask;
1780 if (i == ss->rx_big.fill_cnt - 1)
1781 ss->rx_big.info[idx].page_offset = MYRI10GE_ALLOC_SIZE;
1782 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_big.info[idx],
1783 mgp->big_bytes);
1784 put_page(ss->rx_big.info[idx].page);
1785 }
1786
1787 for (i = ss->rx_small.cnt; i < ss->rx_small.fill_cnt; i++) {
1788 idx = i & ss->rx_small.mask;
1789 if (i == ss->rx_small.fill_cnt - 1)
1790 ss->rx_small.info[idx].page_offset =
1791 MYRI10GE_ALLOC_SIZE;
1792 myri10ge_unmap_rx_page(mgp->pdev, &ss->rx_small.info[idx],
1793 mgp->small_bytes + MXGEFW_PAD);
1794 put_page(ss->rx_small.info[idx].page);
1795 }
1796 tx = &ss->tx;
1797 while (tx->done != tx->req) {
1798 idx = tx->done & tx->mask;
1799 skb = tx->info[idx].skb;
1800
1801 /* Mark as free */
1802 tx->info[idx].skb = NULL;
1803 tx->done++;
1804 len = pci_unmap_len(&tx->info[idx], len);
1805 pci_unmap_len_set(&tx->info[idx], len, 0);
1806 if (skb) {
1807 ss->stats.tx_dropped++;
1808 dev_kfree_skb_any(skb);
1809 if (len)
1810 pci_unmap_single(mgp->pdev,
1811 pci_unmap_addr(&tx->info[idx],
1812 bus), len,
1813 PCI_DMA_TODEVICE);
1814 } else {
1815 if (len)
1816 pci_unmap_page(mgp->pdev,
1817 pci_unmap_addr(&tx->info[idx],
1818 bus), len,
1819 PCI_DMA_TODEVICE);
1820 }
1821 }
1822 kfree(ss->rx_big.info);
1823
1824 kfree(ss->rx_small.info);
1825
1826 kfree(ss->tx.info);
1827
1828 kfree(ss->rx_big.shadow);
1829
1830 kfree(ss->rx_small.shadow);
1831
1832 kfree(ss->tx.req_bytes);
1833 ss->tx.req_bytes = NULL;
1834 ss->tx.req_list = NULL;
1835 }
1836
1837 static int myri10ge_request_irq(struct myri10ge_priv *mgp)
1838 {
1839 struct pci_dev *pdev = mgp->pdev;
1840 int status;
1841
1842 if (myri10ge_msi) {
1843 status = pci_enable_msi(pdev);
1844 if (status != 0)
1845 dev_err(&pdev->dev,
1846 "Error %d setting up MSI; falling back to xPIC\n",
1847 status);
1848 else
1849 mgp->msi_enabled = 1;
1850 } else {
1851 mgp->msi_enabled = 0;
1852 }
1853 status = request_irq(pdev->irq, myri10ge_intr, IRQF_SHARED,
1854 mgp->dev->name, mgp);
1855 if (status != 0) {
1856 dev_err(&pdev->dev, "failed to allocate IRQ\n");
1857 if (mgp->msi_enabled)
1858 pci_disable_msi(pdev);
1859 }
1860 return status;
1861 }
1862
1863 static void myri10ge_free_irq(struct myri10ge_priv *mgp)
1864 {
1865 struct pci_dev *pdev = mgp->pdev;
1866
1867 free_irq(pdev->irq, mgp);
1868 if (mgp->msi_enabled)
1869 pci_disable_msi(pdev);
1870 }
1871
1872 static int
1873 myri10ge_get_frag_header(struct skb_frag_struct *frag, void **mac_hdr,
1874 void **ip_hdr, void **tcpudp_hdr,
1875 u64 * hdr_flags, void *priv)
1876 {
1877 struct ethhdr *eh;
1878 struct vlan_ethhdr *veh;
1879 struct iphdr *iph;
1880 u8 *va = page_address(frag->page) + frag->page_offset;
1881 unsigned long ll_hlen;
1882 /* passed opaque through lro_receive_frags() */
1883 __wsum csum = (__force __wsum) (unsigned long)priv;
1884
1885 /* find the mac header, aborting if not IPv4 */
1886
1887 eh = (struct ethhdr *)va;
1888 *mac_hdr = eh;
1889 ll_hlen = ETH_HLEN;
1890 if (eh->h_proto != htons(ETH_P_IP)) {
1891 if (eh->h_proto == htons(ETH_P_8021Q)) {
1892 veh = (struct vlan_ethhdr *)va;
1893 if (veh->h_vlan_encapsulated_proto != htons(ETH_P_IP))
1894 return -1;
1895
1896 ll_hlen += VLAN_HLEN;
1897
1898 /*
1899 * HW checksum starts ETH_HLEN bytes into
1900 * frame, so we must subtract off the VLAN
1901 * header's checksum before csum can be used
1902 */
1903 csum = csum_sub(csum, csum_partial(va + ETH_HLEN,
1904 VLAN_HLEN, 0));
1905 } else {
1906 return -1;
1907 }
1908 }
1909 *hdr_flags = LRO_IPV4;
1910
1911 iph = (struct iphdr *)(va + ll_hlen);
1912 *ip_hdr = iph;
1913 if (iph->protocol != IPPROTO_TCP)
1914 return -1;
1915 *hdr_flags |= LRO_TCP;
1916 *tcpudp_hdr = (u8 *) (*ip_hdr) + (iph->ihl << 2);
1917
1918 /* verify the IP checksum */
1919 if (unlikely(ip_fast_csum((u8 *) iph, iph->ihl)))
1920 return -1;
1921
1922 /* verify the checksum */
1923 if (unlikely(csum_tcpudp_magic(iph->saddr, iph->daddr,
1924 ntohs(iph->tot_len) - (iph->ihl << 2),
1925 IPPROTO_TCP, csum)))
1926 return -1;
1927
1928 return 0;
1929 }
1930
1931 static int myri10ge_open(struct net_device *dev)
1932 {
1933 struct myri10ge_priv *mgp = netdev_priv(dev);
1934 struct myri10ge_cmd cmd;
1935 struct net_lro_mgr *lro_mgr;
1936 int status, big_pow2;
1937
1938 if (mgp->running != MYRI10GE_ETH_STOPPED)
1939 return -EBUSY;
1940
1941 mgp->running = MYRI10GE_ETH_STARTING;
1942 status = myri10ge_reset(mgp);
1943 if (status != 0) {
1944 printk(KERN_ERR "myri10ge: %s: failed reset\n", dev->name);
1945 goto abort_with_nothing;
1946 }
1947
1948 status = myri10ge_request_irq(mgp);
1949 if (status != 0)
1950 goto abort_with_nothing;
1951
1952 /* decide what small buffer size to use. For good TCP rx
1953 * performance, it is important to not receive 1514 byte
1954 * frames into jumbo buffers, as it confuses the socket buffer
1955 * accounting code, leading to drops and erratic performance.
1956 */
1957
1958 if (dev->mtu <= ETH_DATA_LEN)
1959 /* enough for a TCP header */
1960 mgp->small_bytes = (128 > SMP_CACHE_BYTES)
1961 ? (128 - MXGEFW_PAD)
1962 : (SMP_CACHE_BYTES - MXGEFW_PAD);
1963 else
1964 /* enough for a vlan encapsulated ETH_DATA_LEN frame */
1965 mgp->small_bytes = VLAN_ETH_FRAME_LEN;
1966
1967 /* Override the small buffer size? */
1968 if (myri10ge_small_bytes > 0)
1969 mgp->small_bytes = myri10ge_small_bytes;
1970
1971 /* get the lanai pointers to the send and receive rings */
1972
1973 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SEND_OFFSET, &cmd, 0);
1974 mgp->ss.tx.lanai =
1975 (struct mcp_kreq_ether_send __iomem *)(mgp->sram + cmd.data0);
1976
1977 status |=
1978 myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_SMALL_RX_OFFSET, &cmd, 0);
1979 mgp->ss.rx_small.lanai =
1980 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1981
1982 status |= myri10ge_send_cmd(mgp, MXGEFW_CMD_GET_BIG_RX_OFFSET, &cmd, 0);
1983 mgp->ss.rx_big.lanai =
1984 (struct mcp_kreq_ether_recv __iomem *)(mgp->sram + cmd.data0);
1985
1986 if (status != 0) {
1987 printk(KERN_ERR
1988 "myri10ge: %s: failed to get ring sizes or locations\n",
1989 dev->name);
1990 mgp->running = MYRI10GE_ETH_STOPPED;
1991 goto abort_with_irq;
1992 }
1993
1994 if (myri10ge_wcfifo && mgp->wc_enabled) {
1995 mgp->ss.tx.wc_fifo = (u8 __iomem *) mgp->sram + MXGEFW_ETH_SEND_4;
1996 mgp->ss.rx_small.wc_fifo =
1997 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_SMALL;
1998 mgp->ss.rx_big.wc_fifo =
1999 (u8 __iomem *) mgp->sram + MXGEFW_ETH_RECV_BIG;
2000 } else {
2001 mgp->ss.tx.wc_fifo = NULL;
2002 mgp->ss.rx_small.wc_fifo = NULL;
2003 mgp->ss.rx_big.wc_fifo = NULL;
2004 }
2005
2006 /* Firmware needs the big buff size as a power of 2. Lie and
2007 * tell him the buffer is larger, because we only use 1
2008 * buffer/pkt, and the mtu will prevent overruns.
2009 */
2010 big_pow2 = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2011 if (big_pow2 < MYRI10GE_ALLOC_SIZE / 2) {
2012 while (!is_power_of_2(big_pow2))
2013 big_pow2++;
2014 mgp->big_bytes = dev->mtu + ETH_HLEN + VLAN_HLEN + MXGEFW_PAD;
2015 } else {
2016 big_pow2 = MYRI10GE_ALLOC_SIZE;
2017 mgp->big_bytes = big_pow2;
2018 }
2019
2020 status = myri10ge_allocate_rings(&mgp->ss);
2021 if (status != 0)
2022 goto abort_with_irq;
2023
2024 /* now give firmware buffers sizes, and MTU */
2025 cmd.data0 = dev->mtu + ETH_HLEN + VLAN_HLEN;
2026 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_MTU, &cmd, 0);
2027 cmd.data0 = mgp->small_bytes;
2028 status |=
2029 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_SMALL_BUFFER_SIZE, &cmd, 0);
2030 cmd.data0 = big_pow2;
2031 status |=
2032 myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_BIG_BUFFER_SIZE, &cmd, 0);
2033 if (status) {
2034 printk(KERN_ERR "myri10ge: %s: Couldn't set buffer sizes\n",
2035 dev->name);
2036 goto abort_with_rings;
2037 }
2038
2039 cmd.data0 = MYRI10GE_LOWPART_TO_U32(mgp->ss.fw_stats_bus);
2040 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(mgp->ss.fw_stats_bus);
2041 cmd.data2 = sizeof(struct mcp_irq_data);
2042 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_SET_STATS_DMA_V2, &cmd, 0);
2043 if (status == -ENOSYS) {
2044 dma_addr_t bus = mgp->ss.fw_stats_bus;
2045 bus += offsetof(struct mcp_irq_data, send_done_count);
2046 cmd.data0 = MYRI10GE_LOWPART_TO_U32(bus);
2047 cmd.data1 = MYRI10GE_HIGHPART_TO_U32(bus);
2048 status = myri10ge_send_cmd(mgp,
2049 MXGEFW_CMD_SET_STATS_DMA_OBSOLETE,
2050 &cmd, 0);
2051 /* Firmware cannot support multicast without STATS_DMA_V2 */
2052 mgp->fw_multicast_support = 0;
2053 } else {
2054 mgp->fw_multicast_support = 1;
2055 }
2056 if (status) {
2057 printk(KERN_ERR "myri10ge: %s: Couldn't set stats DMA\n",
2058 dev->name);
2059 goto abort_with_rings;
2060 }
2061
2062 mgp->link_state = ~0U;
2063 mgp->rdma_tags_available = 15;
2064
2065 lro_mgr = &mgp->ss.rx_done.lro_mgr;
2066 lro_mgr->dev = dev;
2067 lro_mgr->features = LRO_F_NAPI;
2068 lro_mgr->ip_summed = CHECKSUM_COMPLETE;
2069 lro_mgr->ip_summed_aggr = CHECKSUM_UNNECESSARY;
2070 lro_mgr->max_desc = MYRI10GE_MAX_LRO_DESCRIPTORS;
2071 lro_mgr->lro_arr = mgp->ss.rx_done.lro_desc;
2072 lro_mgr->get_frag_header = myri10ge_get_frag_header;
2073 lro_mgr->max_aggr = myri10ge_lro_max_pkts;
2074 lro_mgr->frag_align_pad = 2;
2075 if (lro_mgr->max_aggr > MAX_SKB_FRAGS)
2076 lro_mgr->max_aggr = MAX_SKB_FRAGS;
2077
2078 napi_enable(&mgp->ss.napi); /* must happen prior to any irq */
2079
2080 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_UP, &cmd, 0);
2081 if (status) {
2082 printk(KERN_ERR "myri10ge: %s: Couldn't bring up link\n",
2083 dev->name);
2084 goto abort_with_rings;
2085 }
2086
2087 mgp->ss.tx.wake_queue = 0;
2088 mgp->ss.tx.stop_queue = 0;
2089 mgp->running = MYRI10GE_ETH_RUNNING;
2090 mgp->watchdog_timer.expires = jiffies + myri10ge_watchdog_timeout * HZ;
2091 add_timer(&mgp->watchdog_timer);
2092 netif_wake_queue(dev);
2093 return 0;
2094
2095 abort_with_rings:
2096 myri10ge_free_rings(&mgp->ss);
2097
2098 abort_with_irq:
2099 myri10ge_free_irq(mgp);
2100
2101 abort_with_nothing:
2102 mgp->running = MYRI10GE_ETH_STOPPED;
2103 return -ENOMEM;
2104 }
2105
2106 static int myri10ge_close(struct net_device *dev)
2107 {
2108 struct myri10ge_priv *mgp = netdev_priv(dev);
2109 struct myri10ge_cmd cmd;
2110 int status, old_down_cnt;
2111
2112 if (mgp->running != MYRI10GE_ETH_RUNNING)
2113 return 0;
2114
2115 if (mgp->ss.tx.req_bytes == NULL)
2116 return 0;
2117
2118 del_timer_sync(&mgp->watchdog_timer);
2119 mgp->running = MYRI10GE_ETH_STOPPING;
2120 napi_disable(&mgp->ss.napi);
2121 netif_carrier_off(dev);
2122 netif_stop_queue(dev);
2123 old_down_cnt = mgp->down_cnt;
2124 mb();
2125 status = myri10ge_send_cmd(mgp, MXGEFW_CMD_ETHERNET_DOWN, &cmd, 0);
2126 if (status)
2127 printk(KERN_ERR "myri10ge: %s: Couldn't bring down link\n",
2128 dev->name);
2129
2130 wait_event_timeout(mgp->down_wq, old_down_cnt != mgp->down_cnt, HZ);
2131 if (old_down_cnt == mgp->down_cnt)
2132 printk(KERN_ERR "myri10ge: %s never got down irq\n", dev->name);
2133
2134 netif_tx_disable(dev);
2135 myri10ge_free_irq(mgp);
2136 myri10ge_free_rings(&mgp->ss);
2137
2138 mgp->running = MYRI10GE_ETH_STOPPED;
2139 return 0;
2140 }
2141
2142 /* copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2143 * backwards one at a time and handle ring wraps */
2144
2145 static inline void
2146 myri10ge_submit_req_backwards(struct myri10ge_tx_buf *tx,
2147 struct mcp_kreq_ether_send *src, int cnt)
2148 {
2149 int idx, starting_slot;
2150 starting_slot = tx->req;
2151 while (cnt > 1) {
2152 cnt--;
2153 idx = (starting_slot + cnt) & tx->mask;
2154 myri10ge_pio_copy(&tx->lanai[idx], &src[cnt], sizeof(*src));
2155 mb();
2156 }
2157 }
2158
2159 /*
2160 * copy an array of struct mcp_kreq_ether_send's to the mcp. Copy
2161 * at most 32 bytes at a time, so as to avoid involving the software
2162 * pio handler in the nic. We re-write the first segment's flags
2163 * to mark them valid only after writing the entire chain.
2164 */
2165
2166 static inline void
2167 myri10ge_submit_req(struct myri10ge_tx_buf *tx, struct mcp_kreq_ether_send *src,
2168 int cnt)
2169 {
2170 int idx, i;
2171 struct mcp_kreq_ether_send __iomem *dstp, *dst;
2172 struct mcp_kreq_ether_send *srcp;
2173 u8 last_flags;
2174
2175 idx = tx->req & tx->mask;
2176
2177 last_flags = src->flags;
2178 src->flags = 0;
2179 mb();
2180 dst = dstp = &tx->lanai[idx];
2181 srcp = src;
2182
2183 if ((idx + cnt) < tx->mask) {
2184 for (i = 0; i < (cnt - 1); i += 2) {
2185 myri10ge_pio_copy(dstp, srcp, 2 * sizeof(*src));
2186 mb(); /* force write every 32 bytes */
2187 srcp += 2;
2188 dstp += 2;
2189 }
2190 } else {
2191 /* submit all but the first request, and ensure
2192 * that it is submitted below */
2193 myri10ge_submit_req_backwards(tx, src, cnt);
2194 i = 0;
2195 }
2196 if (i < cnt) {
2197 /* submit the first request */
2198 myri10ge_pio_copy(dstp, srcp, sizeof(*src));
2199 mb(); /* barrier before setting valid flag */
2200 }
2201
2202 /* re-write the last 32-bits with the valid flags */
2203 src->flags = last_flags;
2204 put_be32(*((__be32 *) src + 3), (__be32 __iomem *) dst + 3);
2205 tx->req += cnt;
2206 mb();
2207 }
2208
2209 static inline void
2210 myri10ge_submit_req_wc(struct myri10ge_tx_buf *tx,
2211 struct mcp_kreq_ether_send *src, int cnt)
2212 {
2213 tx->req += cnt;
2214 mb();
2215 while (cnt >= 4) {
2216 myri10ge_pio_copy(tx->wc_fifo, src, 64);
2217 mb();
2218 src += 4;
2219 cnt -= 4;
2220 }
2221 if (cnt > 0) {
2222 /* pad it to 64 bytes. The src is 64 bytes bigger than it
2223 * needs to be so that we don't overrun it */
2224 myri10ge_pio_copy(tx->wc_fifo + MXGEFW_ETH_SEND_OFFSET(cnt),
2225 src, 64);
2226 mb();
2227 }
2228 }
2229
2230 /*
2231 * Transmit a packet. We need to split the packet so that a single
2232 * segment does not cross myri10ge->tx_boundary, so this makes segment
2233 * counting tricky. So rather than try to count segments up front, we
2234 * just give up if there are too few segments to hold a reasonably
2235 * fragmented packet currently available. If we run
2236 * out of segments while preparing a packet for DMA, we just linearize
2237 * it and try again.
2238 */
2239
2240 static int myri10ge_xmit(struct sk_buff *skb, struct net_device *dev)
2241 {
2242 struct myri10ge_priv *mgp = netdev_priv(dev);
2243 struct myri10ge_slice_state *ss;
2244 struct mcp_kreq_ether_send *req;
2245 struct myri10ge_tx_buf *tx;
2246 struct skb_frag_struct *frag;
2247 dma_addr_t bus;
2248 u32 low;
2249 __be32 high_swapped;
2250 unsigned int len;
2251 int idx, last_idx, avail, frag_cnt, frag_idx, count, mss, max_segments;
2252 u16 pseudo_hdr_offset, cksum_offset;
2253 int cum_len, seglen, boundary, rdma_count;
2254 u8 flags, odd_flag;
2255
2256 /* always transmit through slot 0 */
2257 ss = &mgp->ss;
2258 tx = &ss->tx;
2259 again:
2260 req = tx->req_list;
2261 avail = tx->mask - 1 - (tx->req - tx->done);
2262
2263 mss = 0;
2264 max_segments = MXGEFW_MAX_SEND_DESC;
2265
2266 if (skb_is_gso(skb)) {
2267 mss = skb_shinfo(skb)->gso_size;
2268 max_segments = MYRI10GE_MAX_SEND_DESC_TSO;
2269 }
2270
2271 if ((unlikely(avail < max_segments))) {
2272 /* we are out of transmit resources */
2273 tx->stop_queue++;
2274 netif_stop_queue(dev);
2275 return 1;
2276 }
2277
2278 /* Setup checksum offloading, if needed */
2279 cksum_offset = 0;
2280 pseudo_hdr_offset = 0;
2281 odd_flag = 0;
2282 flags = (MXGEFW_FLAGS_NO_TSO | MXGEFW_FLAGS_FIRST);
2283 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) {
2284 cksum_offset = skb_transport_offset(skb);
2285 pseudo_hdr_offset = cksum_offset + skb->csum_offset;
2286 /* If the headers are excessively large, then we must
2287 * fall back to a software checksum */
2288 if (unlikely(!mss && (cksum_offset > 255 ||
2289 pseudo_hdr_offset > 127))) {
2290 if (skb_checksum_help(skb))
2291 goto drop;
2292 cksum_offset = 0;
2293 pseudo_hdr_offset = 0;
2294 } else {
2295 odd_flag = MXGEFW_FLAGS_ALIGN_ODD;
2296 flags |= MXGEFW_FLAGS_CKSUM;
2297 }
2298 }
2299
2300 cum_len = 0;
2301
2302 if (mss) { /* TSO */
2303 /* this removes any CKSUM flag from before */
2304 flags = (MXGEFW_FLAGS_TSO_HDR | MXGEFW_FLAGS_FIRST);
2305
2306 /* negative cum_len signifies to the
2307 * send loop that we are still in the
2308 * header portion of the TSO packet.
2309 * TSO header can be at most 1KB long */
2310 cum_len = -(skb_transport_offset(skb) + tcp_hdrlen(skb));
2311
2312 /* for IPv6 TSO, the checksum offset stores the
2313 * TCP header length, to save the firmware from
2314 * the need to parse the headers */
2315 if (skb_is_gso_v6(skb)) {
2316 cksum_offset = tcp_hdrlen(skb);
2317 /* Can only handle headers <= max_tso6 long */
2318 if (unlikely(-cum_len > mgp->max_tso6))
2319 return myri10ge_sw_tso(skb, dev);
2320 }
2321 /* for TSO, pseudo_hdr_offset holds mss.
2322 * The firmware figures out where to put
2323 * the checksum by parsing the header. */
2324 pseudo_hdr_offset = mss;
2325 } else
2326 /* Mark small packets, and pad out tiny packets */
2327 if (skb->len <= MXGEFW_SEND_SMALL_SIZE) {
2328 flags |= MXGEFW_FLAGS_SMALL;
2329
2330 /* pad frames to at least ETH_ZLEN bytes */
2331 if (unlikely(skb->len < ETH_ZLEN)) {
2332 if (skb_padto(skb, ETH_ZLEN)) {
2333 /* The packet is gone, so we must
2334 * return 0 */
2335 ss->stats.tx_dropped += 1;
2336 return 0;
2337 }
2338 /* adjust the len to account for the zero pad
2339 * so that the nic can know how long it is */
2340 skb->len = ETH_ZLEN;
2341 }
2342 }
2343
2344 /* map the skb for DMA */
2345 len = skb->len - skb->data_len;
2346 idx = tx->req & tx->mask;
2347 tx->info[idx].skb = skb;
2348 bus = pci_map_single(mgp->pdev, skb->data, len, PCI_DMA_TODEVICE);
2349 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2350 pci_unmap_len_set(&tx->info[idx], len, len);
2351
2352 frag_cnt = skb_shinfo(skb)->nr_frags;
2353 frag_idx = 0;
2354 count = 0;
2355 rdma_count = 0;
2356
2357 /* "rdma_count" is the number of RDMAs belonging to the
2358 * current packet BEFORE the current send request. For
2359 * non-TSO packets, this is equal to "count".
2360 * For TSO packets, rdma_count needs to be reset
2361 * to 0 after a segment cut.
2362 *
2363 * The rdma_count field of the send request is
2364 * the number of RDMAs of the packet starting at
2365 * that request. For TSO send requests with one ore more cuts
2366 * in the middle, this is the number of RDMAs starting
2367 * after the last cut in the request. All previous
2368 * segments before the last cut implicitly have 1 RDMA.
2369 *
2370 * Since the number of RDMAs is not known beforehand,
2371 * it must be filled-in retroactively - after each
2372 * segmentation cut or at the end of the entire packet.
2373 */
2374
2375 while (1) {
2376 /* Break the SKB or Fragment up into pieces which
2377 * do not cross mgp->tx_boundary */
2378 low = MYRI10GE_LOWPART_TO_U32(bus);
2379 high_swapped = htonl(MYRI10GE_HIGHPART_TO_U32(bus));
2380 while (len) {
2381 u8 flags_next;
2382 int cum_len_next;
2383
2384 if (unlikely(count == max_segments))
2385 goto abort_linearize;
2386
2387 boundary =
2388 (low + mgp->tx_boundary) & ~(mgp->tx_boundary - 1);
2389 seglen = boundary - low;
2390 if (seglen > len)
2391 seglen = len;
2392 flags_next = flags & ~MXGEFW_FLAGS_FIRST;
2393 cum_len_next = cum_len + seglen;
2394 if (mss) { /* TSO */
2395 (req - rdma_count)->rdma_count = rdma_count + 1;
2396
2397 if (likely(cum_len >= 0)) { /* payload */
2398 int next_is_first, chop;
2399
2400 chop = (cum_len_next > mss);
2401 cum_len_next = cum_len_next % mss;
2402 next_is_first = (cum_len_next == 0);
2403 flags |= chop * MXGEFW_FLAGS_TSO_CHOP;
2404 flags_next |= next_is_first *
2405 MXGEFW_FLAGS_FIRST;
2406 rdma_count |= -(chop | next_is_first);
2407 rdma_count += chop & !next_is_first;
2408 } else if (likely(cum_len_next >= 0)) { /* header ends */
2409 int small;
2410
2411 rdma_count = -1;
2412 cum_len_next = 0;
2413 seglen = -cum_len;
2414 small = (mss <= MXGEFW_SEND_SMALL_SIZE);
2415 flags_next = MXGEFW_FLAGS_TSO_PLD |
2416 MXGEFW_FLAGS_FIRST |
2417 (small * MXGEFW_FLAGS_SMALL);
2418 }
2419 }
2420 req->addr_high = high_swapped;
2421 req->addr_low = htonl(low);
2422 req->pseudo_hdr_offset = htons(pseudo_hdr_offset);
2423 req->pad = 0; /* complete solid 16-byte block; does this matter? */
2424 req->rdma_count = 1;
2425 req->length = htons(seglen);
2426 req->cksum_offset = cksum_offset;
2427 req->flags = flags | ((cum_len & 1) * odd_flag);
2428
2429 low += seglen;
2430 len -= seglen;
2431 cum_len = cum_len_next;
2432 flags = flags_next;
2433 req++;
2434 count++;
2435 rdma_count++;
2436 if (cksum_offset != 0 && !(mss && skb_is_gso_v6(skb))) {
2437 if (unlikely(cksum_offset > seglen))
2438 cksum_offset -= seglen;
2439 else
2440 cksum_offset = 0;
2441 }
2442 }
2443 if (frag_idx == frag_cnt)
2444 break;
2445
2446 /* map next fragment for DMA */
2447 idx = (count + tx->req) & tx->mask;
2448 frag = &skb_shinfo(skb)->frags[frag_idx];
2449 frag_idx++;
2450 len = frag->size;
2451 bus = pci_map_page(mgp->pdev, frag->page, frag->page_offset,
2452 len, PCI_DMA_TODEVICE);
2453 pci_unmap_addr_set(&tx->info[idx], bus, bus);
2454 pci_unmap_len_set(&tx->info[idx], len, len);
2455 }
2456
2457 (req - rdma_count)->rdma_count = rdma_count;
2458 if (mss)
2459 do {
2460 req--;
2461 req->flags |= MXGEFW_FLAGS_TSO_LAST;
2462 } while (!(req->flags & (MXGEFW_FLAGS_TSO_CHOP |
2463 MXGEFW_FLAGS_FIRST)));
2464 idx = ((count - 1) + tx->req) & tx->mask;
2465 tx->info[idx].last = 1;
2466 if (tx->wc_fifo == NULL)
2467 myri10ge_submit_req(tx, tx->req_list, count);
2468 else
2469 myri10ge_submit_req_wc(tx, tx->req_list, count);
2470 tx->pkt_start++;
2471 if ((avail - count) < MXGEFW_MAX_SEND_DESC) {
2472 tx->stop_queue++;
2473 netif_stop_queue(dev);
2474 }
2475 dev->trans_start = jiffies;
2476 return 0;
2477
2478 abort_linearize:
2479 /* Free any DMA resources we've alloced and clear out the skb
2480 * slot so as to not trip up assertions, and to avoid a
2481 * double-free if linearizing fails */
2482
2483 last_idx = (idx + 1) & tx->mask;
2484 idx = tx->req & tx->mask;
2485 tx->info[idx].skb = NULL;
2486 do {
2487 len = pci_unmap_len(&tx->info[idx], len);
2488 if (len) {
2489 if (tx->info[idx].skb != NULL)
2490 pci_unmap_single(mgp->pdev,
2491 pci_unmap_addr(&tx->info[idx],
2492 bus), len,
2493 PCI_DMA_TODEVICE);
2494 else
2495 pci_unmap_page(mgp->pdev,
2496 pci_unmap_addr(&tx->info[idx],
2497 bus), len,
2498 PCI_DMA_TODEVICE);
2499 pci_unmap_len_set(&tx->info[idx], len, 0);
2500 tx->info[idx].skb = NULL;
2501 }
2502 idx = (idx + 1) & tx->mask;
2503 } while (idx != last_idx);
2504 if (skb_is_gso(skb)) {
2505 printk(KERN_ERR
2506 "myri10ge: %s: TSO but wanted to linearize?!?!?\n",
2507 mgp->dev->name);
2508 goto drop;
2509 }
2510
2511 if (skb_linearize(skb))
2512 goto drop;
2513
2514 tx->linearized++;
2515 goto again;
2516
2517 drop:
2518 dev_kfree_skb_any(skb);
2519 ss->stats.tx_dropped += 1;
2520 return 0;
2521
2522 }
2523
2524 static int myri10ge_sw_tso(struct sk_buff *skb, struct net_device *dev)
2525 {
2526 struct sk_buff *segs, *curr;
2527 struct myri10ge_priv *mgp = netdev_priv(dev);
2528 int status;
2529
2530 segs = skb_gso_segment(skb, dev->features & ~NETIF_F_TSO6);
2531 if (IS_ERR(segs))
2532 goto drop;
2533
2534 while (segs) {
2535 curr = segs;
2536 segs = segs->next;
2537 curr->next = NULL;
2538 status = myri10ge_xmit(curr, dev);
2539 if (status != 0) {
2540 dev_kfree_skb_any(curr);
2541 if (segs != NULL) {
2542 curr = segs;
2543 segs = segs->next;
2544 curr->next = NULL;
2545 dev_kfree_skb_any(segs);
2546 }
2547 goto drop;
2548 }
2549 }
2550 dev_kfree_skb_any(skb);
2551 return 0;
2552
2553 drop:
2554 dev_kfree_skb_any(skb);
2555 mgp->stats.tx_dropped += 1;
2556 return 0;
2557 }
2558
2559 static struct net_device_stats *myri10ge_get_stats(struct net_device *dev)
2560 {
2561 struct myri10ge_priv *mgp = netdev_priv(dev);
2562 return &mgp->stats;
2563 }
2564
2565 static void myri10ge_set_multicast_list(struct net_device *dev)
2566 {
2567 struct myri10ge_priv *mgp = netdev_priv(dev);
2568 struct myri10ge_cmd cmd;
2569 struct dev_mc_list *mc_list;
2570 __be32 data[2] = { 0, 0 };
2571 int err;
2572 DECLARE_MAC_BUF(mac);
2573
2574 /* can be called from atomic contexts,
2575 * pass 1 to force atomicity in myri10ge_send_cmd() */
2576 myri10ge_change_promisc(mgp, dev->flags & IFF_PROMISC, 1);
2577
2578 /* This firmware is known to not support multicast */
2579 if (!mgp->fw_multicast_support)
2580 return;
2581
2582 /* Disable multicast filtering */
2583
2584 err = myri10ge_send_cmd(mgp, MXGEFW_ENABLE_ALLMULTI, &cmd, 1);
2585 if (err != 0) {
2586 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_ENABLE_ALLMULTI,"
2587 " error status: %d\n", dev->name, err);
2588 goto abort;
2589 }
2590
2591 if ((dev->flags & IFF_ALLMULTI) || mgp->adopted_rx_filter_bug) {
2592 /* request to disable multicast filtering, so quit here */
2593 return;
2594 }
2595
2596 /* Flush the filters */
2597
2598 err = myri10ge_send_cmd(mgp, MXGEFW_LEAVE_ALL_MULTICAST_GROUPS,
2599 &cmd, 1);
2600 if (err != 0) {
2601 printk(KERN_ERR
2602 "myri10ge: %s: Failed MXGEFW_LEAVE_ALL_MULTICAST_GROUPS"
2603 ", error status: %d\n", dev->name, err);
2604 goto abort;
2605 }
2606
2607 /* Walk the multicast list, and add each address */
2608 for (mc_list = dev->mc_list; mc_list != NULL; mc_list = mc_list->next) {
2609 memcpy(data, &mc_list->dmi_addr, 6);
2610 cmd.data0 = ntohl(data[0]);
2611 cmd.data1 = ntohl(data[1]);
2612 err = myri10ge_send_cmd(mgp, MXGEFW_JOIN_MULTICAST_GROUP,
2613 &cmd, 1);
2614
2615 if (err != 0) {
2616 printk(KERN_ERR "myri10ge: %s: Failed "
2617 "MXGEFW_JOIN_MULTICAST_GROUP, error status:"
2618 "%d\t", dev->name, err);
2619 printk(KERN_ERR "MAC %s\n",
2620 print_mac(mac, mc_list->dmi_addr));
2621 goto abort;
2622 }
2623 }
2624 /* Enable multicast filtering */
2625 err = myri10ge_send_cmd(mgp, MXGEFW_DISABLE_ALLMULTI, &cmd, 1);
2626 if (err != 0) {
2627 printk(KERN_ERR "myri10ge: %s: Failed MXGEFW_DISABLE_ALLMULTI,"
2628 "error status: %d\n", dev->name, err);
2629 goto abort;
2630 }
2631
2632 return;
2633
2634 abort:
2635 return;
2636 }
2637
2638 static int myri10ge_set_mac_address(struct net_device *dev, void *addr)
2639 {
2640 struct sockaddr *sa = addr;
2641 struct myri10ge_priv *mgp = netdev_priv(dev);
2642 int status;
2643
2644 if (!is_valid_ether_addr(sa->sa_data))
2645 return -EADDRNOTAVAIL;
2646
2647 status = myri10ge_update_mac_address(mgp, sa->sa_data);
2648 if (status != 0) {
2649 printk(KERN_ERR
2650 "myri10ge: %s: changing mac address failed with %d\n",
2651 dev->name, status);
2652 return status;
2653 }
2654
2655 /* change the dev structure */
2656 memcpy(dev->dev_addr, sa->sa_data, 6);
2657 return 0;
2658 }
2659
2660 static int myri10ge_change_mtu(struct net_device *dev, int new_mtu)
2661 {
2662 struct myri10ge_priv *mgp = netdev_priv(dev);
2663 int error = 0;
2664
2665 if ((new_mtu < 68) || (ETH_HLEN + new_mtu > MYRI10GE_MAX_ETHER_MTU)) {
2666 printk(KERN_ERR "myri10ge: %s: new mtu (%d) is not valid\n",
2667 dev->name, new_mtu);
2668 return -EINVAL;
2669 }
2670 printk(KERN_INFO "%s: changing mtu from %d to %d\n",
2671 dev->name, dev->mtu, new_mtu);
2672 if (mgp->running) {
2673 /* if we change the mtu on an active device, we must
2674 * reset the device so the firmware sees the change */
2675 myri10ge_close(dev);
2676 dev->mtu = new_mtu;
2677 myri10ge_open(dev);
2678 } else
2679 dev->mtu = new_mtu;
2680
2681 return error;
2682 }
2683
2684 /*
2685 * Enable ECRC to align PCI-E Completion packets on an 8-byte boundary.
2686 * Only do it if the bridge is a root port since we don't want to disturb
2687 * any other device, except if forced with myri10ge_ecrc_enable > 1.
2688 */
2689
2690 static void myri10ge_enable_ecrc(struct myri10ge_priv *mgp)
2691 {
2692 struct pci_dev *bridge = mgp->pdev->bus->self;
2693 struct device *dev = &mgp->pdev->dev;
2694 unsigned cap;
2695 unsigned err_cap;
2696 u16 val;
2697 u8 ext_type;
2698 int ret;
2699
2700 if (!myri10ge_ecrc_enable || !bridge)
2701 return;
2702
2703 /* check that the bridge is a root port */
2704 cap = pci_find_capability(bridge, PCI_CAP_ID_EXP);
2705 pci_read_config_word(bridge, cap + PCI_CAP_FLAGS, &val);
2706 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2707 if (ext_type != PCI_EXP_TYPE_ROOT_PORT) {
2708 if (myri10ge_ecrc_enable > 1) {
2709 struct pci_dev *prev_bridge, *old_bridge = bridge;
2710
2711 /* Walk the hierarchy up to the root port
2712 * where ECRC has to be enabled */
2713 do {
2714 prev_bridge = bridge;
2715 bridge = bridge->bus->self;
2716 if (!bridge || prev_bridge == bridge) {
2717 dev_err(dev,
2718 "Failed to find root port"
2719 " to force ECRC\n");
2720 return;
2721 }
2722 cap =
2723 pci_find_capability(bridge, PCI_CAP_ID_EXP);
2724 pci_read_config_word(bridge,
2725 cap + PCI_CAP_FLAGS, &val);
2726 ext_type = (val & PCI_EXP_FLAGS_TYPE) >> 4;
2727 } while (ext_type != PCI_EXP_TYPE_ROOT_PORT);
2728
2729 dev_info(dev,
2730 "Forcing ECRC on non-root port %s"
2731 " (enabling on root port %s)\n",
2732 pci_name(old_bridge), pci_name(bridge));
2733 } else {
2734 dev_err(dev,
2735 "Not enabling ECRC on non-root port %s\n",
2736 pci_name(bridge));
2737 return;
2738 }
2739 }
2740
2741 cap = pci_find_ext_capability(bridge, PCI_EXT_CAP_ID_ERR);
2742 if (!cap)
2743 return;
2744
2745 ret = pci_read_config_dword(bridge, cap + PCI_ERR_CAP, &err_cap);
2746 if (ret) {
2747 dev_err(dev, "failed reading ext-conf-space of %s\n",
2748 pci_name(bridge));
2749 dev_err(dev, "\t pci=nommconf in use? "
2750 "or buggy/incomplete/absent ACPI MCFG attr?\n");
2751 return;
2752 }
2753 if (!(err_cap & PCI_ERR_CAP_ECRC_GENC))
2754 return;
2755
2756 err_cap |= PCI_ERR_CAP_ECRC_GENE;
2757 pci_write_config_dword(bridge, cap + PCI_ERR_CAP, err_cap);
2758 dev_info(dev, "Enabled ECRC on upstream bridge %s\n", pci_name(bridge));
2759 }
2760
2761 /*
2762 * The Lanai Z8E PCI-E interface achieves higher Read-DMA throughput
2763 * when the PCI-E Completion packets are aligned on an 8-byte
2764 * boundary. Some PCI-E chip sets always align Completion packets; on
2765 * the ones that do not, the alignment can be enforced by enabling
2766 * ECRC generation (if supported).
2767 *
2768 * When PCI-E Completion packets are not aligned, it is actually more
2769 * efficient to limit Read-DMA transactions to 2KB, rather than 4KB.
2770 *
2771 * If the driver can neither enable ECRC nor verify that it has
2772 * already been enabled, then it must use a firmware image which works
2773 * around unaligned completion packets (myri10ge_ethp_z8e.dat), and it
2774 * should also ensure that it never gives the device a Read-DMA which is
2775 * larger than 2KB by setting the tx_boundary to 2KB. If ECRC is
2776 * enabled, then the driver should use the aligned (myri10ge_eth_z8e.dat)
2777 * firmware image, and set tx_boundary to 4KB.
2778 */
2779
2780 static void myri10ge_firmware_probe(struct myri10ge_priv *mgp)
2781 {
2782 struct pci_dev *pdev = mgp->pdev;
2783 struct device *dev = &pdev->dev;
2784 int status;
2785
2786 mgp->tx_boundary = 4096;
2787 /*
2788 * Verify the max read request size was set to 4KB
2789 * before trying the test with 4KB.
2790 */
2791 status = pcie_get_readrq(pdev);
2792 if (status < 0) {
2793 dev_err(dev, "Couldn't read max read req size: %d\n", status);
2794 goto abort;
2795 }
2796 if (status != 4096) {
2797 dev_warn(dev, "Max Read Request size != 4096 (%d)\n", status);
2798 mgp->tx_boundary = 2048;
2799 }
2800 /*
2801 * load the optimized firmware (which assumes aligned PCIe
2802 * completions) in order to see if it works on this host.
2803 */
2804 mgp->fw_name = myri10ge_fw_aligned;
2805 status = myri10ge_load_firmware(mgp);
2806 if (status != 0) {
2807 goto abort;
2808 }
2809
2810 /*
2811 * Enable ECRC if possible
2812 */
2813 myri10ge_enable_ecrc(mgp);
2814
2815 /*
2816 * Run a DMA test which watches for unaligned completions and
2817 * aborts on the first one seen.
2818 */
2819
2820 status = myri10ge_dma_test(mgp, MXGEFW_CMD_UNALIGNED_TEST);
2821 if (status == 0)
2822 return; /* keep the aligned firmware */
2823
2824 if (status != -E2BIG)
2825 dev_warn(dev, "DMA test failed: %d\n", status);
2826 if (status == -ENOSYS)
2827 dev_warn(dev, "Falling back to ethp! "
2828 "Please install up to date fw\n");
2829 abort:
2830 /* fall back to using the unaligned firmware */
2831 mgp->tx_boundary = 2048;
2832 mgp->fw_name = myri10ge_fw_unaligned;
2833
2834 }
2835
2836 static void myri10ge_select_firmware(struct myri10ge_priv *mgp)
2837 {
2838 if (myri10ge_force_firmware == 0) {
2839 int link_width, exp_cap;
2840 u16 lnk;
2841
2842 exp_cap = pci_find_capability(mgp->pdev, PCI_CAP_ID_EXP);
2843 pci_read_config_word(mgp->pdev, exp_cap + PCI_EXP_LNKSTA, &lnk);
2844 link_width = (lnk >> 4) & 0x3f;
2845
2846 /* Check to see if Link is less than 8 or if the
2847 * upstream bridge is known to provide aligned
2848 * completions */
2849 if (link_width < 8) {
2850 dev_info(&mgp->pdev->dev, "PCIE x%d Link\n",
2851 link_width);
2852 mgp->tx_boundary = 4096;
2853 mgp->fw_name = myri10ge_fw_aligned;
2854 } else {
2855 myri10ge_firmware_probe(mgp);
2856 }
2857 } else {
2858 if (myri10ge_force_firmware == 1) {
2859 dev_info(&mgp->pdev->dev,
2860 "Assuming aligned completions (forced)\n");
2861 mgp->tx_boundary = 4096;
2862 mgp->fw_name = myri10ge_fw_aligned;
2863 } else {
2864 dev_info(&mgp->pdev->dev,
2865 "Assuming unaligned completions (forced)\n");
2866 mgp->tx_boundary = 2048;
2867 mgp->fw_name = myri10ge_fw_unaligned;
2868 }
2869 }
2870 if (myri10ge_fw_name != NULL) {
2871 dev_info(&mgp->pdev->dev, "overriding firmware to %s\n",
2872 myri10ge_fw_name);
2873 mgp->fw_name = myri10ge_fw_name;
2874 }
2875 }
2876
2877 #ifdef CONFIG_PM
2878 static int myri10ge_suspend(struct pci_dev *pdev, pm_message_t state)
2879 {
2880 struct myri10ge_priv *mgp;
2881 struct net_device *netdev;
2882
2883 mgp = pci_get_drvdata(pdev);
2884 if (mgp == NULL)
2885 return -EINVAL;
2886 netdev = mgp->dev;
2887
2888 netif_device_detach(netdev);
2889 if (netif_running(netdev)) {
2890 printk(KERN_INFO "myri10ge: closing %s\n", netdev->name);
2891 rtnl_lock();
2892 myri10ge_close(netdev);
2893 rtnl_unlock();
2894 }
2895 myri10ge_dummy_rdma(mgp, 0);
2896 pci_save_state(pdev);
2897 pci_disable_device(pdev);
2898
2899 return pci_set_power_state(pdev, pci_choose_state(pdev, state));
2900 }
2901
2902 static int myri10ge_resume(struct pci_dev *pdev)
2903 {
2904 struct myri10ge_priv *mgp;
2905 struct net_device *netdev;
2906 int status;
2907 u16 vendor;
2908
2909 mgp = pci_get_drvdata(pdev);
2910 if (mgp == NULL)
2911 return -EINVAL;
2912 netdev = mgp->dev;
2913 pci_set_power_state(pdev, 0); /* zeros conf space as a side effect */
2914 msleep(5); /* give card time to respond */
2915 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
2916 if (vendor == 0xffff) {
2917 printk(KERN_ERR "myri10ge: %s: device disappeared!\n",
2918 mgp->dev->name);
2919 return -EIO;
2920 }
2921
2922 status = pci_restore_state(pdev);
2923 if (status)
2924 return status;
2925
2926 status = pci_enable_device(pdev);
2927 if (status) {
2928 dev_err(&pdev->dev, "failed to enable device\n");
2929 return status;
2930 }
2931
2932 pci_set_master(pdev);
2933
2934 myri10ge_reset(mgp);
2935 myri10ge_dummy_rdma(mgp, 1);
2936
2937 /* Save configuration space to be restored if the
2938 * nic resets due to a parity error */
2939 pci_save_state(pdev);
2940
2941 if (netif_running(netdev)) {
2942 rtnl_lock();
2943 status = myri10ge_open(netdev);
2944 rtnl_unlock();
2945 if (status != 0)
2946 goto abort_with_enabled;
2947
2948 }
2949 netif_device_attach(netdev);
2950
2951 return 0;
2952
2953 abort_with_enabled:
2954 pci_disable_device(pdev);
2955 return -EIO;
2956
2957 }
2958 #endif /* CONFIG_PM */
2959
2960 static u32 myri10ge_read_reboot(struct myri10ge_priv *mgp)
2961 {
2962 struct pci_dev *pdev = mgp->pdev;
2963 int vs = mgp->vendor_specific_offset;
2964 u32 reboot;
2965
2966 /*enter read32 mode */
2967 pci_write_config_byte(pdev, vs + 0x10, 0x3);
2968
2969 /*read REBOOT_STATUS (0xfffffff0) */
2970 pci_write_config_dword(pdev, vs + 0x18, 0xfffffff0);
2971 pci_read_config_dword(pdev, vs + 0x14, &reboot);
2972 return reboot;
2973 }
2974
2975 /*
2976 * This watchdog is used to check whether the board has suffered
2977 * from a parity error and needs to be recovered.
2978 */
2979 static void myri10ge_watchdog(struct work_struct *work)
2980 {
2981 struct myri10ge_priv *mgp =
2982 container_of(work, struct myri10ge_priv, watchdog_work);
2983 struct myri10ge_tx_buf *tx;
2984 u32 reboot;
2985 int status;
2986 u16 cmd, vendor;
2987
2988 mgp->watchdog_resets++;
2989 pci_read_config_word(mgp->pdev, PCI_COMMAND, &cmd);
2990 if ((cmd & PCI_COMMAND_MASTER) == 0) {
2991 /* Bus master DMA disabled? Check to see
2992 * if the card rebooted due to a parity error
2993 * For now, just report it */
2994 reboot = myri10ge_read_reboot(mgp);
2995 printk(KERN_ERR
2996 "myri10ge: %s: NIC rebooted (0x%x),%s resetting\n",
2997 mgp->dev->name, reboot,
2998 myri10ge_reset_recover ? " " : " not");
2999 if (myri10ge_reset_recover == 0)
3000 return;
3001
3002 myri10ge_reset_recover--;
3003
3004 /*
3005 * A rebooted nic will come back with config space as
3006 * it was after power was applied to PCIe bus.
3007 * Attempt to restore config space which was saved
3008 * when the driver was loaded, or the last time the
3009 * nic was resumed from power saving mode.
3010 */
3011 pci_restore_state(mgp->pdev);
3012
3013 /* save state again for accounting reasons */
3014 pci_save_state(mgp->pdev);
3015
3016 } else {
3017 /* if we get back -1's from our slot, perhaps somebody
3018 * powered off our card. Don't try to reset it in
3019 * this case */
3020 if (cmd == 0xffff) {
3021 pci_read_config_word(mgp->pdev, PCI_VENDOR_ID, &vendor);
3022 if (vendor == 0xffff) {
3023 printk(KERN_ERR
3024 "myri10ge: %s: device disappeared!\n",
3025 mgp->dev->name);
3026 return;
3027 }
3028 }
3029 /* Perhaps it is a software error. Try to reset */
3030
3031 printk(KERN_ERR "myri10ge: %s: device timeout, resetting\n",
3032 mgp->dev->name);
3033 tx = &mgp->ss.tx;
3034 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
3035 mgp->dev->name, tx->req, tx->done,
3036 tx->pkt_start, tx->pkt_done,
3037 (int)ntohl(mgp->ss.fw_stats->send_done_count));
3038 msleep(2000);
3039 printk(KERN_INFO "myri10ge: %s: %d %d %d %d %d\n",
3040 mgp->dev->name, tx->req, tx->done,
3041 tx->pkt_start, tx->pkt_done,
3042 (int)ntohl(mgp->ss.fw_stats->send_done_count));
3043 }
3044 rtnl_lock();
3045 myri10ge_close(mgp->dev);
3046 status = myri10ge_load_firmware(mgp);
3047 if (status != 0)
3048 printk(KERN_ERR "myri10ge: %s: failed to load firmware\n",
3049 mgp->dev->name);
3050 else
3051 myri10ge_open(mgp->dev);
3052 rtnl_unlock();
3053 }
3054
3055 /*
3056 * We use our own timer routine rather than relying upon
3057 * netdev->tx_timeout because we have a very large hardware transmit
3058 * queue. Due to the large queue, the netdev->tx_timeout function
3059 * cannot detect a NIC with a parity error in a timely fashion if the
3060 * NIC is lightly loaded.
3061 */
3062 static void myri10ge_watchdog_timer(unsigned long arg)
3063 {
3064 struct myri10ge_priv *mgp;
3065 struct myri10ge_slice_state *ss;
3066 u32 rx_pause_cnt;
3067
3068 mgp = (struct myri10ge_priv *)arg;
3069
3070 rx_pause_cnt = ntohl(mgp->ss.fw_stats->dropped_pause);
3071
3072 ss = &mgp->ss;
3073 if (ss->rx_small.watchdog_needed) {
3074 myri10ge_alloc_rx_pages(mgp, &ss->rx_small,
3075 mgp->small_bytes + MXGEFW_PAD, 1);
3076 if (ss->rx_small.fill_cnt - ss->rx_small.cnt >=
3077 myri10ge_fill_thresh)
3078 ss->rx_small.watchdog_needed = 0;
3079 }
3080 if (ss->rx_big.watchdog_needed) {
3081 myri10ge_alloc_rx_pages(mgp, &ss->rx_big, mgp->big_bytes, 1);
3082 if (ss->rx_big.fill_cnt - ss->rx_big.cnt >=
3083 myri10ge_fill_thresh)
3084 ss->rx_big.watchdog_needed = 0;
3085 }
3086
3087 if (ss->tx.req != ss->tx.done &&
3088 ss->tx.done == ss->watchdog_tx_done &&
3089 ss->watchdog_tx_req != ss->watchdog_tx_done) {
3090 /* nic seems like it might be stuck.. */
3091 if (rx_pause_cnt != mgp->watchdog_pause) {
3092 if (net_ratelimit())
3093 printk(KERN_WARNING "myri10ge %s:"
3094 "TX paused, check link partner\n",
3095 mgp->dev->name);
3096 } else {
3097 schedule_work(&mgp->watchdog_work);
3098 return;
3099 }
3100 }
3101 /* rearm timer */
3102 mod_timer(&mgp->watchdog_timer,
3103 jiffies + myri10ge_watchdog_timeout * HZ);
3104 ss->watchdog_tx_done = ss->tx.done;
3105 ss->watchdog_tx_req = ss->tx.req;
3106 mgp->watchdog_pause = rx_pause_cnt;
3107 }
3108
3109 static int myri10ge_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3110 {
3111 struct net_device *netdev;
3112 struct myri10ge_priv *mgp;
3113 struct device *dev = &pdev->dev;
3114 size_t bytes;
3115 int i;
3116 int status = -ENXIO;
3117 int dac_enabled;
3118
3119 netdev = alloc_etherdev(sizeof(*mgp));
3120 if (netdev == NULL) {
3121 dev_err(dev, "Could not allocate ethernet device\n");
3122 return -ENOMEM;
3123 }
3124
3125 SET_NETDEV_DEV(netdev, &pdev->dev);
3126
3127 mgp = netdev_priv(netdev);
3128 mgp->dev = netdev;
3129 netif_napi_add(netdev, &mgp->ss.napi, myri10ge_poll, myri10ge_napi_weight);
3130 mgp->pdev = pdev;
3131 mgp->csum_flag = MXGEFW_FLAGS_CKSUM;
3132 mgp->pause = myri10ge_flow_control;
3133 mgp->intr_coal_delay = myri10ge_intr_coal_delay;
3134 mgp->msg_enable = netif_msg_init(myri10ge_debug, MYRI10GE_MSG_DEFAULT);
3135 init_waitqueue_head(&mgp->down_wq);
3136
3137 if (pci_enable_device(pdev)) {
3138 dev_err(&pdev->dev, "pci_enable_device call failed\n");
3139 status = -ENODEV;
3140 goto abort_with_netdev;
3141 }
3142
3143 /* Find the vendor-specific cap so we can check
3144 * the reboot register later on */
3145 mgp->vendor_specific_offset
3146 = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
3147
3148 /* Set our max read request to 4KB */
3149 status = pcie_set_readrq(pdev, 4096);
3150 if (status != 0) {
3151 dev_err(&pdev->dev, "Error %d writing PCI_EXP_DEVCTL\n",
3152 status);
3153 goto abort_with_netdev;
3154 }
3155
3156 pci_set_master(pdev);
3157 dac_enabled = 1;
3158 status = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
3159 if (status != 0) {
3160 dac_enabled = 0;
3161 dev_err(&pdev->dev,
3162 "64-bit pci address mask was refused, "
3163 "trying 32-bit\n");
3164 status = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3165 }
3166 if (status != 0) {
3167 dev_err(&pdev->dev, "Error %d setting DMA mask\n", status);
3168 goto abort_with_netdev;
3169 }
3170 mgp->cmd = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->cmd),
3171 &mgp->cmd_bus, GFP_KERNEL);
3172 if (mgp->cmd == NULL)
3173 goto abort_with_netdev;
3174
3175 mgp->ss.fw_stats = dma_alloc_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3176 &mgp->ss.fw_stats_bus, GFP_KERNEL);
3177 if (mgp->ss.fw_stats == NULL)
3178 goto abort_with_cmd;
3179
3180 mgp->board_span = pci_resource_len(pdev, 0);
3181 mgp->iomem_base = pci_resource_start(pdev, 0);
3182 mgp->mtrr = -1;
3183 mgp->wc_enabled = 0;
3184 #ifdef CONFIG_MTRR
3185 mgp->mtrr = mtrr_add(mgp->iomem_base, mgp->board_span,
3186 MTRR_TYPE_WRCOMB, 1);
3187 if (mgp->mtrr >= 0)
3188 mgp->wc_enabled = 1;
3189 #endif
3190 /* Hack. need to get rid of these magic numbers */
3191 mgp->sram_size =
3192 2 * 1024 * 1024 - (2 * (48 * 1024) + (32 * 1024)) - 0x100;
3193 if (mgp->sram_size > mgp->board_span) {
3194 dev_err(&pdev->dev, "board span %ld bytes too small\n",
3195 mgp->board_span);
3196 goto abort_with_wc;
3197 }
3198 mgp->sram = ioremap(mgp->iomem_base, mgp->board_span);
3199 if (mgp->sram == NULL) {
3200 dev_err(&pdev->dev, "ioremap failed for %ld bytes at 0x%lx\n",
3201 mgp->board_span, mgp->iomem_base);
3202 status = -ENXIO;
3203 goto abort_with_wc;
3204 }
3205 memcpy_fromio(mgp->eeprom_strings,
3206 mgp->sram + mgp->sram_size - MYRI10GE_EEPROM_STRINGS_SIZE,
3207 MYRI10GE_EEPROM_STRINGS_SIZE);
3208 memset(mgp->eeprom_strings + MYRI10GE_EEPROM_STRINGS_SIZE - 2, 0, 2);
3209 status = myri10ge_read_mac_addr(mgp);
3210 if (status)
3211 goto abort_with_ioremap;
3212
3213 for (i = 0; i < ETH_ALEN; i++)
3214 netdev->dev_addr[i] = mgp->mac_addr[i];
3215
3216 /* allocate rx done ring */
3217 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3218 mgp->ss.rx_done.entry = dma_alloc_coherent(&pdev->dev, bytes,
3219 &mgp->ss.rx_done.bus, GFP_KERNEL);
3220 if (mgp->ss.rx_done.entry == NULL)
3221 goto abort_with_ioremap;
3222 memset(mgp->ss.rx_done.entry, 0, bytes);
3223
3224 myri10ge_select_firmware(mgp);
3225
3226 status = myri10ge_load_firmware(mgp);
3227 if (status != 0) {
3228 dev_err(&pdev->dev, "failed to load firmware\n");
3229 goto abort_with_rx_done;
3230 }
3231
3232 status = myri10ge_reset(mgp);
3233 if (status != 0) {
3234 dev_err(&pdev->dev, "failed reset\n");
3235 goto abort_with_firmware;
3236 }
3237
3238 pci_set_drvdata(pdev, mgp);
3239 if ((myri10ge_initial_mtu + ETH_HLEN) > MYRI10GE_MAX_ETHER_MTU)
3240 myri10ge_initial_mtu = MYRI10GE_MAX_ETHER_MTU - ETH_HLEN;
3241 if ((myri10ge_initial_mtu + ETH_HLEN) < 68)
3242 myri10ge_initial_mtu = 68;
3243 netdev->mtu = myri10ge_initial_mtu;
3244 netdev->open = myri10ge_open;
3245 netdev->stop = myri10ge_close;
3246 netdev->hard_start_xmit = myri10ge_xmit;
3247 netdev->get_stats = myri10ge_get_stats;
3248 netdev->base_addr = mgp->iomem_base;
3249 netdev->change_mtu = myri10ge_change_mtu;
3250 netdev->set_multicast_list = myri10ge_set_multicast_list;
3251 netdev->set_mac_address = myri10ge_set_mac_address;
3252 netdev->features = mgp->features;
3253 if (dac_enabled)
3254 netdev->features |= NETIF_F_HIGHDMA;
3255
3256 /* make sure we can get an irq, and that MSI can be
3257 * setup (if available). Also ensure netdev->irq
3258 * is set to correct value if MSI is enabled */
3259 status = myri10ge_request_irq(mgp);
3260 if (status != 0)
3261 goto abort_with_firmware;
3262 netdev->irq = pdev->irq;
3263 myri10ge_free_irq(mgp);
3264
3265 /* Save configuration space to be restored if the
3266 * nic resets due to a parity error */
3267 pci_save_state(pdev);
3268
3269 /* Setup the watchdog timer */
3270 setup_timer(&mgp->watchdog_timer, myri10ge_watchdog_timer,
3271 (unsigned long)mgp);
3272
3273 SET_ETHTOOL_OPS(netdev, &myri10ge_ethtool_ops);
3274 INIT_WORK(&mgp->watchdog_work, myri10ge_watchdog);
3275 status = register_netdev(netdev);
3276 if (status != 0) {
3277 dev_err(&pdev->dev, "register_netdev failed: %d\n", status);
3278 goto abort_with_state;
3279 }
3280 dev_info(dev, "%s IRQ %d, tx bndry %d, fw %s, WC %s\n",
3281 (mgp->msi_enabled ? "MSI" : "xPIC"),
3282 netdev->irq, mgp->tx_boundary, mgp->fw_name,
3283 (mgp->wc_enabled ? "Enabled" : "Disabled"));
3284
3285 return 0;
3286
3287 abort_with_state:
3288 pci_restore_state(pdev);
3289
3290 abort_with_firmware:
3291 myri10ge_dummy_rdma(mgp, 0);
3292
3293 abort_with_rx_done:
3294 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3295 dma_free_coherent(&pdev->dev, bytes,
3296 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3297
3298 abort_with_ioremap:
3299 iounmap(mgp->sram);
3300
3301 abort_with_wc:
3302 #ifdef CONFIG_MTRR
3303 if (mgp->mtrr >= 0)
3304 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3305 #endif
3306 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3307 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3308
3309 abort_with_cmd:
3310 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3311 mgp->cmd, mgp->cmd_bus);
3312
3313 abort_with_netdev:
3314
3315 free_netdev(netdev);
3316 return status;
3317 }
3318
3319 /*
3320 * myri10ge_remove
3321 *
3322 * Does what is necessary to shutdown one Myrinet device. Called
3323 * once for each Myrinet card by the kernel when a module is
3324 * unloaded.
3325 */
3326 static void myri10ge_remove(struct pci_dev *pdev)
3327 {
3328 struct myri10ge_priv *mgp;
3329 struct net_device *netdev;
3330 size_t bytes;
3331
3332 mgp = pci_get_drvdata(pdev);
3333 if (mgp == NULL)
3334 return;
3335
3336 flush_scheduled_work();
3337 netdev = mgp->dev;
3338 unregister_netdev(netdev);
3339
3340 myri10ge_dummy_rdma(mgp, 0);
3341
3342 /* avoid a memory leak */
3343 pci_restore_state(pdev);
3344
3345 bytes = mgp->max_intr_slots * sizeof(*mgp->ss.rx_done.entry);
3346 dma_free_coherent(&pdev->dev, bytes,
3347 mgp->ss.rx_done.entry, mgp->ss.rx_done.bus);
3348
3349 iounmap(mgp->sram);
3350
3351 #ifdef CONFIG_MTRR
3352 if (mgp->mtrr >= 0)
3353 mtrr_del(mgp->mtrr, mgp->iomem_base, mgp->board_span);
3354 #endif
3355 dma_free_coherent(&pdev->dev, sizeof(*mgp->ss.fw_stats),
3356 mgp->ss.fw_stats, mgp->ss.fw_stats_bus);
3357
3358 dma_free_coherent(&pdev->dev, sizeof(*mgp->cmd),
3359 mgp->cmd, mgp->cmd_bus);
3360
3361 free_netdev(netdev);
3362 pci_set_drvdata(pdev, NULL);
3363 }
3364
3365 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E 0x0008
3366 #define PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9 0x0009
3367
3368 static struct pci_device_id myri10ge_pci_tbl[] = {
3369 {PCI_DEVICE(PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E)},
3370 {PCI_DEVICE
3371 (PCI_VENDOR_ID_MYRICOM, PCI_DEVICE_ID_MYRICOM_MYRI10GE_Z8E_9)},
3372 {0},
3373 };
3374
3375 static struct pci_driver myri10ge_driver = {
3376 .name = "myri10ge",
3377 .probe = myri10ge_probe,
3378 .remove = myri10ge_remove,
3379 .id_table = myri10ge_pci_tbl,
3380 #ifdef CONFIG_PM
3381 .suspend = myri10ge_suspend,
3382 .resume = myri10ge_resume,
3383 #endif
3384 };
3385
3386 static __init int myri10ge_init_module(void)
3387 {
3388 printk(KERN_INFO "%s: Version %s\n", myri10ge_driver.name,
3389 MYRI10GE_VERSION_STR);
3390 return pci_register_driver(&myri10ge_driver);
3391 }
3392
3393 module_init(myri10ge_init_module);
3394
3395 static __exit void myri10ge_cleanup_module(void)
3396 {
3397 pci_unregister_driver(&myri10ge_driver);
3398 }
3399
3400 module_exit(myri10ge_cleanup_module);
Linux for Ginger Game Console