arch/mips/include/asm/mach-pb1x00/pb1550.h

   1 /*
   2  * AMD Alchemy Semi PB1550 Referrence Board
   3  * Board Registers defines.
   4  *
   5  * Copyright 2004 Embedded Edge LLC.
   6  * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
   7  *
   8  * ########################################################################
   9  *
  10  *  This program is free software; you can distribute it and/or modify it
  11  *  under the terms of the GNU General Public License (Version 2) as
  12  *  published by the Free Software Foundation.
  13  *
  14  *  This program is distributed in the hope it will be useful, but WITHOUT
  15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  17  *  for more details.
  18  *
  19  *  You should have received a copy of the GNU General Public License along
  20  *  with this program; if not, write to the Free Software Foundation, Inc.,
  21  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  22  *
  23  * ########################################################################
  24  *
  25  *
  26  */
  27 #ifndef __ASM_PB1550_H
  28 #define __ASM_PB1550_H
  29
  30 #include <linux/types.h>
  31 #include <asm/mach-au1x00/au1xxx_psc.h>
  32
  33 #define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
  34 #define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
  35 #define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
  36 #define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
  37
  38 #define SPI_PSC_BASE            PSC0_BASE_ADDR
  39 #define AC97_PSC_BASE           PSC1_BASE_ADDR
  40 #define SMBUS_PSC_BASE          PSC2_BASE_ADDR
  41 #define I2S_PSC_BASE            PSC3_BASE_ADDR
  42
  43 #define BCSR_PHYS_ADDR 0xAF000000
  44
  45 typedef volatile struct
  46 {
  47         /*00*/  u16 whoami;
  48                 u16 reserved0;
  49         /*04*/  u16 status;
  50                 u16 reserved1;
  51         /*08*/  u16 switches;
  52                 u16 reserved2;
  53         /*0C*/  u16 resets;
  54                 u16 reserved3;
  55         /*10*/  u16 pcmcia;
  56                 u16 reserved4;
  57         /*14*/  u16 pci;
  58                 u16 reserved5;
  59         /*18*/  u16 leds;
  60                 u16 reserved6;
  61         /*1C*/  u16 system;
  62                 u16 reserved7;
  63
  64 } BCSR;
  65
  66 static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
  67
  68 /*
  69  * Register bit definitions for the BCSRs
  70  */
  71 #define BCSR_WHOAMI_DCID        0x000F
  72 #define BCSR_WHOAMI_CPLD        0x00F0
  73 #define BCSR_WHOAMI_BOARD       0x0F00
  74
  75 #define BCSR_STATUS_PCMCIA0VS   0x0003
  76 #define BCSR_STATUS_PCMCIA1VS   0x000C
  77 #define BCSR_STATUS_PCMCIA0FI   0x0010
  78 #define BCSR_STATUS_PCMCIA1FI   0x0020
  79 #define BCSR_STATUS_SWAPBOOT    0x0040
  80 #define BCSR_STATUS_SRAMWIDTH   0x0080
  81 #define BCSR_STATUS_FLASHBUSY   0x0100
  82 #define BCSR_STATUS_ROMBUSY     0x0200
  83 #define BCSR_STATUS_USBOTGID    0x0800
  84 #define BCSR_STATUS_U0RXD       0x1000
  85 #define BCSR_STATUS_U1RXD       0x2000
  86 #define BCSR_STATUS_U3RXD       0x8000
  87
  88 #define BCSR_SWITCHES_OCTAL     0x00FF
  89 #define BCSR_SWITCHES_DIP_1     0x0080
  90 #define BCSR_SWITCHES_DIP_2     0x0040
  91 #define BCSR_SWITCHES_DIP_3     0x0020
  92 #define BCSR_SWITCHES_DIP_4     0x0010
  93 #define BCSR_SWITCHES_DIP_5     0x0008
  94 #define BCSR_SWITCHES_DIP_6     0x0004
  95 #define BCSR_SWITCHES_DIP_7     0x0002
  96 #define BCSR_SWITCHES_DIP_8     0x0001
  97 #define BCSR_SWITCHES_ROTARY    0x0F00
  98
  99 #define BCSR_RESETS_PHY0        0x0001
 100 #define BCSR_RESETS_PHY1        0x0002
 101 #define BCSR_RESETS_DC          0x0004
 102 #define BCSR_RESETS_WSC         0x2000
 103 #define BCSR_RESETS_SPISEL      0x4000
 104 #define BCSR_RESETS_DMAREQ      0x8000
 105
 106 #define BCSR_PCMCIA_PC0VPP      0x0003
 107 #define BCSR_PCMCIA_PC0VCC      0x000C
 108 #define BCSR_PCMCIA_PC0DRVEN    0x0010
 109 #define BCSR_PCMCIA_PC0RST      0x0080
 110 #define BCSR_PCMCIA_PC1VPP      0x0300
 111 #define BCSR_PCMCIA_PC1VCC      0x0C00
 112 #define BCSR_PCMCIA_PC1DRVEN    0x1000
 113 #define BCSR_PCMCIA_PC1RST      0x8000
 114
 115 #define BCSR_PCI_M66EN          0x0001
 116 #define BCSR_PCI_M33            0x0100
 117 #define BCSR_PCI_EXTERNARB      0x0200
 118 #define BCSR_PCI_GPIO200RST     0x0400
 119 #define BCSR_PCI_CLKOUT         0x0800
 120 #define BCSR_PCI_CFGHOST        0x1000
 121
 122 #define BCSR_LEDS_DECIMALS      0x00FF
 123 #define BCSR_LEDS_LED0          0x0100
 124 #define BCSR_LEDS_LED1          0x0200
 125 #define BCSR_LEDS_LED2          0x0400
 126 #define BCSR_LEDS_LED3          0x0800
 127
 128 #define BCSR_SYSTEM_VDDI        0x001F
 129 #define BCSR_SYSTEM_POWEROFF    0x4000
 130 #define BCSR_SYSTEM_RESET       0x8000
 131
 132 #define PCMCIA_MAX_SOCK  1
 133 #define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
 134
 135 /* VPP/VCC */
 136 #define SET_VCC_VPP(VCC, VPP, SLOT) \
 137         ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
 138
 139 #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
 140 #define PB1550_BOTH_BANKS
 141 #elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
 142 #define PB1550_BOOT_ONLY
 143 #elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
 144 #define PB1550_USER_ONLY
 145 #endif
 146
 147 /*
 148  * Timing values as described in databook, * ns value stripped of
 149  * lower 2 bits.
 150  * These defines are here rather than an SOC1550 generic file because
 151  * the parts chosen on another board may be different and may require
 152  * different timings.
 153  */
 154 #define NAND_T_H                (18 >> 2)
 155 #define NAND_T_PUL              (30 >> 2)
 156 #define NAND_T_SU               (30 >> 2)
 157 #define NAND_T_WH               (30 >> 2)
 158
 159 /* Bitfield shift amounts */
 160 #define NAND_T_H_SHIFT          0
 161 #define NAND_T_PUL_SHIFT        4
 162 #define NAND_T_SU_SHIFT         8
 163 #define NAND_T_WH_SHIFT         12
 164
 165 #define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
 166                          ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
 167                          ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
 168                          ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
 169
 170 #define NAND_CS 1
 171
 172 /* Should be done by YAMON */
 173 #define NAND_STCFG      0x00400005 /* 8-bit NAND */
 174 #define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
 175 #define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
 176
 177 #endif /* __ASM_PB1550_H */