arch/mips/txx9/generic/irq_tx4939.c

   1 /*
   2  * TX4939 irq routines
   3  * Based on linux/arch/mips/kernel/irq_txx9.c,
   4  *          and RBTX49xx patch from CELF patch archive.
   5  *
   6  * Copyright 2001, 2003-2005 MontaVista Software Inc.
   7  * Author: MontaVista Software, Inc.
   8  *         ahennessy@mvista.com
   9  *         source@mvista.com
  10  * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file "COPYING" in the main directory of this archive
  14  * for more details.
  15  */
  16 /*
  17  * TX4939 defines 64 IRQs.
  18  * Similer to irq_txx9.c but different register layouts.
  19  */
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/types.h>
  23 #include <asm/irq_cpu.h>
  24 #include <asm/txx9irq.h>
  25 #include <asm/txx9/tx4939.h>
  26
  27 /* IRCER : Int. Control Enable */
  28 #define TXx9_IRCER_ICE  0x00000001
  29
  30 /* IRCR : Int. Control */
  31 #define TXx9_IRCR_LOW   0x00000000
  32 #define TXx9_IRCR_HIGH  0x00000001
  33 #define TXx9_IRCR_DOWN  0x00000002
  34 #define TXx9_IRCR_UP    0x00000003
  35 #define TXx9_IRCR_EDGE(cr)      ((cr) & 0x00000002)
  36
  37 /* IRSCR : Int. Status Control */
  38 #define TXx9_IRSCR_EIClrE       0x00000100
  39 #define TXx9_IRSCR_EIClr_MASK   0x0000000f
  40
  41 /* IRCSR : Int. Current Status */
  42 #define TXx9_IRCSR_IF   0x00010000
  43
  44 #define irc_dlevel      0
  45 #define irc_elevel      1
  46
  47 static struct {
  48         unsigned char level;
  49         unsigned char mode;
  50 } tx4939irq[TX4939_NUM_IR] __read_mostly;
  51
  52 static void tx4939_irq_unmask(unsigned int irq)
  53 {
  54         unsigned int irq_nr = irq - TXX9_IRQ_BASE;
  55         u32 __iomem *lvlp;
  56         int ofs;
  57         if (irq_nr < 32) {
  58                 irq_nr--;
  59                 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
  60         } else {
  61                 irq_nr -= 32;
  62                 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
  63         }
  64         ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
  65         __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
  66                      | (tx4939irq[irq_nr].level << ofs),
  67                      lvlp);
  68 }
  69
  70 static inline void tx4939_irq_mask(unsigned int irq)
  71 {
  72         unsigned int irq_nr = irq - TXX9_IRQ_BASE;
  73         u32 __iomem *lvlp;
  74         int ofs;
  75         if (irq_nr < 32) {
  76                 irq_nr--;
  77                 lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
  78         } else {
  79                 irq_nr -= 32;
  80                 lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
  81         }
  82         ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
  83         __raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
  84                      | (irc_dlevel << ofs),
  85                      lvlp);
  86         mmiowb();
  87 }
  88
  89 static void tx4939_irq_mask_ack(unsigned int irq)
  90 {
  91         unsigned int irq_nr = irq - TXX9_IRQ_BASE;
  92
  93         tx4939_irq_mask(irq);
  94         if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
  95                 irq_nr--;
  96                 /* clear edge detection */
  97                 __raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
  98                              << (irq_nr & 0x10),
  99                              &tx4939_ircptr->edc.r);
 100         }
 101 }
 102
 103 static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
 104 {
 105         unsigned int irq_nr = irq - TXX9_IRQ_BASE;
 106         u32 cr;
 107         u32 __iomem *crp;
 108         int ofs;
 109         int mode;
 110
 111         if (flow_type & IRQF_TRIGGER_PROBE)
 112                 return 0;
 113         switch (flow_type & IRQF_TRIGGER_MASK) {
 114         case IRQF_TRIGGER_RISING:
 115                 mode = TXx9_IRCR_UP;
 116                 break;
 117         case IRQF_TRIGGER_FALLING:
 118                 mode = TXx9_IRCR_DOWN;
 119                 break;
 120         case IRQF_TRIGGER_HIGH:
 121                 mode = TXx9_IRCR_HIGH;
 122                 break;
 123         case IRQF_TRIGGER_LOW:
 124                 mode = TXx9_IRCR_LOW;
 125                 break;
 126         default:
 127                 return -EINVAL;
 128         }
 129         if (irq_nr < 32) {
 130                 irq_nr--;
 131                 crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
 132         } else {
 133                 irq_nr -= 32;
 134                 crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
 135         }
 136         ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
 137         cr = __raw_readl(crp);
 138         cr &= ~(0x3 << ofs);
 139         cr |= (mode & 0x3) << ofs;
 140         __raw_writel(cr, crp);
 141         tx4939irq[irq_nr].mode = mode;
 142         return 0;
 143 }
 144
 145 static struct irq_chip tx4939_irq_chip = {
 146         .name           = "TX4939",
 147         .ack            = tx4939_irq_mask_ack,
 148         .mask           = tx4939_irq_mask,
 149         .mask_ack       = tx4939_irq_mask_ack,
 150         .unmask         = tx4939_irq_unmask,
 151         .set_type       = tx4939_irq_set_type,
 152 };
 153
 154 static int tx4939_irq_set_pri(int irc_irq, int new_pri)
 155 {
 156         int old_pri;
 157
 158         if ((unsigned int)irc_irq >= TX4939_NUM_IR)
 159                 return 0;
 160         old_pri = tx4939irq[irc_irq].level;
 161         tx4939irq[irc_irq].level = new_pri;
 162         return old_pri;
 163 }
 164
 165 void __init tx4939_irq_init(void)
 166 {
 167         int i;
 168
 169         mips_cpu_irq_init();
 170         /* disable interrupt control */
 171         __raw_writel(0, &tx4939_ircptr->den.r);
 172         __raw_writel(0, &tx4939_ircptr->maskint.r);
 173         __raw_writel(0, &tx4939_ircptr->maskext.r);
 174         /* irq_base + 0 is not used */
 175         for (i = 1; i < TX4939_NUM_IR; i++) {
 176                 tx4939irq[i].level = 4; /* middle level */
 177                 tx4939irq[i].mode = TXx9_IRCR_LOW;
 178                 set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
 179                                          &tx4939_irq_chip, handle_level_irq);
 180         }
 181
 182         /* mask all IRC interrupts */
 183         __raw_writel(0, &tx4939_ircptr->msk.r);
 184         for (i = 0; i < 16; i++)
 185                 __raw_writel(0, &tx4939_ircptr->lvl[i].r);
 186         /* setup IRC interrupt mode (Low Active) */
 187         for (i = 0; i < 2; i++)
 188                 __raw_writel(0, &tx4939_ircptr->dm[i].r);
 189         for (i = 0; i < 2; i++)
 190                 __raw_writel(0, &tx4939_ircptr->dm2[i].r);
 191         /* enable interrupt control */
 192         __raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
 193         __raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
 194
 195         set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
 196                                 handle_simple_irq);
 197
 198         /* raise priority for errors, timers, sio */
 199         tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
 200         tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
 201         tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
 202         for (i = 0; i < TX4939_NUM_IR_TMR; i++)
 203                 tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
 204         for (i = 0; i < TX4939_NUM_IR_SIO; i++)
 205                 tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
 206 }
 207
 208 int tx4939_irq(void)
 209 {
 210         u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
 211
 212         if (likely(!(csr & TXx9_IRCSR_IF)))
 213                 return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
 214         return -1;
 215 }