OMAP3 SRF: Add virt clk nodes for VDD1/VDD2
[linux-ginger.git] / arch / sh / include / asm / clock.h
blob9fe7d7f8af404646dfcce651d53727f69fc91653
1 #ifndef __ASM_SH_CLOCK_H
2 #define __ASM_SH_CLOCK_H
4 #include <linux/list.h>
5 #include <linux/seq_file.h>
6 #include <linux/cpufreq.h>
7 #include <linux/clk.h>
8 #include <linux/err.h>
10 struct clk;
12 struct clk_ops {
13 void (*init)(struct clk *clk);
14 int (*enable)(struct clk *clk);
15 void (*disable)(struct clk *clk);
16 unsigned long (*recalc)(struct clk *clk);
17 int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
18 int (*set_parent)(struct clk *clk, struct clk *parent);
19 long (*round_rate)(struct clk *clk, unsigned long rate);
22 struct clk {
23 struct list_head node;
24 const char *name;
25 int id;
26 struct module *owner;
28 struct clk *parent;
29 struct clk_ops *ops;
31 struct list_head children;
32 struct list_head sibling; /* node for children */
34 int usecount;
36 unsigned long rate;
37 unsigned long flags;
39 void __iomem *enable_reg;
40 unsigned int enable_bit;
42 unsigned long arch_flags;
43 void *priv;
44 struct dentry *dentry;
45 struct cpufreq_frequency_table *freq_table;
48 struct clk_lookup {
49 struct list_head node;
50 const char *dev_id;
51 const char *con_id;
52 struct clk *clk;
55 #define CLK_ENABLE_ON_INIT (1 << 0)
57 /* Should be defined by processor-specific code */
58 void __deprecated arch_init_clk_ops(struct clk_ops **, int type);
59 int __init arch_clk_init(void);
61 /* arch/sh/kernel/cpu/clock.c */
62 int clk_init(void);
63 unsigned long followparent_recalc(struct clk *);
64 void recalculate_root_clocks(void);
65 void propagate_rate(struct clk *);
66 int clk_reparent(struct clk *child, struct clk *parent);
67 int clk_register(struct clk *);
68 void clk_unregister(struct clk *);
70 /* arch/sh/kernel/cpu/clock-cpg.c */
71 int __init __deprecated cpg_clk_init(void);
73 /* the exported API, in addition to clk_set_rate */
74 /**
75 * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
76 * @clk: clock source
77 * @rate: desired clock rate in Hz
78 * @algo_id: algorithm id to be passed down to ops->set_rate
80 * Returns success (0) or negative errno.
82 int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
84 enum clk_sh_algo_id {
85 NO_CHANGE = 0,
87 IUS_N1_N1,
88 IUS_322,
89 IUS_522,
90 IUS_N11,
92 SB_N1,
94 SB3_N1,
95 SB3_32,
96 SB3_43,
97 SB3_54,
99 BP_N1,
101 IP_N1,
104 struct clk_div_mult_table {
105 unsigned int *divisors;
106 unsigned int nr_divisors;
107 unsigned int *multipliers;
108 unsigned int nr_multipliers;
111 struct cpufreq_frequency_table;
112 void clk_rate_table_build(struct clk *clk,
113 struct cpufreq_frequency_table *freq_table,
114 int nr_freqs,
115 struct clk_div_mult_table *src_table,
116 unsigned long *bitmap);
118 long clk_rate_table_round(struct clk *clk,
119 struct cpufreq_frequency_table *freq_table,
120 unsigned long rate);
122 int clk_rate_table_find(struct clk *clk,
123 struct cpufreq_frequency_table *freq_table,
124 unsigned long rate);
126 #define SH_CLK_MSTP32(_name, _id, _parent, _enable_reg, \
127 _enable_bit, _flags) \
129 .name = _name, \
130 .id = _id, \
131 .parent = _parent, \
132 .enable_reg = (void __iomem *)_enable_reg, \
133 .enable_bit = _enable_bit, \
134 .flags = _flags, \
137 int sh_clk_mstp32_register(struct clk *clks, int nr);
139 #define SH_CLK_DIV4(_name, _parent, _reg, _shift, _div_bitmap, _flags) \
141 .name = _name, \
142 .parent = _parent, \
143 .enable_reg = (void __iomem *)_reg, \
144 .enable_bit = _shift, \
145 .arch_flags = _div_bitmap, \
146 .flags = _flags, \
149 int sh_clk_div4_register(struct clk *clks, int nr,
150 struct clk_div_mult_table *table);
152 #define SH_CLK_DIV6(_name, _parent, _reg, _flags) \
154 .name = _name, \
155 .parent = _parent, \
156 .enable_reg = (void __iomem *)_reg, \
157 .flags = _flags, \
160 int sh_clk_div6_register(struct clk *clks, int nr);
162 #endif /* __ASM_SH_CLOCK_H */