?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
OMAP3 SRF: Add virt clk nodes for VDD1/VDD2
[linux-ginger.git] / drivers / ide / amd74xx.c
blob628cd2e5fed83de28aab0b423f02adc15944e90d
1 /*
2 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04
3 * IDE driver for Linux.
4 *
5 * Copyright (c) 2000-2002 Vojtech Pavlik
6 * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz
7 *
8 * Based on the work of:
9 * Andre Hedrick
10 */
11
12 /*
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License version 2 as published by
15 * the Free Software Foundation.
16 */
17
18 #include <linux/module.h>
19 #include <linux/kernel.h>
20 #include <linux/pci.h>
21 #include <linux/init.h>
22 #include <linux/ide.h>
23
24 #define DRV_NAME "amd74xx"
25
26 enum {
27 AMD_IDE_CONFIG = 0x41,
28 AMD_CABLE_DETECT = 0x42,
29 AMD_DRIVE_TIMING = 0x48,
30 AMD_8BIT_TIMING = 0x4e,
31 AMD_ADDRESS_SETUP = 0x4c,
32 AMD_UDMA_TIMING = 0x50,
33 };
34
35 static unsigned int amd_80w;
36 static unsigned int amd_clock;
37
38 static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" };
39 static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 };
40
41 static inline u8 amd_offset(struct pci_dev *dev)
42 {
43 return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0;
44 }
45
46 /*
47 * amd_set_speed() writes timing values to the chipset registers
48 */
49
50 static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask,
51 struct ide_timing *timing)
52 {
53 u8 t = 0, offset = amd_offset(dev);
54
55 pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t);
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
57 pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t);
58
59 pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)),
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1));
61
62 pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn),
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1));
64
65 switch (udma_mask) {
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break;
67 case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break;
68 case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break;
69 case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break;
70 default: return;
71 }
72
73 pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + (3 - dn), t);
74 }
75
76 /*
77 * amd_set_drive() computes timing values and configures the chipset
78 * to a desired transfer mode. It also can be called by upper layers.
79 */
80
81 static void amd_set_drive(ide_drive_t *drive, const u8 speed)
82 {
83 ide_hwif_t *hwif = drive->hwif;
84 struct pci_dev *dev = to_pci_dev(hwif->dev);
85 ide_drive_t *peer = ide_get_pair_dev(drive);
86 struct ide_timing t, p;
87 int T, UT;
88 u8 udma_mask = hwif->ultra_mask;
89
90 T = 1000000000 / amd_clock;
91 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2);
92
93 ide_timing_compute(drive, speed, &t, T, UT);
94
95 if (peer) {
96 ide_timing_compute(peer, peer->current_speed, &p, T, UT);
97 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
98 }
99
100 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1;
101 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15;
102
103 amd_set_speed(dev, drive->dn, udma_mask, &t);
104 }
105
106 /*
107 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning.
108 */
109
110 static void amd_set_pio_mode(ide_drive_t *drive, const u8 pio)
111 {
112 amd_set_drive(drive, XFER_PIO_0 + pio);
113 }
114
115 static void amd7409_cable_detect(struct pci_dev *dev)
116 {
117 /* no host side cable detection */
118 amd_80w = 0x03;
119 }
120
121 static void amd7411_cable_detect(struct pci_dev *dev)
122 {
123 int i;
124 u32 u = 0;
125 u8 t = 0, offset = amd_offset(dev);
126
127 pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t);
128 pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u);
129 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0);
130 for (i = 24; i >= 0; i -= 8)
131 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) {
132 printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set "
133 "cable bits correctly. Enabling workaround.\n",
134 pci_name(dev));
135 amd_80w |= (1 << (1 - (i >> 4)));
136 }
137 }
138
139 /*
140 * The initialization callback. Initialize drive independent registers.
141 */
142
143 static int init_chipset_amd74xx(struct pci_dev *dev)
144 {
145 u8 t = 0, offset = amd_offset(dev);
146
147 /*
148 * Check 80-wire cable presence.
149 */
150
151 if (dev->vendor == PCI_VENDOR_ID_AMD &&
152 dev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
153 ; /* no UDMA > 2 */
154 else if (dev->vendor == PCI_VENDOR_ID_AMD &&
155 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409)
156 amd7409_cable_detect(dev);
157 else
158 amd7411_cable_detect(dev);
159
160 /*
161 * Take care of prefetch & postwrite.
162 */
163
164 pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t);
165 /*
166 * Check for broken FIFO support.
167 */
168 if (dev->vendor == PCI_VENDOR_ID_AMD &&
169 dev->device == PCI_DEVICE_ID_AMD_VIPER_7411)
170 t &= 0x0f;
171 else
172 t |= 0xf0;
173 pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t);
174
175 return 0;
176 }
177
178 static u8 amd_cable_detect(ide_hwif_t *hwif)
179 {
180 if ((amd_80w >> hwif->channel) & 1)
181 return ATA_CBL_PATA80;
182 else
183 return ATA_CBL_PATA40;
184 }
185
186 static const struct ide_port_ops amd_port_ops = {
187 .set_pio_mode = amd_set_pio_mode,
188 .set_dma_mode = amd_set_drive,
189 .cable_detect = amd_cable_detect,
190 };
191
192 #define IDE_HFLAGS_AMD \
193 (IDE_HFLAG_PIO_NO_BLACKLIST | \
194 IDE_HFLAG_POST_SET_MODE | \
195 IDE_HFLAG_IO_32BIT | \
196 IDE_HFLAG_UNMASK_IRQS)
197
198 #define DECLARE_AMD_DEV(swdma, udma) \
199 { \
200 .name = DRV_NAME, \
201 .init_chipset = init_chipset_amd74xx, \
202 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \
203 .port_ops = &amd_port_ops, \
204 .host_flags = IDE_HFLAGS_AMD, \
205 .pio_mask = ATA_PIO5, \
206 .swdma_mask = swdma, \
207 .mwdma_mask = ATA_MWDMA2, \
208 .udma_mask = udma, \
209 }
210
211 #define DECLARE_NV_DEV(udma) \
212 { \
213 .name = DRV_NAME, \
214 .init_chipset = init_chipset_amd74xx, \
215 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \
216 .port_ops = &amd_port_ops, \
217 .host_flags = IDE_HFLAGS_AMD, \
218 .pio_mask = ATA_PIO5, \
219 .swdma_mask = ATA_SWDMA2, \
220 .mwdma_mask = ATA_MWDMA2, \
221 .udma_mask = udma, \
222 }
223
224 static const struct ide_port_info amd74xx_chipsets[] __devinitdata = {
225 /* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2),
226 /* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4),
227 /* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
228 /* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6),
229
230 /* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5),
231 /* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6),
232
233 /* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5),
234 };
235
236 static int __devinit amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id)
237 {
238 struct ide_port_info d;
239 u8 idx = id->driver_data;
240
241 d = amd74xx_chipsets[idx];
242
243 /*
244 * Check for bad SWDMA and incorrectly wired Serenade mainboards.
245 */
246 if (idx == 1) {
247 if (dev->revision <= 7)
248 d.swdma_mask = 0;
249 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX;
250 } else if (idx == 3) {
251 if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
252 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
253 d.udma_mask = ATA_UDMA5;
254 }
255
256 /*
257 * It seems that on some nVidia controllers using AltStatus
258 * register can be unreliable so default to Status register
259 * if the device is in Compatibility Mode.
260 */
261 if (dev->vendor == PCI_VENDOR_ID_NVIDIA &&
262 ide_pci_is_in_compatibility_mode(dev))
263 d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS;
264
265 printk(KERN_INFO "%s %s: UDMA%s controller\n",
266 d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]);
267
268 /*
269 * Determine the system bus clock.
270 */
271 amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000;
272
273 switch (amd_clock) {
274 case 33000: amd_clock = 33333; break;
275 case 37000: amd_clock = 37500; break;
276 case 41000: amd_clock = 41666; break;
277 }
278
279 if (amd_clock < 20000 || amd_clock > 50000) {
280 printk(KERN_WARNING "%s: User given PCI clock speed impossible"
281 " (%d), using 33 MHz instead.\n",
282 d.name, amd_clock);
283 amd_clock = 33333;
284 }
285
286 return ide_pci_init_one(dev, &d, NULL);
287 }
288
289 static const struct pci_device_id amd74xx_pci_tbl[] = {
290 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
291 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
292 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 },
293 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 },
294 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 },
295 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 },
296 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 },
297 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 },
298 #ifdef CONFIG_BLK_DEV_IDE_SATA
299 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 },
300 #endif
301 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 },
302 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 },
303 #ifdef CONFIG_BLK_DEV_IDE_SATA
304 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 },
305 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 },
306 #endif
307 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 },
308 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 },
309 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 },
310 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 },
311 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 },
312 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 },
313 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 },
314 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 },
315 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 },
316 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 },
317 { 0, },
318 };
319 MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl);
320
321 static struct pci_driver amd74xx_pci_driver = {
322 .name = "AMD_IDE",
323 .id_table = amd74xx_pci_tbl,
324 .probe = amd74xx_probe,
325 .remove = ide_pci_remove,
326 .suspend = ide_pci_suspend,
327 .resume = ide_pci_resume,
328 };
329
330 static int __init amd74xx_ide_init(void)
331 {
332 return ide_pci_register_driver(&amd74xx_pci_driver);
333 }
334
335 static void __exit amd74xx_ide_exit(void)
336 {
337 pci_unregister_driver(&amd74xx_pci_driver);
338 }
339
340 module_init(amd74xx_ide_init);
341 module_exit(amd74xx_ide_exit);
342
343 MODULE_AUTHOR("Vojtech Pavlik");
344 MODULE_DESCRIPTION("AMD PCI IDE driver");
345 MODULE_LICENSE("GPL");
Linux for Ginger Game Console