omap: Introduce OMAP3630
[linux-ginger.git] / arch / arm / mach-omap2 / id.c
blob1c151122089056a55f3e471aa30907a592fa23d0
1 /*
2 * linux/arch/arm/mach-omap2/id.c
4 * OMAP2 CPU identification code
6 * Copyright (C) 2005 Nokia Corporation
7 * Written by Tony Lindgren <tony@atomide.com>
9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/module.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/io.h>
22 #include <asm/cputype.h>
24 #include <plat/common.h>
25 #include <plat/control.h>
26 #include <plat/cpu.h>
28 static struct omap_chip_id omap_chip;
29 static unsigned int omap_revision;
31 u32 omap3_features;
33 unsigned int omap_rev(void)
35 return omap_revision;
37 EXPORT_SYMBOL(omap_rev);
39 /**
40 * omap_chip_is - test whether currently running OMAP matches a chip type
41 * @oc: omap_chip_t to test against
43 * Test whether the currently-running OMAP chip matches the supplied
44 * chip type 'oc'. Returns 1 upon a match; 0 upon failure.
46 int omap_chip_is(struct omap_chip_id oci)
48 return (oci.oc & omap_chip.oc) ? 1 : 0;
50 EXPORT_SYMBOL(omap_chip_is);
52 int omap_type(void)
54 u32 val = 0;
56 if (cpu_is_omap24xx())
57 val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
58 else if (cpu_is_omap34xx())
59 val = omap_ctrl_readl(OMAP343X_CONTROL_STATUS);
60 else {
61 pr_err("Cannot detect omap type!\n");
62 goto out;
65 val &= OMAP2_DEVICETYPE_MASK;
66 val >>= 8;
68 out:
69 return val;
71 EXPORT_SYMBOL(omap_type);
74 /*----------------------------------------------------------------------------*/
76 #define OMAP_TAP_IDCODE 0x0204
77 #define OMAP_TAP_DIE_ID_0 0x0218
78 #define OMAP_TAP_DIE_ID_1 0x021C
79 #define OMAP_TAP_DIE_ID_2 0x0220
80 #define OMAP_TAP_DIE_ID_3 0x0224
82 #define read_tap_reg(reg) __raw_readl(tap_base + (reg))
84 struct omap_id {
85 u16 hawkeye; /* Silicon type (Hawkeye id) */
86 u8 dev; /* Device type from production_id reg */
87 u32 type; /* Combined type id copied to omap_revision */
90 /* Register values to detect the OMAP version */
91 static struct omap_id omap_ids[] __initdata = {
92 { .hawkeye = 0xb5d9, .dev = 0x0, .type = 0x24200024 },
93 { .hawkeye = 0xb5d9, .dev = 0x1, .type = 0x24201024 },
94 { .hawkeye = 0xb5d9, .dev = 0x2, .type = 0x24202024 },
95 { .hawkeye = 0xb5d9, .dev = 0x4, .type = 0x24220024 },
96 { .hawkeye = 0xb5d9, .dev = 0x8, .type = 0x24230024 },
97 { .hawkeye = 0xb68a, .dev = 0x0, .type = 0x24300024 },
100 static void __iomem *tap_base;
101 static u16 tap_prod_id;
103 void __init omap24xx_check_revision(void)
105 int i, j;
106 u32 idcode, prod_id;
107 u16 hawkeye;
108 u8 dev_type, rev;
110 idcode = read_tap_reg(OMAP_TAP_IDCODE);
111 prod_id = read_tap_reg(tap_prod_id);
112 hawkeye = (idcode >> 12) & 0xffff;
113 rev = (idcode >> 28) & 0x0f;
114 dev_type = (prod_id >> 16) & 0x0f;
116 pr_debug("OMAP_TAP_IDCODE 0x%08x REV %i HAWKEYE 0x%04x MANF %03x\n",
117 idcode, rev, hawkeye, (idcode >> 1) & 0x7ff);
118 pr_debug("OMAP_TAP_DIE_ID_0: 0x%08x\n",
119 read_tap_reg(OMAP_TAP_DIE_ID_0));
120 pr_debug("OMAP_TAP_DIE_ID_1: 0x%08x DEV_REV: %i\n",
121 read_tap_reg(OMAP_TAP_DIE_ID_1),
122 (read_tap_reg(OMAP_TAP_DIE_ID_1) >> 28) & 0xf);
123 pr_debug("OMAP_TAP_DIE_ID_2: 0x%08x\n",
124 read_tap_reg(OMAP_TAP_DIE_ID_2));
125 pr_debug("OMAP_TAP_DIE_ID_3: 0x%08x\n",
126 read_tap_reg(OMAP_TAP_DIE_ID_3));
127 pr_debug("OMAP_TAP_PROD_ID_0: 0x%08x DEV_TYPE: %i\n",
128 prod_id, dev_type);
130 /* Check hawkeye ids */
131 for (i = 0; i < ARRAY_SIZE(omap_ids); i++) {
132 if (hawkeye == omap_ids[i].hawkeye)
133 break;
136 if (i == ARRAY_SIZE(omap_ids)) {
137 printk(KERN_ERR "Unknown OMAP CPU id\n");
138 return;
141 for (j = i; j < ARRAY_SIZE(omap_ids); j++) {
142 if (dev_type == omap_ids[j].dev)
143 break;
146 if (j == ARRAY_SIZE(omap_ids)) {
147 printk(KERN_ERR "Unknown OMAP device type. "
148 "Handling it as OMAP%04x\n",
149 omap_ids[i].type >> 16);
150 j = i;
153 pr_info("OMAP%04x", omap_rev() >> 16);
154 if ((omap_rev() >> 8) & 0x0f)
155 pr_info("ES%x", (omap_rev() >> 12) & 0xf);
156 pr_info("\n");
159 #define OMAP3_CHECK_FEATURE(status,feat) \
160 if (((status & OMAP3_ ##feat## _MASK) \
161 >> OMAP3_ ##feat## _SHIFT) != FEAT_ ##feat## _NONE) { \
162 omap3_features |= OMAP3_HAS_ ##feat; \
165 void __init omap3_check_features(void)
167 u32 status;
169 omap3_features = 0;
171 status = omap_ctrl_readl(OMAP3_CONTROL_OMAP_STATUS);
173 OMAP3_CHECK_FEATURE(status, L2CACHE);
174 OMAP3_CHECK_FEATURE(status, IVA);
175 OMAP3_CHECK_FEATURE(status, SGX);
176 OMAP3_CHECK_FEATURE(status, NEON);
177 OMAP3_CHECK_FEATURE(status, ISP);
180 * TODO: Get additional info (where applicable)
181 * e.g. Size of L2 cache.
185 void __init omap3_check_revision(void)
187 u32 cpuid, idcode;
188 u16 hawkeye;
189 u8 rev;
192 * We cannot access revision registers on ES1.0.
193 * If the processor type is Cortex-A8 and the revision is 0x0
194 * it means its Cortex r0p0 which is 3430 ES1.0.
196 cpuid = read_cpuid(CPUID_ID);
197 if ((((cpuid >> 4) & 0xfff) == 0xc08) && ((cpuid & 0xf) == 0x0)) {
198 omap_revision = OMAP3430_REV_ES1_0;
199 return;
203 * Detection for 34xx ES2.0 and above can be done with just
204 * hawkeye and rev. See TRM 1.5.2 Device Identification.
205 * Note that rev does not map directly to our defined processor
206 * revision numbers as ES1.0 uses value 0.
208 idcode = read_tap_reg(OMAP_TAP_IDCODE);
209 hawkeye = (idcode >> 12) & 0xffff;
210 rev = (idcode >> 28) & 0xff;
212 switch (hawkeye) {
213 case 0xb7ae:
214 /* Handle 34xx/35xx devices */
215 switch (rev) {
216 case 0: /* Take care of early samples */
217 case 1:
218 omap_revision = OMAP3430_REV_ES2_0;
219 break;
220 case 2:
221 omap_revision = OMAP3430_REV_ES2_1;
222 break;
223 case 3:
224 omap_revision = OMAP3430_REV_ES3_0;
225 break;
226 case 4:
227 omap_revision = OMAP3430_REV_ES3_1;
228 break;
229 default:
230 /* Use the latest known revision as default */
231 omap_revision = OMAP3430_REV_ES3_1;
233 break;
234 case 0xb891:
235 /* Handle 36xx devices */
236 switch (rev) {
237 case 0:
238 omap_revision = OMAP3630_REV_ES1_0;
239 break;
240 default:
241 /* Use the latest known revision as default */
242 omap_revision = OMAP3630_REV_ES1_0;
244 break;
245 default:
246 /* Unknown default to latest silicon rev as default*/
247 omap_revision = OMAP3630_REV_ES1_0;
251 #define OMAP3_SHOW_FEATURE(feat) \
252 if (omap3_has_ ##feat()) { \
253 pr_info (" - "#feat" : Y"); \
254 } else { \
255 pr_info (" - "#feat" : N"); \
258 void __init omap3_cpuinfo(void)
260 u8 rev = GET_OMAP_REVISION();
261 char cpu_name[16], cpu_rev[16];
263 /* OMAP3430 and OMAP3530 are assumed to be same.
265 * OMAP3525, OMAP3515 and OMAP3503 can be detected only based
266 * on available features. Upon detection, update the CPU id
267 * and CPU class bits.
269 if (cpu_is_omap3630())
270 strcpy(cpu_name, "3630");
271 else if (omap3_has_iva() && omap3_has_sgx())
272 strcpy(cpu_name, "3430/3530");
273 else if (omap3_has_sgx()) {
274 omap_revision = OMAP3525_REV(rev);
275 strcpy(cpu_name, "3525");
277 else if (omap3_has_iva()) {
278 omap_revision = OMAP3515_REV(rev);
279 strcpy(cpu_name, "3515");
281 else {
282 omap_revision = OMAP3503_REV(rev);
283 strcpy(cpu_name, "3503");
286 switch (rev) {
287 case OMAP_REVBITS_00:
288 strcpy(cpu_rev, "1.0");
289 break;
290 case OMAP_REVBITS_10:
291 strcpy(cpu_rev, "2.0");
292 break;
293 case OMAP_REVBITS_20:
294 strcpy(cpu_rev, "2.1");
295 break;
296 case OMAP_REVBITS_30:
297 strcpy(cpu_rev, "3.0");
298 break;
299 case OMAP_REVBITS_40:
300 strcpy(cpu_rev, "3.1");
301 break;
302 default:
303 /* Use the latest known revision as default */
304 strcpy(cpu_rev, "3.1");
308 * Print verbose information
310 pr_info("OMAP%s ES%s\n", cpu_name, cpu_rev);
312 OMAP3_SHOW_FEATURE(l2cache);
313 OMAP3_SHOW_FEATURE(iva);
314 OMAP3_SHOW_FEATURE(sgx);
315 OMAP3_SHOW_FEATURE(neon);
316 OMAP3_SHOW_FEATURE(isp);
320 * Try to detect the exact revision of the omap we're running on
322 void __init omap2_check_revision(void)
325 * At this point we have an idea about the processor revision set
326 * earlier with omap2_set_globals_tap().
328 if (cpu_is_omap24xx())
329 omap24xx_check_revision();
330 else if (cpu_is_omap34xx()) {
331 omap3_check_features();
332 omap3_check_revision();
333 omap3_cpuinfo();
335 else if (cpu_is_omap44xx()) {
336 printk(KERN_INFO "FIXME: CPU revision = OMAP4430\n");
337 return;
338 } else
339 pr_err("OMAP revision unknown, please fix!\n");
342 * OK, now we know the exact revision. Initialize omap_chip bits
343 * for powerdowmain and clockdomain code.
345 if (cpu_is_omap243x()) {
346 /* Currently only supports 2430ES2.1 and 2430-all */
347 omap_chip.oc |= CHIP_IS_OMAP2430;
348 } else if (cpu_is_omap242x()) {
349 /* Currently only supports 2420ES2.1.1 and 2420-all */
350 omap_chip.oc |= CHIP_IS_OMAP2420;
351 } else if (cpu_is_omap343x()) {
352 omap_chip.oc = CHIP_IS_OMAP3430;
353 if (omap_rev() == OMAP3430_REV_ES1_0)
354 omap_chip.oc |= CHIP_IS_OMAP3430ES1;
355 else if (omap_rev() >= OMAP3430_REV_ES2_0 &&
356 omap_rev() <= OMAP3430_REV_ES2_1)
357 omap_chip.oc |= CHIP_IS_OMAP3430ES2;
358 else if (omap_rev() == OMAP3430_REV_ES3_0)
359 omap_chip.oc |= CHIP_IS_OMAP3430ES3_0;
360 else if (omap_rev() == OMAP3430_REV_ES3_1)
361 omap_chip.oc |= CHIP_IS_OMAP3430ES3_1;
362 } else {
363 pr_err("Uninitialized omap_chip, please fix!\n");
368 * Set up things for map_io and processor detection later on. Gets called
369 * pretty much first thing from board init. For multi-omap, this gets
370 * cpu_is_omapxxxx() working accurately enough for map_io. Then we'll try to
371 * detect the exact revision later on in omap2_detect_revision() once map_io
372 * is done.
374 void __init omap2_set_globals_tap(struct omap_globals *omap2_globals)
376 omap_revision = omap2_globals->class;
377 tap_base = omap2_globals->tap;
379 if (cpu_is_omap34xx())
380 tap_prod_id = 0x0210;
381 else
382 tap_prod_id = 0x0208;