include/asm-powerpc/qe.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Authors:     Shlomi Gridish <gridish@freescale.com>
   5  *              Li Yang <leoli@freescale.com>
   6  *
   7  * Description:
   8  * QUICC Engine (QE) external definitions and structure.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15 #ifndef _ASM_POWERPC_QE_H
  16 #define _ASM_POWERPC_QE_H
  17 #ifdef __KERNEL__
  18
  19 #include <linux/spinlock.h>
  20 #include <asm/cpm.h>
  21 #include <asm/immap_qe.h>
  22
  23 #define QE_NUM_OF_SNUM  28
  24 #define QE_NUM_OF_BRGS  16
  25 #define QE_NUM_OF_PORTS 1024
  26
  27 /* Memory partitions
  28 */
  29 #define MEM_PART_SYSTEM         0
  30 #define MEM_PART_SECONDARY      1
  31 #define MEM_PART_MURAM          2
  32
  33 /* Clocks and BRGs */
  34 enum qe_clock {
  35         QE_CLK_NONE = 0,
  36         QE_BRG1,                /* Baud Rate Generator 1 */
  37         QE_BRG2,                /* Baud Rate Generator 2 */
  38         QE_BRG3,                /* Baud Rate Generator 3 */
  39         QE_BRG4,                /* Baud Rate Generator 4 */
  40         QE_BRG5,                /* Baud Rate Generator 5 */
  41         QE_BRG6,                /* Baud Rate Generator 6 */
  42         QE_BRG7,                /* Baud Rate Generator 7 */
  43         QE_BRG8,                /* Baud Rate Generator 8 */
  44         QE_BRG9,                /* Baud Rate Generator 9 */
  45         QE_BRG10,               /* Baud Rate Generator 10 */
  46         QE_BRG11,               /* Baud Rate Generator 11 */
  47         QE_BRG12,               /* Baud Rate Generator 12 */
  48         QE_BRG13,               /* Baud Rate Generator 13 */
  49         QE_BRG14,               /* Baud Rate Generator 14 */
  50         QE_BRG15,               /* Baud Rate Generator 15 */
  51         QE_BRG16,               /* Baud Rate Generator 16 */
  52         QE_CLK1,                /* Clock 1 */
  53         QE_CLK2,                /* Clock 2 */
  54         QE_CLK3,                /* Clock 3 */
  55         QE_CLK4,                /* Clock 4 */
  56         QE_CLK5,                /* Clock 5 */
  57         QE_CLK6,                /* Clock 6 */
  58         QE_CLK7,                /* Clock 7 */
  59         QE_CLK8,                /* Clock 8 */
  60         QE_CLK9,                /* Clock 9 */
  61         QE_CLK10,               /* Clock 10 */
  62         QE_CLK11,               /* Clock 11 */
  63         QE_CLK12,               /* Clock 12 */
  64         QE_CLK13,               /* Clock 13 */
  65         QE_CLK14,               /* Clock 14 */
  66         QE_CLK15,               /* Clock 15 */
  67         QE_CLK16,               /* Clock 16 */
  68         QE_CLK17,               /* Clock 17 */
  69         QE_CLK18,               /* Clock 18 */
  70         QE_CLK19,               /* Clock 19 */
  71         QE_CLK20,               /* Clock 20 */
  72         QE_CLK21,               /* Clock 21 */
  73         QE_CLK22,               /* Clock 22 */
  74         QE_CLK23,               /* Clock 23 */
  75         QE_CLK24,               /* Clock 24 */
  76         QE_CLK_DUMMY
  77 };
  78
  79 static inline bool qe_clock_is_brg(enum qe_clock clk)
  80 {
  81         return clk >= QE_BRG1 && clk <= QE_BRG16;
  82 }
  83
  84 extern spinlock_t cmxgcr_lock;
  85
  86 /* Export QE common operations */
  87 extern void __init qe_reset(void);
  88
  89 /* QE PIO */
  90 #define QE_PIO_PINS 32
  91
  92 struct qe_pio_regs {
  93         __be32  cpodr;          /* Open drain register */
  94         __be32  cpdata;         /* Data register */
  95         __be32  cpdir1;         /* Direction register */
  96         __be32  cpdir2;         /* Direction register */
  97         __be32  cppar1;         /* Pin assignment register */
  98         __be32  cppar2;         /* Pin assignment register */
  99 #ifdef CONFIG_PPC_85xx
 100         u8      pad[8];
 101 #endif
 102 };
 103
 104 extern int par_io_init(struct device_node *np);
 105 extern int par_io_of_config(struct device_node *np);
 106 #define QE_PIO_DIR_IN   2
 107 #define QE_PIO_DIR_OUT  1
 108 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
 109                                 int dir, int open_drain, int assignment,
 110                                 int has_irq);
 111 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
 112                              int assignment, int has_irq);
 113 extern int par_io_data_set(u8 port, u8 pin, u8 val);
 114
 115 /* QE internal API */
 116 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
 117 enum qe_clock qe_clock_source(const char *source);
 118 unsigned int qe_get_brg_clk(void);
 119 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
 120 int qe_get_snum(void);
 121 void qe_put_snum(u8 snum);
 122 /* we actually use cpm_muram implementation, define this for convenience */
 123 #define qe_muram_init cpm_muram_init
 124 #define qe_muram_alloc cpm_muram_alloc
 125 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed
 126 #define qe_muram_free cpm_muram_free
 127 #define qe_muram_addr cpm_muram_addr
 128 #define qe_muram_offset cpm_muram_offset
 129
 130 /* Structure that defines QE firmware binary files.
 131  *
 132  * See Documentation/powerpc/qe-firmware.txt for a description of these
 133  * fields.
 134  */
 135 struct qe_firmware {
 136         struct qe_header {
 137                 __be32 length;  /* Length of the entire structure, in bytes */
 138                 u8 magic[3];    /* Set to { 'Q', 'E', 'F' } */
 139                 u8 version;     /* Version of this layout. First ver is '1' */
 140         } header;
 141         u8 id[62];      /* Null-terminated identifier string */
 142         u8 split;       /* 0 = shared I-RAM, 1 = split I-RAM */
 143         u8 count;       /* Number of microcode[] structures */
 144         struct {
 145                 __be16 model;           /* The SOC model  */
 146                 u8 major;               /* The SOC revision major */
 147                 u8 minor;               /* The SOC revision minor */
 148         } __attribute__ ((packed)) soc;
 149         u8 padding[4];                  /* Reserved, for alignment */
 150         __be64 extended_modes;          /* Extended modes */
 151         __be32 vtraps[8];               /* Virtual trap addresses */
 152         u8 reserved[4];                 /* Reserved, for future expansion */
 153         struct qe_microcode {
 154                 u8 id[32];              /* Null-terminated identifier */
 155                 __be32 traps[16];       /* Trap addresses, 0 == ignore */
 156                 __be32 eccr;            /* The value for the ECCR register */
 157                 __be32 iram_offset;     /* Offset into I-RAM for the code */
 158                 __be32 count;           /* Number of 32-bit words of the code */
 159                 __be32 code_offset;     /* Offset of the actual microcode */
 160                 u8 major;               /* The microcode version major */
 161                 u8 minor;               /* The microcode version minor */
 162                 u8 revision;            /* The microcode version revision */
 163                 u8 padding;             /* Reserved, for alignment */
 164                 u8 reserved[4];         /* Reserved, for future expansion */
 165         } __attribute__ ((packed)) microcode[1];
 166         /* All microcode binaries should be located here */
 167         /* CRC32 should be located here, after the microcode binaries */
 168 } __attribute__ ((packed));
 169
 170 struct qe_firmware_info {
 171         char id[64];            /* Firmware name */
 172         u32 vtraps[8];          /* Virtual trap addresses */
 173         u64 extended_modes;     /* Extended modes */
 174 };
 175
 176 /* Upload a firmware to the QE */
 177 int qe_upload_firmware(const struct qe_firmware *firmware);
 178
 179 /* Obtain information on the uploaded firmware */
 180 struct qe_firmware_info *qe_get_firmware_info(void);
 181
 182 /* QE USB */
 183 int qe_usb_clock_set(enum qe_clock clk, int rate);
 184
 185 /* Buffer descriptors */
 186 struct qe_bd {
 187         __be16 status;
 188         __be16 length;
 189         __be32 buf;
 190 } __attribute__ ((packed));
 191
 192 #define BD_STATUS_MASK  0xffff0000
 193 #define BD_LENGTH_MASK  0x0000ffff
 194
 195 /* Alignment */
 196 #define QE_INTR_TABLE_ALIGN     16      /* ??? */
 197 #define QE_ALIGNMENT_OF_BD      8
 198 #define QE_ALIGNMENT_OF_PRAM    64
 199
 200 /* RISC allocation */
 201 enum qe_risc_allocation {
 202         QE_RISC_ALLOCATION_RISC1 = 1,   /* RISC 1 */
 203         QE_RISC_ALLOCATION_RISC2 = 2,   /* RISC 2 */
 204         QE_RISC_ALLOCATION_RISC1_AND_RISC2 = 3  /* Dynamically choose
 205                                                    RISC 1 or RISC 2 */
 206 };
 207
 208 /* QE extended filtering Table Lookup Key Size */
 209 enum qe_fltr_tbl_lookup_key_size {
 210         QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
 211                 = 0x3f,         /* LookupKey parsed by the Generate LookupKey
 212                                    CMD is truncated to 8 bytes */
 213         QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
 214                 = 0x5f,         /* LookupKey parsed by the Generate LookupKey
 215                                    CMD is truncated to 16 bytes */
 216 };
 217
 218 /* QE FLTR extended filtering Largest External Table Lookup Key Size */
 219 enum qe_fltr_largest_external_tbl_lookup_key_size {
 220         QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
 221                 = 0x0,/* not used */
 222         QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
 223                 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES,        /* 8 bytes */
 224         QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
 225                 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES,       /* 16 bytes */
 226 };
 227
 228 /* structure representing QE parameter RAM */
 229 struct qe_timer_tables {
 230         u16 tm_base;            /* QE timer table base adr */
 231         u16 tm_ptr;             /* QE timer table pointer */
 232         u16 r_tmr;              /* QE timer mode register */
 233         u16 r_tmv;              /* QE timer valid register */
 234         u32 tm_cmd;             /* QE timer cmd register */
 235         u32 tm_cnt;             /* QE timer internal cnt */
 236 } __attribute__ ((packed));
 237
 238 #define QE_FLTR_TAD_SIZE        8
 239
 240 /* QE extended filtering Termination Action Descriptor (TAD) */
 241 struct qe_fltr_tad {
 242         u8 serialized[QE_FLTR_TAD_SIZE];
 243 } __attribute__ ((packed));
 244
 245 /* Communication Direction */
 246 enum comm_dir {
 247         COMM_DIR_NONE = 0,
 248         COMM_DIR_RX = 1,
 249         COMM_DIR_TX = 2,
 250         COMM_DIR_RX_AND_TX = 3
 251 };
 252
 253 /* QE CMXUCR Registers.
 254  * There are two UCCs represented in each of the four CMXUCR registers.
 255  * These values are for the UCC in the LSBs
 256  */
 257 #define QE_CMXUCR_MII_ENET_MNG          0x00007000
 258 #define QE_CMXUCR_MII_ENET_MNG_SHIFT    12
 259 #define QE_CMXUCR_GRANT                 0x00008000
 260 #define QE_CMXUCR_TSA                   0x00004000
 261 #define QE_CMXUCR_BKPT                  0x00000100
 262 #define QE_CMXUCR_TX_CLK_SRC_MASK       0x0000000F
 263
 264 /* QE CMXGCR Registers.
 265 */
 266 #define QE_CMXGCR_MII_ENET_MNG          0x00007000
 267 #define QE_CMXGCR_MII_ENET_MNG_SHIFT    12
 268 #define QE_CMXGCR_USBCS                 0x0000000f
 269 #define QE_CMXGCR_USBCS_CLK3            0x1
 270 #define QE_CMXGCR_USBCS_CLK5            0x2
 271 #define QE_CMXGCR_USBCS_CLK7            0x3
 272 #define QE_CMXGCR_USBCS_CLK9            0x4
 273 #define QE_CMXGCR_USBCS_CLK13           0x5
 274 #define QE_CMXGCR_USBCS_CLK17           0x6
 275 #define QE_CMXGCR_USBCS_CLK19           0x7
 276 #define QE_CMXGCR_USBCS_CLK21           0x8
 277 #define QE_CMXGCR_USBCS_BRG9            0x9
 278 #define QE_CMXGCR_USBCS_BRG10           0xa
 279
 280 /* QE CECR Commands.
 281 */
 282 #define QE_CR_FLG                       0x00010000
 283 #define QE_RESET                        0x80000000
 284 #define QE_INIT_TX_RX                   0x00000000
 285 #define QE_INIT_RX                      0x00000001
 286 #define QE_INIT_TX                      0x00000002
 287 #define QE_ENTER_HUNT_MODE              0x00000003
 288 #define QE_STOP_TX                      0x00000004
 289 #define QE_GRACEFUL_STOP_TX             0x00000005
 290 #define QE_RESTART_TX                   0x00000006
 291 #define QE_CLOSE_RX_BD                  0x00000007
 292 #define QE_SWITCH_COMMAND               0x00000007
 293 #define QE_SET_GROUP_ADDRESS            0x00000008
 294 #define QE_START_IDMA                   0x00000009
 295 #define QE_MCC_STOP_RX                  0x00000009
 296 #define QE_ATM_TRANSMIT                 0x0000000a
 297 #define QE_HPAC_CLEAR_ALL               0x0000000b
 298 #define QE_GRACEFUL_STOP_RX             0x0000001a
 299 #define QE_RESTART_RX                   0x0000001b
 300 #define QE_HPAC_SET_PRIORITY            0x0000010b
 301 #define QE_HPAC_STOP_TX                 0x0000020b
 302 #define QE_HPAC_STOP_RX                 0x0000030b
 303 #define QE_HPAC_GRACEFUL_STOP_TX        0x0000040b
 304 #define QE_HPAC_GRACEFUL_STOP_RX        0x0000050b
 305 #define QE_HPAC_START_TX                0x0000060b
 306 #define QE_HPAC_START_RX                0x0000070b
 307 #define QE_USB_STOP_TX                  0x0000000a
 308 #define QE_USB_RESTART_TX               0x0000000c
 309 #define QE_QMC_STOP_TX                  0x0000000c
 310 #define QE_QMC_STOP_RX                  0x0000000d
 311 #define QE_SS7_SU_FIL_RESET             0x0000000e
 312 /* jonathbr added from here down for 83xx */
 313 #define QE_RESET_BCS                    0x0000000a
 314 #define QE_MCC_INIT_TX_RX_16            0x00000003
 315 #define QE_MCC_STOP_TX                  0x00000004
 316 #define QE_MCC_INIT_TX_1                0x00000005
 317 #define QE_MCC_INIT_RX_1                0x00000006
 318 #define QE_MCC_RESET                    0x00000007
 319 #define QE_SET_TIMER                    0x00000008
 320 #define QE_RANDOM_NUMBER                0x0000000c
 321 #define QE_ATM_MULTI_THREAD_INIT        0x00000011
 322 #define QE_ASSIGN_PAGE                  0x00000012
 323 #define QE_ADD_REMOVE_HASH_ENTRY        0x00000013
 324 #define QE_START_FLOW_CONTROL           0x00000014
 325 #define QE_STOP_FLOW_CONTROL            0x00000015
 326 #define QE_ASSIGN_PAGE_TO_DEVICE        0x00000016
 327
 328 #define QE_ASSIGN_RISC                  0x00000010
 329 #define QE_CR_MCN_NORMAL_SHIFT          6
 330 #define QE_CR_MCN_USB_SHIFT             4
 331 #define QE_CR_MCN_RISC_ASSIGN_SHIFT     8
 332 #define QE_CR_SNUM_SHIFT                17
 333
 334 /* QE CECR Sub Block - sub block of QE command.
 335 */
 336 #define QE_CR_SUBBLOCK_INVALID          0x00000000
 337 #define QE_CR_SUBBLOCK_USB              0x03200000
 338 #define QE_CR_SUBBLOCK_UCCFAST1         0x02000000
 339 #define QE_CR_SUBBLOCK_UCCFAST2         0x02200000
 340 #define QE_CR_SUBBLOCK_UCCFAST3         0x02400000
 341 #define QE_CR_SUBBLOCK_UCCFAST4         0x02600000
 342 #define QE_CR_SUBBLOCK_UCCFAST5         0x02800000
 343 #define QE_CR_SUBBLOCK_UCCFAST6         0x02a00000
 344 #define QE_CR_SUBBLOCK_UCCFAST7         0x02c00000
 345 #define QE_CR_SUBBLOCK_UCCFAST8         0x02e00000
 346 #define QE_CR_SUBBLOCK_UCCSLOW1         0x00000000
 347 #define QE_CR_SUBBLOCK_UCCSLOW2         0x00200000
 348 #define QE_CR_SUBBLOCK_UCCSLOW3         0x00400000
 349 #define QE_CR_SUBBLOCK_UCCSLOW4         0x00600000
 350 #define QE_CR_SUBBLOCK_UCCSLOW5         0x00800000
 351 #define QE_CR_SUBBLOCK_UCCSLOW6         0x00a00000
 352 #define QE_CR_SUBBLOCK_UCCSLOW7         0x00c00000
 353 #define QE_CR_SUBBLOCK_UCCSLOW8         0x00e00000
 354 #define QE_CR_SUBBLOCK_MCC1             0x03800000
 355 #define QE_CR_SUBBLOCK_MCC2             0x03a00000
 356 #define QE_CR_SUBBLOCK_MCC3             0x03000000
 357 #define QE_CR_SUBBLOCK_IDMA1            0x02800000
 358 #define QE_CR_SUBBLOCK_IDMA2            0x02a00000
 359 #define QE_CR_SUBBLOCK_IDMA3            0x02c00000
 360 #define QE_CR_SUBBLOCK_IDMA4            0x02e00000
 361 #define QE_CR_SUBBLOCK_HPAC             0x01e00000
 362 #define QE_CR_SUBBLOCK_SPI1             0x01400000
 363 #define QE_CR_SUBBLOCK_SPI2             0x01600000
 364 #define QE_CR_SUBBLOCK_RAND             0x01c00000
 365 #define QE_CR_SUBBLOCK_TIMER            0x01e00000
 366 #define QE_CR_SUBBLOCK_GENERAL          0x03c00000
 367
 368 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
 369 #define QE_CR_PROTOCOL_UNSPECIFIED      0x00    /* For all other protocols */
 370 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
 371 #define QE_CR_PROTOCOL_QMC              0x02
 372 #define QE_CR_PROTOCOL_UART             0x04
 373 #define QE_CR_PROTOCOL_ATM_POS          0x0A
 374 #define QE_CR_PROTOCOL_ETHERNET         0x0C
 375 #define QE_CR_PROTOCOL_L2_SWITCH        0x0D
 376
 377 /* BRG configuration register */
 378 #define QE_BRGC_ENABLE          0x00010000
 379 #define QE_BRGC_DIVISOR_SHIFT   1
 380 #define QE_BRGC_DIVISOR_MAX     0xFFF
 381 #define QE_BRGC_DIV16           1
 382
 383 /* QE Timers registers */
 384 #define QE_GTCFR1_PCAS  0x80
 385 #define QE_GTCFR1_STP2  0x20
 386 #define QE_GTCFR1_RST2  0x10
 387 #define QE_GTCFR1_GM2   0x08
 388 #define QE_GTCFR1_GM1   0x04
 389 #define QE_GTCFR1_STP1  0x02
 390 #define QE_GTCFR1_RST1  0x01
 391
 392 /* SDMA registers */
 393 #define QE_SDSR_BER1    0x02000000
 394 #define QE_SDSR_BER2    0x01000000
 395
 396 #define QE_SDMR_GLB_1_MSK       0x80000000
 397 #define QE_SDMR_ADR_SEL         0x20000000
 398 #define QE_SDMR_BER1_MSK        0x02000000
 399 #define QE_SDMR_BER2_MSK        0x01000000
 400 #define QE_SDMR_EB1_MSK         0x00800000
 401 #define QE_SDMR_ER1_MSK         0x00080000
 402 #define QE_SDMR_ER2_MSK         0x00040000
 403 #define QE_SDMR_CEN_MASK        0x0000E000
 404 #define QE_SDMR_SBER_1          0x00000200
 405 #define QE_SDMR_SBER_2          0x00000200
 406 #define QE_SDMR_EB1_PR_MASK     0x000000C0
 407 #define QE_SDMR_ER1_PR          0x00000008
 408
 409 #define QE_SDMR_CEN_SHIFT       13
 410 #define QE_SDMR_EB1_PR_SHIFT    6
 411
 412 #define QE_SDTM_MSNUM_SHIFT     24
 413
 414 #define QE_SDEBCR_BA_MASK       0x01FFFFFF
 415
 416 /* Communication Processor */
 417 #define QE_CP_CERCR_MEE         0x8000  /* Multi-user RAM ECC enable */
 418 #define QE_CP_CERCR_IEE         0x4000  /* Instruction RAM ECC enable */
 419 #define QE_CP_CERCR_CIR         0x0800  /* Common instruction RAM */
 420
 421 /* I-RAM */
 422 #define QE_IRAM_IADD_AIE        0x80000000      /* Auto Increment Enable */
 423 #define QE_IRAM_IADD_BADDR      0x00080000      /* Base Address */
 424
 425 /* UPC */
 426 #define UPGCR_PROTOCOL  0x80000000      /* protocol ul2 or pl2 */
 427 #define UPGCR_TMS       0x40000000      /* Transmit master/slave mode */
 428 #define UPGCR_RMS       0x20000000      /* Receive master/slave mode */
 429 #define UPGCR_ADDR      0x10000000      /* Master MPHY Addr multiplexing */
 430 #define UPGCR_DIAG      0x01000000      /* Diagnostic mode */
 431
 432 /* UCC GUEMR register */
 433 #define UCC_GUEMR_MODE_MASK_RX  0x02
 434 #define UCC_GUEMR_MODE_FAST_RX  0x02
 435 #define UCC_GUEMR_MODE_SLOW_RX  0x00
 436 #define UCC_GUEMR_MODE_MASK_TX  0x01
 437 #define UCC_GUEMR_MODE_FAST_TX  0x01
 438 #define UCC_GUEMR_MODE_SLOW_TX  0x00
 439 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
 440 #define UCC_GUEMR_SET_RESERVED3 0x10    /* Bit 3 in the guemr is reserved but
 441                                            must be set 1 */
 442
 443 /* structure representing UCC SLOW parameter RAM */
 444 struct ucc_slow_pram {
 445         __be16 rbase;           /* RX BD base address */
 446         __be16 tbase;           /* TX BD base address */
 447         u8 rbmr;                /* RX bus mode register (same as CPM's RFCR) */
 448         u8 tbmr;                /* TX bus mode register (same as CPM's TFCR) */
 449         __be16 mrblr;           /* Rx buffer length */
 450         __be32 rstate;          /* Rx internal state */
 451         __be32 rptr;            /* Rx internal data pointer */
 452         __be16 rbptr;           /* rb BD Pointer */
 453         __be16 rcount;          /* Rx internal byte count */
 454         __be32 rtemp;           /* Rx temp */
 455         __be32 tstate;          /* Tx internal state */
 456         __be32 tptr;            /* Tx internal data pointer */
 457         __be16 tbptr;           /* Tx BD pointer */
 458         __be16 tcount;          /* Tx byte count */
 459         __be32 ttemp;           /* Tx temp */
 460         __be32 rcrc;            /* temp receive CRC */
 461         __be32 tcrc;            /* temp transmit CRC */
 462 } __attribute__ ((packed));
 463
 464 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */
 465 #define UCC_SLOW_GUMR_H_SAM_QMC         0x00000000
 466 #define UCC_SLOW_GUMR_H_SAM_SATM        0x00008000
 467 #define UCC_SLOW_GUMR_H_REVD            0x00002000
 468 #define UCC_SLOW_GUMR_H_TRX             0x00001000
 469 #define UCC_SLOW_GUMR_H_TTX             0x00000800
 470 #define UCC_SLOW_GUMR_H_CDP             0x00000400
 471 #define UCC_SLOW_GUMR_H_CTSP            0x00000200
 472 #define UCC_SLOW_GUMR_H_CDS             0x00000100
 473 #define UCC_SLOW_GUMR_H_CTSS            0x00000080
 474 #define UCC_SLOW_GUMR_H_TFL             0x00000040
 475 #define UCC_SLOW_GUMR_H_RFW             0x00000020
 476 #define UCC_SLOW_GUMR_H_TXSY            0x00000010
 477 #define UCC_SLOW_GUMR_H_4SYNC           0x00000004
 478 #define UCC_SLOW_GUMR_H_8SYNC           0x00000008
 479 #define UCC_SLOW_GUMR_H_16SYNC          0x0000000c
 480 #define UCC_SLOW_GUMR_H_RTSM            0x00000002
 481 #define UCC_SLOW_GUMR_H_RSYN            0x00000001
 482
 483 #define UCC_SLOW_GUMR_L_TCI             0x10000000
 484 #define UCC_SLOW_GUMR_L_RINV            0x02000000
 485 #define UCC_SLOW_GUMR_L_TINV            0x01000000
 486 #define UCC_SLOW_GUMR_L_TEND            0x00040000
 487 #define UCC_SLOW_GUMR_L_TDCR_MASK       0x00030000
 488 #define UCC_SLOW_GUMR_L_TDCR_32         0x00030000
 489 #define UCC_SLOW_GUMR_L_TDCR_16         0x00020000
 490 #define UCC_SLOW_GUMR_L_TDCR_8          0x00010000
 491 #define UCC_SLOW_GUMR_L_TDCR_1          0x00000000
 492 #define UCC_SLOW_GUMR_L_RDCR_MASK       0x0000c000
 493 #define UCC_SLOW_GUMR_L_RDCR_32         0x0000c000
 494 #define UCC_SLOW_GUMR_L_RDCR_16         0x00008000
 495 #define UCC_SLOW_GUMR_L_RDCR_8          0x00004000
 496 #define UCC_SLOW_GUMR_L_RDCR_1          0x00000000
 497 #define UCC_SLOW_GUMR_L_RENC_NRZI       0x00000800
 498 #define UCC_SLOW_GUMR_L_RENC_NRZ        0x00000000
 499 #define UCC_SLOW_GUMR_L_TENC_NRZI       0x00000100
 500 #define UCC_SLOW_GUMR_L_TENC_NRZ        0x00000000
 501 #define UCC_SLOW_GUMR_L_DIAG_MASK       0x000000c0
 502 #define UCC_SLOW_GUMR_L_DIAG_LE         0x000000c0
 503 #define UCC_SLOW_GUMR_L_DIAG_ECHO       0x00000080
 504 #define UCC_SLOW_GUMR_L_DIAG_LOOP       0x00000040
 505 #define UCC_SLOW_GUMR_L_DIAG_NORM       0x00000000
 506 #define UCC_SLOW_GUMR_L_ENR             0x00000020
 507 #define UCC_SLOW_GUMR_L_ENT             0x00000010
 508 #define UCC_SLOW_GUMR_L_MODE_MASK       0x0000000F
 509 #define UCC_SLOW_GUMR_L_MODE_BISYNC     0x00000008
 510 #define UCC_SLOW_GUMR_L_MODE_AHDLC      0x00000006
 511 #define UCC_SLOW_GUMR_L_MODE_UART       0x00000004
 512 #define UCC_SLOW_GUMR_L_MODE_QMC        0x00000002
 513
 514 /* General UCC FAST Mode Register */
 515 #define UCC_FAST_GUMR_TCI       0x20000000
 516 #define UCC_FAST_GUMR_TRX       0x10000000
 517 #define UCC_FAST_GUMR_TTX       0x08000000
 518 #define UCC_FAST_GUMR_CDP       0x04000000
 519 #define UCC_FAST_GUMR_CTSP      0x02000000
 520 #define UCC_FAST_GUMR_CDS       0x01000000
 521 #define UCC_FAST_GUMR_CTSS      0x00800000
 522 #define UCC_FAST_GUMR_TXSY      0x00020000
 523 #define UCC_FAST_GUMR_RSYN      0x00010000
 524 #define UCC_FAST_GUMR_RTSM      0x00002000
 525 #define UCC_FAST_GUMR_REVD      0x00000400
 526 #define UCC_FAST_GUMR_ENR       0x00000020
 527 #define UCC_FAST_GUMR_ENT       0x00000010
 528
 529 /* UART Slow UCC Event Register (UCCE) */
 530 #define UCC_UART_UCCE_AB        0x0200
 531 #define UCC_UART_UCCE_IDLE      0x0100
 532 #define UCC_UART_UCCE_GRA       0x0080
 533 #define UCC_UART_UCCE_BRKE      0x0040
 534 #define UCC_UART_UCCE_BRKS      0x0020
 535 #define UCC_UART_UCCE_CCR       0x0008
 536 #define UCC_UART_UCCE_BSY       0x0004
 537 #define UCC_UART_UCCE_TX        0x0002
 538 #define UCC_UART_UCCE_RX        0x0001
 539
 540 /* HDLC Slow UCC Event Register (UCCE) */
 541 #define UCC_HDLC_UCCE_GLR       0x1000
 542 #define UCC_HDLC_UCCE_GLT       0x0800
 543 #define UCC_HDLC_UCCE_IDLE      0x0100
 544 #define UCC_HDLC_UCCE_BRKE      0x0040
 545 #define UCC_HDLC_UCCE_BRKS      0x0020
 546 #define UCC_HDLC_UCCE_TXE       0x0010
 547 #define UCC_HDLC_UCCE_RXF       0x0008
 548 #define UCC_HDLC_UCCE_BSY       0x0004
 549 #define UCC_HDLC_UCCE_TXB       0x0002
 550 #define UCC_HDLC_UCCE_RXB       0x0001
 551
 552 /* BISYNC Slow UCC Event Register (UCCE) */
 553 #define UCC_BISYNC_UCCE_GRA     0x0080
 554 #define UCC_BISYNC_UCCE_TXE     0x0010
 555 #define UCC_BISYNC_UCCE_RCH     0x0008
 556 #define UCC_BISYNC_UCCE_BSY     0x0004
 557 #define UCC_BISYNC_UCCE_TXB     0x0002
 558 #define UCC_BISYNC_UCCE_RXB     0x0001
 559
 560 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */
 561 #define UCC_GETH_UCCE_MPD       0x80000000
 562 #define UCC_GETH_UCCE_SCAR      0x40000000
 563 #define UCC_GETH_UCCE_GRA       0x20000000
 564 #define UCC_GETH_UCCE_CBPR      0x10000000
 565 #define UCC_GETH_UCCE_BSY       0x08000000
 566 #define UCC_GETH_UCCE_RXC       0x04000000
 567 #define UCC_GETH_UCCE_TXC       0x02000000
 568 #define UCC_GETH_UCCE_TXE       0x01000000
 569 #define UCC_GETH_UCCE_TXB7      0x00800000
 570 #define UCC_GETH_UCCE_TXB6      0x00400000
 571 #define UCC_GETH_UCCE_TXB5      0x00200000
 572 #define UCC_GETH_UCCE_TXB4      0x00100000
 573 #define UCC_GETH_UCCE_TXB3      0x00080000
 574 #define UCC_GETH_UCCE_TXB2      0x00040000
 575 #define UCC_GETH_UCCE_TXB1      0x00020000
 576 #define UCC_GETH_UCCE_TXB0      0x00010000
 577 #define UCC_GETH_UCCE_RXB7      0x00008000
 578 #define UCC_GETH_UCCE_RXB6      0x00004000
 579 #define UCC_GETH_UCCE_RXB5      0x00002000
 580 #define UCC_GETH_UCCE_RXB4      0x00001000
 581 #define UCC_GETH_UCCE_RXB3      0x00000800
 582 #define UCC_GETH_UCCE_RXB2      0x00000400
 583 #define UCC_GETH_UCCE_RXB1      0x00000200
 584 #define UCC_GETH_UCCE_RXB0      0x00000100
 585 #define UCC_GETH_UCCE_RXF7      0x00000080
 586 #define UCC_GETH_UCCE_RXF6      0x00000040
 587 #define UCC_GETH_UCCE_RXF5      0x00000020
 588 #define UCC_GETH_UCCE_RXF4      0x00000010
 589 #define UCC_GETH_UCCE_RXF3      0x00000008
 590 #define UCC_GETH_UCCE_RXF2      0x00000004
 591 #define UCC_GETH_UCCE_RXF1      0x00000002
 592 #define UCC_GETH_UCCE_RXF0      0x00000001
 593
 594 /* UPSMR, when used as a UART */
 595 #define UCC_UART_UPSMR_FLC              0x8000
 596 #define UCC_UART_UPSMR_SL               0x4000
 597 #define UCC_UART_UPSMR_CL_MASK          0x3000
 598 #define UCC_UART_UPSMR_CL_8             0x3000
 599 #define UCC_UART_UPSMR_CL_7             0x2000
 600 #define UCC_UART_UPSMR_CL_6             0x1000
 601 #define UCC_UART_UPSMR_CL_5             0x0000
 602 #define UCC_UART_UPSMR_UM_MASK          0x0c00
 603 #define UCC_UART_UPSMR_UM_NORMAL        0x0000
 604 #define UCC_UART_UPSMR_UM_MAN_MULTI     0x0400
 605 #define UCC_UART_UPSMR_UM_AUTO_MULTI    0x0c00
 606 #define UCC_UART_UPSMR_FRZ              0x0200
 607 #define UCC_UART_UPSMR_RZS              0x0100
 608 #define UCC_UART_UPSMR_SYN              0x0080
 609 #define UCC_UART_UPSMR_DRT              0x0040
 610 #define UCC_UART_UPSMR_PEN              0x0010
 611 #define UCC_UART_UPSMR_RPM_MASK         0x000c
 612 #define UCC_UART_UPSMR_RPM_ODD          0x0000
 613 #define UCC_UART_UPSMR_RPM_LOW          0x0004
 614 #define UCC_UART_UPSMR_RPM_EVEN         0x0008
 615 #define UCC_UART_UPSMR_RPM_HIGH         0x000C
 616 #define UCC_UART_UPSMR_TPM_MASK         0x0003
 617 #define UCC_UART_UPSMR_TPM_ODD          0x0000
 618 #define UCC_UART_UPSMR_TPM_LOW          0x0001
 619 #define UCC_UART_UPSMR_TPM_EVEN         0x0002
 620 #define UCC_UART_UPSMR_TPM_HIGH         0x0003
 621
 622 /* UCC Transmit On Demand Register (UTODR) */
 623 #define UCC_SLOW_TOD    0x8000
 624 #define UCC_FAST_TOD    0x8000
 625
 626 /* UCC Bus Mode Register masks */
 627 /* Not to be confused with the Bundle Mode Register */
 628 #define UCC_BMR_GBL             0x20
 629 #define UCC_BMR_BO_BE           0x10
 630 #define UCC_BMR_CETM            0x04
 631 #define UCC_BMR_DTB             0x02
 632 #define UCC_BMR_BDB             0x01
 633
 634 /* Function code masks */
 635 #define FC_GBL                          0x20
 636 #define FC_DTB_LCL                      0x02
 637 #define UCC_FAST_FUNCTION_CODE_GBL      0x20
 638 #define UCC_FAST_FUNCTION_CODE_DTB_LCL  0x02
 639 #define UCC_FAST_FUNCTION_CODE_BDB_LCL  0x01
 640
 641 #endif /* __KERNEL__ */
 642 #endif /* _ASM_POWERPC_QE_H */