arch/arm/mach-mx2/pcm038.c

   1 /*
   2  * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
   3  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/platform_device.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/mtd/plat-ram.h>
  23 #include <linux/io.h>
  24 #include <linux/i2c.h>
  25 #include <linux/i2c/at24.h>
  26
  27 #include <asm/mach/arch.h>
  28 #include <asm/mach-types.h>
  29 #include <mach/common.h>
  30 #include <mach/hardware.h>
  31 #include <mach/iomux.h>
  32 #ifdef CONFIG_I2C_IMX
  33 #include <mach/i2c.h>
  34 #endif
  35 #include <asm/mach/time.h>
  36 #include <mach/imx-uart.h>
  37 #include <mach/board-pcm038.h>
  38 #include <mach/mxc_nand.h>
  39
  40 #include "devices.h"
  41
  42 /*
  43  * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
  44  * 16 bit width
  45  */
  46
  47 static struct platdata_mtd_ram pcm038_sram_data = {
  48         .bankwidth = 2,
  49 };
  50
  51 static struct resource pcm038_sram_resource = {
  52         .start = CS1_BASE_ADDR,
  53         .end   = CS1_BASE_ADDR + 512 * 1024 - 1,
  54         .flags = IORESOURCE_MEM,
  55 };
  56
  57 static struct platform_device pcm038_sram_mtd_device = {
  58         .name = "mtd-ram",
  59         .id = 0,
  60         .dev = {
  61                 .platform_data = &pcm038_sram_data,
  62         },
  63         .num_resources = 1,
  64         .resource = &pcm038_sram_resource,
  65 };
  66
  67 /*
  68  * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
  69  * 16 bit width
  70  */
  71 static struct physmap_flash_data pcm038_flash_data = {
  72         .width = 2,
  73 };
  74
  75 static struct resource pcm038_flash_resource = {
  76         .start = 0xc0000000,
  77         .end   = 0xc1ffffff,
  78         .flags = IORESOURCE_MEM,
  79 };
  80
  81 static struct platform_device pcm038_nor_mtd_device = {
  82         .name = "physmap-flash",
  83         .id = 0,
  84         .dev = {
  85                 .platform_data = &pcm038_flash_data,
  86         },
  87         .num_resources = 1,
  88         .resource = &pcm038_flash_resource,
  89 };
  90
  91 static int mxc_uart0_pins[] = {
  92         PE12_PF_UART1_TXD,
  93         PE13_PF_UART1_RXD,
  94         PE14_PF_UART1_CTS,
  95         PE15_PF_UART1_RTS
  96 };
  97
  98 static int uart_mxc_port0_init(struct platform_device *pdev)
  99 {
 100         return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
 101                         ARRAY_SIZE(mxc_uart0_pins), "UART0");
 102 }
 103
 104 static int uart_mxc_port0_exit(struct platform_device *pdev)
 105 {
 106         mxc_gpio_release_multiple_pins(mxc_uart0_pins,
 107                         ARRAY_SIZE(mxc_uart0_pins));
 108         return 0;
 109 }
 110
 111 static int mxc_uart1_pins[] = {
 112         PE3_PF_UART2_CTS,
 113         PE4_PF_UART2_RTS,
 114         PE6_PF_UART2_TXD,
 115         PE7_PF_UART2_RXD
 116 };
 117
 118 static int uart_mxc_port1_init(struct platform_device *pdev)
 119 {
 120         return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
 121                         ARRAY_SIZE(mxc_uart1_pins), "UART1");
 122 }
 123
 124 static int uart_mxc_port1_exit(struct platform_device *pdev)
 125 {
 126         mxc_gpio_release_multiple_pins(mxc_uart1_pins,
 127                         ARRAY_SIZE(mxc_uart1_pins));
 128         return 0;
 129 }
 130
 131 static int mxc_uart2_pins[] = { PE8_PF_UART3_TXD,
 132                                 PE9_PF_UART3_RXD,
 133                                 PE10_PF_UART3_CTS,
 134                                 PE11_PF_UART3_RTS };
 135
 136 static int uart_mxc_port2_init(struct platform_device *pdev)
 137 {
 138         return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
 139                         ARRAY_SIZE(mxc_uart2_pins), "UART2");
 140 }
 141
 142 static int uart_mxc_port2_exit(struct platform_device *pdev)
 143 {
 144         mxc_gpio_release_multiple_pins(mxc_uart2_pins,
 145                         ARRAY_SIZE(mxc_uart2_pins));
 146         return 0;
 147 }
 148
 149 static struct imxuart_platform_data uart_pdata[] = {
 150         {
 151                 .init = uart_mxc_port0_init,
 152                 .exit = uart_mxc_port0_exit,
 153                 .flags = IMXUART_HAVE_RTSCTS,
 154         }, {
 155                 .init = uart_mxc_port1_init,
 156                 .exit = uart_mxc_port1_exit,
 157                 .flags = IMXUART_HAVE_RTSCTS,
 158         }, {
 159                 .init = uart_mxc_port2_init,
 160                 .exit = uart_mxc_port2_exit,
 161                 .flags = IMXUART_HAVE_RTSCTS,
 162         },
 163 };
 164
 165 static int mxc_fec_pins[] = {
 166         PD0_AIN_FEC_TXD0,
 167         PD1_AIN_FEC_TXD1,
 168         PD2_AIN_FEC_TXD2,
 169         PD3_AIN_FEC_TXD3,
 170         PD4_AOUT_FEC_RX_ER,
 171         PD5_AOUT_FEC_RXD1,
 172         PD6_AOUT_FEC_RXD2,
 173         PD7_AOUT_FEC_RXD3,
 174         PD8_AF_FEC_MDIO,
 175         PD9_AIN_FEC_MDC,
 176         PD10_AOUT_FEC_CRS,
 177         PD11_AOUT_FEC_TX_CLK,
 178         PD12_AOUT_FEC_RXD0,
 179         PD13_AOUT_FEC_RX_DV,
 180         PD14_AOUT_FEC_RX_CLK,
 181         PD15_AOUT_FEC_COL,
 182         PD16_AIN_FEC_TX_ER,
 183         PF23_AIN_FEC_TX_EN
 184 };
 185
 186 static void gpio_fec_active(void)
 187 {
 188         mxc_gpio_setup_multiple_pins(mxc_fec_pins,
 189                         ARRAY_SIZE(mxc_fec_pins), "FEC");
 190 }
 191
 192 static struct mxc_nand_platform_data pcm038_nand_board_info = {
 193         .width = 1,
 194         .hw_ecc = 1,
 195 };
 196
 197 static struct platform_device *platform_devices[] __initdata = {
 198         &pcm038_nor_mtd_device,
 199         &mxc_w1_master_device,
 200         &mxc_fec_device,
 201         &pcm038_sram_mtd_device,
 202 };
 203
 204 /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
 205  * setup other stuffs to access the sram. */
 206 static void __init pcm038_init_sram(void)
 207 {
 208         __raw_writel(0x0000d843, CSCR_U(1));
 209         __raw_writel(0x22252521, CSCR_L(1));
 210         __raw_writel(0x22220a00, CSCR_A(1));
 211 }
 212
 213 #ifdef CONFIG_I2C_IMX
 214 static int mxc_i2c1_pins[] = {
 215         PC5_PF_I2C2_SDA,
 216         PC6_PF_I2C2_SCL
 217 };
 218
 219 static int pcm038_i2c_1_init(struct device *dev)
 220 {
 221         return mxc_gpio_setup_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins),
 222                         "I2C1");
 223 }
 224
 225 static void pcm038_i2c_1_exit(struct device *dev)
 226 {
 227         mxc_gpio_release_multiple_pins(mxc_i2c1_pins, ARRAY_SIZE(mxc_i2c1_pins));
 228 }
 229
 230 static struct imxi2c_platform_data pcm038_i2c_1_data = {
 231         .bitrate = 100000,
 232         .init = pcm038_i2c_1_init,
 233         .exit = pcm038_i2c_1_exit,
 234 };
 235
 236 static struct at24_platform_data board_eeprom = {
 237         .byte_len = 4096,
 238         .page_size = 32,
 239         .flags = AT24_FLAG_ADDR16,
 240 };
 241
 242 static struct i2c_board_info pcm038_i2c_devices[] = {
 243         [0] = {
 244                 I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
 245                 .platform_data = &board_eeprom,
 246         },
 247         [1] = {
 248                 I2C_BOARD_INFO("rtc-pcf8563", 0x51),
 249                 .type = "pcf8563"
 250         },
 251         [2] = {
 252                 I2C_BOARD_INFO("lm75", 0x4a),
 253                 .type = "lm75"
 254         }
 255 };
 256 #endif
 257
 258 static void __init pcm038_init(void)
 259 {
 260         gpio_fec_active();
 261         pcm038_init_sram();
 262
 263         mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
 264         mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
 265         mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
 266
 267         mxc_gpio_mode(PE16_AF_OWIRE);
 268         mxc_register_device(&mxc_nand_device, &pcm038_nand_board_info);
 269
 270 #ifdef CONFIG_I2C_IMX
 271         /* only the i2c master 1 is used on this CPU card */
 272         i2c_register_board_info(1, pcm038_i2c_devices,
 273                                 ARRAY_SIZE(pcm038_i2c_devices));
 274
 275         mxc_register_device(&mxc_i2c_device1, &pcm038_i2c_1_data);
 276 #endif
 277
 278         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 279
 280 #ifdef CONFIG_MACH_PCM970_BASEBOARD
 281         pcm970_baseboard_init();
 282 #endif
 283 }
 284
 285 static void __init pcm038_timer_init(void)
 286 {
 287         mx27_clocks_init(26000000);
 288 }
 289
 290 static struct sys_timer pcm038_timer = {
 291         .init = pcm038_timer_init,
 292 };
 293
 294 MACHINE_START(PCM038, "phyCORE-i.MX27")
 295         .phys_io        = AIPI_BASE_ADDR,
 296         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 297         .boot_params    = PHYS_OFFSET + 0x100,
 298         .map_io         = mxc_map_io,
 299         .init_irq       = mxc_init_irq,
 300         .init_machine   = pcm038_init,
 301         .timer          = &pcm038_timer,
 302 MACHINE_END