arch/arm/plat-mxc/irq.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA  02110-1301, USA.
  18  */
  19
  20 #include <linux/module.h>
  21 #include <linux/irq.h>
  22 #include <linux/io.h>
  23 #include <mach/common.h>
  24 #include <asm/mach/irq.h>
  25 #include <mach/hardware.h>
  26
  27 #define AVIC_BASE               IO_ADDRESS(AVIC_BASE_ADDR)
  28 #define AVIC_INTCNTL            (AVIC_BASE + 0x00)      /* int control reg */
  29 #define AVIC_NIMASK             (AVIC_BASE + 0x04)      /* int mask reg */
  30 #define AVIC_INTENNUM           (AVIC_BASE + 0x08)      /* int enable number reg */
  31 #define AVIC_INTDISNUM          (AVIC_BASE + 0x0C)      /* int disable number reg */
  32 #define AVIC_INTENABLEH         (AVIC_BASE + 0x10)      /* int enable reg high */
  33 #define AVIC_INTENABLEL         (AVIC_BASE + 0x14)      /* int enable reg low */
  34 #define AVIC_INTTYPEH           (AVIC_BASE + 0x18)      /* int type reg high */
  35 #define AVIC_INTTYPEL           (AVIC_BASE + 0x1C)      /* int type reg low */
  36 #define AVIC_NIPRIORITY(x)      (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
  37 #define AVIC_NIVECSR            (AVIC_BASE + 0x40)      /* norm int vector/status */
  38 #define AVIC_FIVECSR            (AVIC_BASE + 0x44)      /* fast int vector/status */
  39 #define AVIC_INTSRCH            (AVIC_BASE + 0x48)      /* int source reg high */
  40 #define AVIC_INTSRCL            (AVIC_BASE + 0x4C)      /* int source reg low */
  41 #define AVIC_INTFRCH            (AVIC_BASE + 0x50)      /* int force reg high */
  42 #define AVIC_INTFRCL            (AVIC_BASE + 0x54)      /* int force reg low */
  43 #define AVIC_NIPNDH             (AVIC_BASE + 0x58)      /* norm int pending high */
  44 #define AVIC_NIPNDL             (AVIC_BASE + 0x5C)      /* norm int pending low */
  45 #define AVIC_FIPNDH             (AVIC_BASE + 0x60)      /* fast int pending high */
  46 #define AVIC_FIPNDL             (AVIC_BASE + 0x64)      /* fast int pending low */
  47
  48 #define SYSTEM_PREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x20)
  49 #define SYSTEM_SREV_REG         IO_ADDRESS(IIM_BASE_ADDR + 0x24)
  50 #define IIM_PROD_REV_SH         3
  51 #define IIM_PROD_REV_LEN        5
  52
  53 int imx_irq_set_priority(unsigned char irq, unsigned char prio)
  54 {
  55 #ifdef CONFIG_MXC_IRQ_PRIOR
  56         unsigned int temp;
  57         unsigned int mask = 0x0F << irq % 8 * 4;
  58
  59         if (irq >= MXC_INTERNAL_IRQS)
  60                 return -EINVAL;;
  61
  62         temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
  63         temp &= ~mask;
  64         temp |= prio & mask;
  65
  66         __raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
  67
  68         return 0;
  69 #else
  70         return -ENOSYS;
  71 #endif
  72 }
  73 EXPORT_SYMBOL(imx_irq_set_priority);
  74
  75 #ifdef CONFIG_FIQ
  76 int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
  77 {
  78         unsigned int irqt;
  79
  80         if (irq >= MXC_INTERNAL_IRQS)
  81                 return -EINVAL;
  82
  83         if (irq < MXC_INTERNAL_IRQS / 2) {
  84                 irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
  85                 __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
  86         } else {
  87                 irq -= MXC_INTERNAL_IRQS / 2;
  88                 irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
  89                 __raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
  90         }
  91
  92         return 0;
  93 }
  94 EXPORT_SYMBOL(mxc_set_irq_fiq);
  95 #endif /* CONFIG_FIQ */
  96
  97 /* Disable interrupt number "irq" in the AVIC */
  98 static void mxc_mask_irq(unsigned int irq)
  99 {
 100         __raw_writel(irq, AVIC_INTDISNUM);
 101 }
 102
 103 /* Enable interrupt number "irq" in the AVIC */
 104 static void mxc_unmask_irq(unsigned int irq)
 105 {
 106         __raw_writel(irq, AVIC_INTENNUM);
 107 }
 108
 109 static struct irq_chip mxc_avic_chip = {
 110         .ack = mxc_mask_irq,
 111         .mask = mxc_mask_irq,
 112         .unmask = mxc_unmask_irq,
 113 };
 114
 115 /*
 116  * This function initializes the AVIC hardware and disables all the
 117  * interrupts. It registers the interrupt enable and disable functions
 118  * to the kernel for each interrupt source.
 119  */
 120 void __init mxc_init_irq(void)
 121 {
 122         int i;
 123
 124         /* put the AVIC into the reset value with
 125          * all interrupts disabled
 126          */
 127         __raw_writel(0, AVIC_INTCNTL);
 128         __raw_writel(0x1f, AVIC_NIMASK);
 129
 130         /* disable all interrupts */
 131         __raw_writel(0, AVIC_INTENABLEH);
 132         __raw_writel(0, AVIC_INTENABLEL);
 133
 134         /* all IRQ no FIQ */
 135         __raw_writel(0, AVIC_INTTYPEH);
 136         __raw_writel(0, AVIC_INTTYPEL);
 137         for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
 138                 set_irq_chip(i, &mxc_avic_chip);
 139                 set_irq_handler(i, handle_level_irq);
 140                 set_irq_flags(i, IRQF_VALID);
 141         }
 142
 143         /* Set default priority value (0) for all IRQ's */
 144         for (i = 0; i < 8; i++)
 145                 __raw_writel(0, AVIC_NIPRIORITY(i));
 146
 147         /* init architectures chained interrupt handler */
 148         mxc_register_gpios();
 149
 150 #ifdef CONFIG_FIQ
 151         /* Initialize FIQ */
 152         init_FIQ();
 153 #endif
 154
 155         printk(KERN_INFO "MXC IRQ initialized\n");
 156 }