arch/blackfin/include/asm/mem_init.h

   1 /*
   2  * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #if defined(EBIU_SDGCTL)
  10 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
  11     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
  12     defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
  13     defined(CONFIG_MEM_GENERIC_BOARD) || \
  14     defined(CONFIG_MEM_MT48LC32M8A2_75) || \
  15     defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
  16     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
  17     defined(CONFIG_MEM_MT48LC32M8A2_75)
  18 #if (CONFIG_SCLK_HZ > 119402985)
  19 #define SDRAM_tRP       TRP_2
  20 #define SDRAM_tRP_num   2
  21 #define SDRAM_tRAS      TRAS_7
  22 #define SDRAM_tRAS_num  7
  23 #define SDRAM_tRCD      TRCD_2
  24 #define SDRAM_tWR       TWR_2
  25 #endif
  26 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
  27 #define SDRAM_tRP       TRP_2
  28 #define SDRAM_tRP_num   2
  29 #define SDRAM_tRAS      TRAS_6
  30 #define SDRAM_tRAS_num  6
  31 #define SDRAM_tRCD      TRCD_2
  32 #define SDRAM_tWR       TWR_2
  33 #endif
  34 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
  35 #define SDRAM_tRP       TRP_2
  36 #define SDRAM_tRP_num   2
  37 #define SDRAM_tRAS      TRAS_5
  38 #define SDRAM_tRAS_num  5
  39 #define SDRAM_tRCD      TRCD_2
  40 #define SDRAM_tWR       TWR_2
  41 #endif
  42 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
  43 #define SDRAM_tRP       TRP_2
  44 #define SDRAM_tRP_num   2
  45 #define SDRAM_tRAS      TRAS_4
  46 #define SDRAM_tRAS_num  4
  47 #define SDRAM_tRCD      TRCD_2
  48 #define SDRAM_tWR       TWR_2
  49 #endif
  50 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
  51 #define SDRAM_tRP       TRP_2
  52 #define SDRAM_tRP_num   2
  53 #define SDRAM_tRAS      TRAS_3
  54 #define SDRAM_tRAS_num  3
  55 #define SDRAM_tRCD      TRCD_2
  56 #define SDRAM_tWR       TWR_2
  57 #endif
  58 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
  59 #define SDRAM_tRP       TRP_1
  60 #define SDRAM_tRP_num   1
  61 #define SDRAM_tRAS      TRAS_4
  62 #define SDRAM_tRAS_num  3
  63 #define SDRAM_tRCD      TRCD_1
  64 #define SDRAM_tWR       TWR_2
  65 #endif
  66 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
  67 #define SDRAM_tRP       TRP_1
  68 #define SDRAM_tRP_num   1
  69 #define SDRAM_tRAS      TRAS_3
  70 #define SDRAM_tRAS_num  3
  71 #define SDRAM_tRCD      TRCD_1
  72 #define SDRAM_tWR       TWR_2
  73 #endif
  74 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
  75 #define SDRAM_tRP       TRP_1
  76 #define SDRAM_tRP_num   1
  77 #define SDRAM_tRAS      TRAS_2
  78 #define SDRAM_tRAS_num  2
  79 #define SDRAM_tRCD      TRCD_1
  80 #define SDRAM_tWR       TWR_2
  81 #endif
  82 #if (CONFIG_SCLK_HZ <= 29850746)
  83 #define SDRAM_tRP       TRP_1
  84 #define SDRAM_tRP_num   1
  85 #define SDRAM_tRAS      TRAS_1
  86 #define SDRAM_tRAS_num  1
  87 #define SDRAM_tRCD      TRCD_1
  88 #define SDRAM_tWR       TWR_2
  89 #endif
  90 #endif
  91
  92 #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
  93     defined(CONFIG_MEM_MT48LC8M32B2B5_7)
  94   /*SDRAM INFORMATION: */
  95 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
  96 #define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
  97 #define SDRAM_CL    CL_3
  98 #endif
  99
 100 #if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
 101     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
 102     defined(CONFIG_MEM_GENERIC_BOARD) || \
 103     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
 104     defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
 105     defined(CONFIG_MEM_MT48LC32M8A2_75)
 106   /*SDRAM INFORMATION: */
 107 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 108 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 109 #define SDRAM_CL    CL_3
 110 #endif
 111
 112
 113 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
 114 /* Equation from section 17 (p17-46) of BF533 HRM */
 115 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 116
 117 /* Enable SCLK Out */
 118 #define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
 119 #else
 120 #define mem_SDRRC       CONFIG_MEM_SDRRC
 121 #define mem_SDGCTL      CONFIG_MEM_SDGCTL
 122 #endif
 123 #endif
 124
 125
 126 #if defined(EBIU_DDRCTL0)
 127 #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
 128 #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
 129 #define DDR_CLK_HZ(x)   (1000*1000*1000/x)
 130
 131 #if defined(CONFIG_MEM_MT46V32M16_6T)
 132 #define DDR_SIZE        DEVSZ_512
 133 #define DDR_WIDTH       DEVWD_16
 134 #define DDR_MAX_tCK     13
 135
 136 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
 137 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
 138 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
 139 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
 140 #define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
 141
 142 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
 143 #define DDR_tWTR        DDR_TWTR(1)
 144 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
 145 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 146 #endif
 147
 148 #if defined(CONFIG_MEM_MT46V32M16_5B)
 149 #define DDR_SIZE        DEVSZ_512
 150 #define DDR_WIDTH       DEVWD_16
 151 #define DDR_MAX_tCK     13
 152
 153 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
 154 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
 155 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
 156 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
 157 #define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
 158
 159 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
 160 #define DDR_tWTR        DDR_TWTR(2)
 161 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
 162 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 163 #endif
 164
 165 #if defined(CONFIG_MEM_GENERIC_BOARD)
 166 #define DDR_SIZE        DEVSZ_512
 167 #define DDR_WIDTH       DEVWD_16
 168 #define DDR_MAX_tCK     13
 169
 170 #define DDR_tRCD        DDR_TRCD(3)
 171 #define DDR_tWTR        DDR_TWTR(2)
 172 #define DDR_tWR         DDR_TWR(2)
 173 #define DDR_tMRD        DDR_TMRD(2)
 174 #define DDR_tRP         DDR_TRP(3)
 175 #define DDR_tRAS        DDR_TRAS(7)
 176 #define DDR_tRC         DDR_TRC(10)
 177 #define DDR_tRFC        DDR_TRFC(12)
 178 #define DDR_tREFI       DDR_TREFI(1288)
 179 #endif
 180
 181 #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
 182 # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
 183 #elif(CONFIG_SCLK_HZ <= 133333333)
 184 # define        DDR_CL          CL_2
 185 #else
 186 # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
 187 #endif
 188
 189 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
 190 #define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
 191 #define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
 192                         | DDR_tMRD | DDR_tWR | DDR_tRCD)
 193 #define mem_DDRCTL2     DDR_CL
 194 #else
 195 #define mem_DDRCTL0     CONFIG_MEM_DDRCTL0
 196 #define mem_DDRCTL1     CONFIG_MEM_DDRCTL1
 197 #define mem_DDRCTL2     CONFIG_MEM_DDRCTL2
 198 #endif
 199 #endif
 200
 201 #if defined CONFIG_CLKIN_HALF
 202 #define CLKIN_HALF       1
 203 #else
 204 #define CLKIN_HALF       0
 205 #endif
 206
 207 #if defined CONFIG_PLL_BYPASS
 208 #define PLL_BYPASS      1
 209 #else
 210 #define PLL_BYPASS       0
 211 #endif
 212
 213 /***************************************Currently Not Being Used *********************************/
 214
 215 #if defined(CONFIG_FLASH_SPEED_BWAT) && \
 216 defined(CONFIG_FLASH_SPEED_BRAT) && \
 217 defined(CONFIG_FLASH_SPEED_BHT) && \
 218 defined(CONFIG_FLASH_SPEED_BST) && \
 219 defined(CONFIG_FLASH_SPEED_BTT)
 220
 221 #define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 222 #define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 223 #define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
 224 #define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 225 #define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 226
 227 #if (flash_EBIU_AMBCTL_TT > 3)
 228 #define flash_EBIU_AMBCTL0_TT   B0TT_4
 229 #endif
 230 #if (flash_EBIU_AMBCTL_TT == 3)
 231 #define flash_EBIU_AMBCTL0_TT   B0TT_3
 232 #endif
 233 #if (flash_EBIU_AMBCTL_TT == 2)
 234 #define flash_EBIU_AMBCTL0_TT   B0TT_2
 235 #endif
 236 #if (flash_EBIU_AMBCTL_TT < 2)
 237 #define flash_EBIU_AMBCTL0_TT   B0TT_1
 238 #endif
 239
 240 #if (flash_EBIU_AMBCTL_ST > 3)
 241 #define flash_EBIU_AMBCTL0_ST   B0ST_4
 242 #endif
 243 #if (flash_EBIU_AMBCTL_ST == 3)
 244 #define flash_EBIU_AMBCTL0_ST   B0ST_3
 245 #endif
 246 #if (flash_EBIU_AMBCTL_ST == 2)
 247 #define flash_EBIU_AMBCTL0_ST   B0ST_2
 248 #endif
 249 #if (flash_EBIU_AMBCTL_ST < 2)
 250 #define flash_EBIU_AMBCTL0_ST   B0ST_1
 251 #endif
 252
 253 #if (flash_EBIU_AMBCTL_HT > 2)
 254 #define flash_EBIU_AMBCTL0_HT   B0HT_3
 255 #endif
 256 #if (flash_EBIU_AMBCTL_HT == 2)
 257 #define flash_EBIU_AMBCTL0_HT   B0HT_2
 258 #endif
 259 #if (flash_EBIU_AMBCTL_HT == 1)
 260 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 261 #endif
 262 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
 263 #define flash_EBIU_AMBCTL0_HT   B0HT_0
 264 #endif
 265 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
 266 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 267 #endif
 268
 269 #if (flash_EBIU_AMBCTL_WAT > 14)
 270 #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
 271 #endif
 272 #if (flash_EBIU_AMBCTL_WAT == 14)
 273 #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
 274 #endif
 275 #if (flash_EBIU_AMBCTL_WAT == 13)
 276 #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
 277 #endif
 278 #if (flash_EBIU_AMBCTL_WAT == 12)
 279 #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
 280 #endif
 281 #if (flash_EBIU_AMBCTL_WAT == 11)
 282 #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
 283 #endif
 284 #if (flash_EBIU_AMBCTL_WAT == 10)
 285 #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
 286 #endif
 287 #if (flash_EBIU_AMBCTL_WAT == 9)
 288 #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
 289 #endif
 290 #if (flash_EBIU_AMBCTL_WAT == 8)
 291 #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
 292 #endif
 293 #if (flash_EBIU_AMBCTL_WAT == 7)
 294 #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
 295 #endif
 296 #if (flash_EBIU_AMBCTL_WAT == 6)
 297 #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
 298 #endif
 299 #if (flash_EBIU_AMBCTL_WAT == 5)
 300 #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
 301 #endif
 302 #if (flash_EBIU_AMBCTL_WAT == 4)
 303 #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
 304 #endif
 305 #if (flash_EBIU_AMBCTL_WAT == 3)
 306 #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
 307 #endif
 308 #if (flash_EBIU_AMBCTL_WAT == 2)
 309 #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
 310 #endif
 311 #if (flash_EBIU_AMBCTL_WAT == 1)
 312 #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
 313 #endif
 314
 315 #if (flash_EBIU_AMBCTL_RAT > 14)
 316 #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
 317 #endif
 318 #if (flash_EBIU_AMBCTL_RAT == 14)
 319 #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
 320 #endif
 321 #if (flash_EBIU_AMBCTL_RAT == 13)
 322 #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
 323 #endif
 324 #if (flash_EBIU_AMBCTL_RAT == 12)
 325 #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
 326 #endif
 327 #if (flash_EBIU_AMBCTL_RAT == 11)
 328 #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
 329 #endif
 330 #if (flash_EBIU_AMBCTL_RAT == 10)
 331 #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
 332 #endif
 333 #if (flash_EBIU_AMBCTL_RAT == 9)
 334 #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
 335 #endif
 336 #if (flash_EBIU_AMBCTL_RAT == 8)
 337 #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
 338 #endif
 339 #if (flash_EBIU_AMBCTL_RAT == 7)
 340 #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
 341 #endif
 342 #if (flash_EBIU_AMBCTL_RAT == 6)
 343 #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
 344 #endif
 345 #if (flash_EBIU_AMBCTL_RAT == 5)
 346 #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
 347 #endif
 348 #if (flash_EBIU_AMBCTL_RAT == 4)
 349 #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
 350 #endif
 351 #if (flash_EBIU_AMBCTL_RAT == 3)
 352 #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
 353 #endif
 354 #if (flash_EBIU_AMBCTL_RAT == 2)
 355 #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
 356 #endif
 357 #if (flash_EBIU_AMBCTL_RAT == 1)
 358 #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
 359 #endif
 360
 361 #define flash_EBIU_AMBCTL0  \
 362         (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
 363          flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
 364 #endif