arch/arm/mach-davinci/psc.c

   1 /*
   2  * TI DaVinci Power and Sleep Controller (PSC)
   3  *
   4  * Copyright (C) 2006 Texas Instruments.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program; if not, write to the Free Software
  18  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  *
  20  */
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25
  26 #include <mach/cputype.h>
  27 #include <mach/hardware.h>
  28 #include <mach/psc.h>
  29 #include <mach/mux.h>
  30
  31 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01C41000
  32
  33 /* PSC register offsets */
  34 #define EPCPR           0x070
  35 #define PTCMD           0x120
  36 #define PTSTAT          0x128
  37 #define PDSTAT          0x200
  38 #define PDCTL1          0x304
  39 #define MDSTAT          0x800
  40 #define MDCTL           0xA00
  41
  42 #define MDSTAT_STATE_MASK 0x1f
  43
  44 /* Return nonzero iff the domain's clock is active */
  45 int __init davinci_psc_is_clk_active(unsigned int id)
  46 {
  47         void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
  48         u32 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
  49
  50         /* if clocked, state can be "Enable" or "SyncReset" */
  51         return mdstat & BIT(12);
  52 }
  53
  54 /* Enable or disable a PSC domain */
  55 void davinci_psc_config(unsigned int domain, unsigned int id, char enable)
  56 {
  57         u32 epcpr, ptcmd, ptstat, pdstat, pdctl1, mdstat, mdctl;
  58         void __iomem *psc_base = IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE);
  59         u32 next_state = enable ? 0x3 : 0x2; /* 0x3 enables, 0x2 disables */
  60
  61         mdctl = __raw_readl(psc_base + MDCTL + 4 * id);
  62         mdctl &= ~MDSTAT_STATE_MASK;
  63         mdctl |= next_state;
  64         __raw_writel(mdctl, psc_base + MDCTL + 4 * id);
  65
  66         pdstat = __raw_readl(psc_base + PDSTAT);
  67         if ((pdstat & 0x00000001) == 0) {
  68                 pdctl1 = __raw_readl(psc_base + PDCTL1);
  69                 pdctl1 |= 0x1;
  70                 __raw_writel(pdctl1, psc_base + PDCTL1);
  71
  72                 ptcmd = 1 << domain;
  73                 __raw_writel(ptcmd, psc_base + PTCMD);
  74
  75                 do {
  76                         epcpr = __raw_readl(psc_base + EPCPR);
  77                 } while ((((epcpr >> domain) & 1) == 0));
  78
  79                 pdctl1 = __raw_readl(psc_base + PDCTL1);
  80                 pdctl1 |= 0x100;
  81                 __raw_writel(pdctl1, psc_base + PDCTL1);
  82
  83                 do {
  84                         ptstat = __raw_readl(psc_base +
  85                                                PTSTAT);
  86                 } while (!(((ptstat >> domain) & 1) == 0));
  87         } else {
  88                 ptcmd = 1 << domain;
  89                 __raw_writel(ptcmd, psc_base + PTCMD);
  90
  91                 do {
  92                         ptstat = __raw_readl(psc_base + PTSTAT);
  93                 } while (!(((ptstat >> domain) & 1) == 0));
  94         }
  95
  96         do {
  97                 mdstat = __raw_readl(psc_base + MDSTAT + 4 * id);
  98         } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
  99 }