arch/arm/mach-omap1/irq.c

   1 /*
   2  * linux/arch/arm/mach-omap1/irq.c
   3  *
   4  * Interrupt handler for all OMAP boards
   5  *
   6  * Copyright (C) 2004 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  * Major cleanups by Juha Yrjölä <juha.yrjola@nokia.com>
   9  *
  10  * Completely re-written to support various OMAP chips with bank specific
  11  * interrupt handlers.
  12  *
  13  * Some snippets of the code taken from the older OMAP interrupt handler
  14  * Copyright (C) 2001 RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  15  *
  16  * GPIO interrupt handler moved to gpio.c by Juha Yrjola
  17  *
  18  * This program is free software; you can redistribute it and/or modify it
  19  * under the terms of the GNU General Public License as published by the
  20  * Free Software Foundation; either version 2 of the License, or (at your
  21  * option) any later version.
  22  *
  23  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  24  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  25  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  26  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  27  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  28  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  29  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  30  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  31  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  32  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * You should have received a copy of the  GNU General Public License along
  35  * with this program; if not, write  to the Free Software Foundation, Inc.,
  36  * 675 Mass Ave, Cambridge, MA 02139, USA.
  37  */
  38
  39 #include <linux/init.h>
  40 #include <linux/module.h>
  41 #include <linux/sched.h>
  42 #include <linux/interrupt.h>
  43 #include <linux/io.h>
  44
  45 #include <mach/hardware.h>
  46 #include <asm/irq.h>
  47 #include <asm/mach/irq.h>
  48 #include <mach/gpio.h>
  49 #include <mach/cpu.h>
  50
  51 #define IRQ_BANK(irq) ((irq) >> 5)
  52 #define IRQ_BIT(irq)  ((irq) & 0x1f)
  53
  54 struct omap_irq_bank {
  55         unsigned long base_reg;
  56         unsigned long trigger_map;
  57         unsigned long wake_enable;
  58 };
  59
  60 static unsigned int irq_bank_count;
  61 static struct omap_irq_bank *irq_banks;
  62
  63 static inline unsigned int irq_bank_readl(int bank, int offset)
  64 {
  65         return omap_readl(irq_banks[bank].base_reg + offset);
  66 }
  67
  68 static inline void irq_bank_writel(unsigned long value, int bank, int offset)
  69 {
  70         omap_writel(value, irq_banks[bank].base_reg + offset);
  71 }
  72
  73 static void omap_ack_irq(unsigned int irq)
  74 {
  75         if (irq > 31)
  76                 omap_writel(0x1, OMAP_IH2_BASE + IRQ_CONTROL_REG_OFFSET);
  77
  78         omap_writel(0x1, OMAP_IH1_BASE + IRQ_CONTROL_REG_OFFSET);
  79 }
  80
  81 static void omap_mask_irq(unsigned int irq)
  82 {
  83         int bank = IRQ_BANK(irq);
  84         u32 l;
  85
  86         l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
  87         l |= 1 << IRQ_BIT(irq);
  88         omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
  89 }
  90
  91 static void omap_unmask_irq(unsigned int irq)
  92 {
  93         int bank = IRQ_BANK(irq);
  94         u32 l;
  95
  96         l = omap_readl(irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
  97         l &= ~(1 << IRQ_BIT(irq));
  98         omap_writel(l, irq_banks[bank].base_reg + IRQ_MIR_REG_OFFSET);
  99 }
 100
 101 static void omap_mask_ack_irq(unsigned int irq)
 102 {
 103         omap_mask_irq(irq);
 104         omap_ack_irq(irq);
 105 }
 106
 107 static int omap_wake_irq(unsigned int irq, unsigned int enable)
 108 {
 109         int bank = IRQ_BANK(irq);
 110
 111         if (enable)
 112                 irq_banks[bank].wake_enable |= IRQ_BIT(irq);
 113         else
 114                 irq_banks[bank].wake_enable &= ~IRQ_BIT(irq);
 115
 116         return 0;
 117 }
 118
 119
 120 /*
 121  * Allows tuning the IRQ type and priority
 122  *
 123  * NOTE: There is currently no OMAP fiq handler for Linux. Read the
 124  *       mailing list threads on FIQ handlers if you are planning to
 125  *       add a FIQ handler for OMAP.
 126  */
 127 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger)
 128 {
 129         signed int bank;
 130         unsigned long val, offset;
 131
 132         bank = IRQ_BANK(irq);
 133         /* FIQ is only available on bank 0 interrupts */
 134         fiq = bank ? 0 : (fiq & 0x1);
 135         val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1);
 136         offset = IRQ_ILR0_REG_OFFSET + IRQ_BIT(irq) * 0x4;
 137         irq_bank_writel(val, bank, offset);
 138 }
 139
 140 #ifdef CONFIG_ARCH_OMAP730
 141 static struct omap_irq_bank omap730_irq_banks[] = {
 142         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
 143         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
 144         { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
 145 };
 146 #endif
 147
 148 #ifdef CONFIG_ARCH_OMAP850
 149 static struct omap_irq_bank omap850_irq_banks[] = {
 150         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3f8e22f },
 151         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb9c1f2 },
 152         { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0x800040f3 },
 153 };
 154 #endif
 155
 156 #ifdef CONFIG_ARCH_OMAP15XX
 157 static struct omap_irq_bank omap1510_irq_banks[] = {
 158         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3febfff },
 159         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xffbfffed },
 160 };
 161 static struct omap_irq_bank omap310_irq_banks[] = {
 162         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3faefc3 },
 163         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0x65b3c061 },
 164 };
 165 #endif
 166
 167 #if defined(CONFIG_ARCH_OMAP16XX)
 168
 169 static struct omap_irq_bank omap1610_irq_banks[] = {
 170         { .base_reg = OMAP_IH1_BASE,            .trigger_map = 0xb3fefe8f },
 171         { .base_reg = OMAP_IH2_BASE,            .trigger_map = 0xfdb7c1fd },
 172         { .base_reg = OMAP_IH2_BASE + 0x100,    .trigger_map = 0xffffb7ff },
 173         { .base_reg = OMAP_IH2_BASE + 0x200,    .trigger_map = 0xffffffff },
 174 };
 175 #endif
 176
 177 static struct irq_chip omap_irq_chip = {
 178         .name           = "MPU",
 179         .ack            = omap_mask_ack_irq,
 180         .mask           = omap_mask_irq,
 181         .unmask         = omap_unmask_irq,
 182         .set_wake       = omap_wake_irq,
 183 };
 184
 185 void __init omap_init_irq(void)
 186 {
 187         int i, j;
 188
 189 #ifdef CONFIG_ARCH_OMAP730
 190         if (cpu_is_omap730()) {
 191                 irq_banks = omap730_irq_banks;
 192                 irq_bank_count = ARRAY_SIZE(omap730_irq_banks);
 193         }
 194 #endif
 195 #ifdef CONFIG_ARCH_OMAP850
 196         if (cpu_is_omap850()) {
 197                 irq_banks = omap850_irq_banks;
 198                 irq_bank_count = ARRAY_SIZE(omap850_irq_banks);
 199         }
 200 #endif
 201 #ifdef CONFIG_ARCH_OMAP15XX
 202         if (cpu_is_omap1510()) {
 203                 irq_banks = omap1510_irq_banks;
 204                 irq_bank_count = ARRAY_SIZE(omap1510_irq_banks);
 205         }
 206         if (cpu_is_omap310()) {
 207                 irq_banks = omap310_irq_banks;
 208                 irq_bank_count = ARRAY_SIZE(omap310_irq_banks);
 209         }
 210 #endif
 211 #if defined(CONFIG_ARCH_OMAP16XX)
 212         if (cpu_is_omap16xx()) {
 213                 irq_banks = omap1610_irq_banks;
 214                 irq_bank_count = ARRAY_SIZE(omap1610_irq_banks);
 215         }
 216 #endif
 217         printk("Total of %i interrupts in %i interrupt banks\n",
 218                irq_bank_count * 32, irq_bank_count);
 219
 220         /* Mask and clear all interrupts */
 221         for (i = 0; i < irq_bank_count; i++) {
 222                 irq_bank_writel(~0x0, i, IRQ_MIR_REG_OFFSET);
 223                 irq_bank_writel(0x0, i, IRQ_ITR_REG_OFFSET);
 224         }
 225
 226         /* Clear any pending interrupts */
 227         irq_bank_writel(0x03, 0, IRQ_CONTROL_REG_OFFSET);
 228         irq_bank_writel(0x03, 1, IRQ_CONTROL_REG_OFFSET);
 229
 230         /* Enable interrupts in global mask */
 231         if (cpu_is_omap7xx())
 232                 irq_bank_writel(0x0, 0, IRQ_GMR_REG_OFFSET);
 233
 234         /* Install the interrupt handlers for each bank */
 235         for (i = 0; i < irq_bank_count; i++) {
 236                 for (j = i * 32; j < (i + 1) * 32; j++) {
 237                         int irq_trigger;
 238
 239                         irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
 240                         omap_irq_set_cfg(j, 0, 0, irq_trigger);
 241
 242                         set_irq_chip(j, &omap_irq_chip);
 243                         set_irq_handler(j, handle_level_irq);
 244                         set_irq_flags(j, IRQF_VALID);
 245                 }
 246         }
 247
 248         /* Unmask level 2 handler */
 249
 250         if (cpu_is_omap730())
 251                 omap_unmask_irq(INT_730_IH2_IRQ);
 252         else if (cpu_is_omap850())
 253                 omap_unmask_irq(INT_850_IH2_IRQ);
 254         else if (cpu_is_omap15xx())
 255                 omap_unmask_irq(INT_1510_IH2_IRQ);
 256         else if (cpu_is_omap16xx())
 257                 omap_unmask_irq(INT_1610_IH2_IRQ);
 258 }