OMAP3: PM: Ensure MUSB block can idle when driver not loaded
[linux-ginger.git] / arch / arm / mach-omap1 / pm.c
blob9774c1f5311e075e34cae1bd12ebb05999688a30
1 /*
2 * linux/arch/arm/mach-omap1/pm.c
4 * OMAP Power Management Routines
6 * Original code for the SA11x0:
7 * Copyright (c) 2001 Cliff Brake <cbrake@accelent.com>
9 * Modified for the PXA250 by Nicolas Pitre:
10 * Copyright (c) 2002 Monta Vista Software, Inc.
12 * Modified for the OMAP1510 by David Singleton:
13 * Copyright (c) 2002 Monta Vista Software, Inc.
15 * Cleanup 2004 for OMAP1510/1610 by Dirk Behme <dirk.behme@de.bosch.com>
17 * This program is free software; you can redistribute it and/or modify it
18 * under the terms of the GNU General Public License as published by the
19 * Free Software Foundation; either version 2 of the License, or (at your
20 * option) any later version.
22 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * You should have received a copy of the GNU General Public License along
34 * with this program; if not, write to the Free Software Foundation, Inc.,
35 * 675 Mass Ave, Cambridge, MA 02139, USA.
38 #include <linux/suspend.h>
39 #include <linux/sched.h>
40 #include <linux/proc_fs.h>
41 #include <linux/interrupt.h>
42 #include <linux/sysfs.h>
43 #include <linux/module.h>
44 #include <linux/io.h>
46 #include <asm/irq.h>
47 #include <asm/atomic.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/irq.h>
51 #include <mach/cpu.h>
52 #include <mach/irqs.h>
53 #include <mach/clock.h>
54 #include <mach/sram.h>
55 #include <mach/tc.h>
56 #include <mach/pm.h>
57 #include <mach/mux.h>
58 #include <mach/dma.h>
59 #include <mach/dmtimer.h>
61 static unsigned int arm_sleep_save[ARM_SLEEP_SAVE_SIZE];
62 static unsigned short dsp_sleep_save[DSP_SLEEP_SAVE_SIZE];
63 static unsigned short ulpd_sleep_save[ULPD_SLEEP_SAVE_SIZE];
64 static unsigned int mpui730_sleep_save[MPUI730_SLEEP_SAVE_SIZE];
65 static unsigned int mpui1510_sleep_save[MPUI1510_SLEEP_SAVE_SIZE];
66 static unsigned int mpui1610_sleep_save[MPUI1610_SLEEP_SAVE_SIZE];
68 #ifdef CONFIG_OMAP_32K_TIMER
70 static unsigned short enable_dyn_sleep = 1;
72 static ssize_t idle_show(struct kobject *kobj, struct kobj_attribute *attr,
73 char *buf)
75 return sprintf(buf, "%hu\n", enable_dyn_sleep);
78 static ssize_t idle_store(struct kobject *kobj, struct kobj_attribute *attr,
79 const char * buf, size_t n)
81 unsigned short value;
82 if (sscanf(buf, "%hu", &value) != 1 ||
83 (value != 0 && value != 1)) {
84 printk(KERN_ERR "idle_sleep_store: Invalid value\n");
85 return -EINVAL;
87 enable_dyn_sleep = value;
88 return n;
91 static struct kobj_attribute sleep_while_idle_attr =
92 __ATTR(sleep_while_idle, 0644, idle_show, idle_store);
94 #endif
96 static void (*omap_sram_suspend)(unsigned long r0, unsigned long r1) = NULL;
99 * Let's power down on idle, but only if we are really
100 * idle, because once we start down the path of
101 * going idle we continue to do idle even if we get
102 * a clock tick interrupt . .
104 void omap_pm_idle(void)
106 extern __u32 arm_idlect1_mask;
107 __u32 use_idlect1 = arm_idlect1_mask;
108 int do_sleep = 0;
110 local_irq_disable();
111 local_fiq_disable();
112 if (need_resched()) {
113 local_fiq_enable();
114 local_irq_enable();
115 return;
118 #ifdef CONFIG_OMAP_MPU_TIMER
119 #warning Enable 32kHz OS timer in order to allow sleep states in idle
120 use_idlect1 = use_idlect1 & ~(1 << 9);
121 #else
123 while (enable_dyn_sleep) {
125 #ifdef CONFIG_CBUS_TAHVO_USB
126 extern int vbus_active;
127 /* Clock requirements? */
128 if (vbus_active)
129 break;
130 #endif
131 do_sleep = 1;
132 break;
135 #endif
137 #ifdef CONFIG_OMAP_DM_TIMER
138 use_idlect1 = omap_dm_timer_modify_idlect_mask(use_idlect1);
139 #endif
141 if (omap_dma_running())
142 use_idlect1 &= ~(1 << 6);
144 /* We should be able to remove the do_sleep variable and multiple
145 * tests above as soon as drivers, timer and DMA code have been fixed.
146 * Even the sleep block count should become obsolete. */
147 if ((use_idlect1 != ~0) || !do_sleep) {
149 __u32 saved_idlect1 = omap_readl(ARM_IDLECT1);
150 if (cpu_is_omap15xx())
151 use_idlect1 &= OMAP1510_BIG_SLEEP_REQUEST;
152 else
153 use_idlect1 &= OMAP1610_IDLECT1_SLEEP_VAL;
154 omap_writel(use_idlect1, ARM_IDLECT1);
155 __asm__ volatile ("mcr p15, 0, r0, c7, c0, 4");
156 omap_writel(saved_idlect1, ARM_IDLECT1);
158 local_fiq_enable();
159 local_irq_enable();
160 return;
162 omap_sram_suspend(omap_readl(ARM_IDLECT1),
163 omap_readl(ARM_IDLECT2));
165 local_fiq_enable();
166 local_irq_enable();
170 * Configuration of the wakeup event is board specific. For the
171 * moment we put it into this helper function. Later it may move
172 * to board specific files.
174 static void omap_pm_wakeup_setup(void)
176 u32 level1_wake = 0;
177 u32 level2_wake = OMAP_IRQ_BIT(INT_UART2);
180 * Turn off all interrupts except GPIO bank 1, L1-2nd level cascade,
181 * and the L2 wakeup interrupts: keypad and UART2. Note that the
182 * drivers must still separately call omap_set_gpio_wakeup() to
183 * wake up to a GPIO interrupt.
185 if (cpu_is_omap730())
186 level1_wake = OMAP_IRQ_BIT(INT_730_GPIO_BANK1) |
187 OMAP_IRQ_BIT(INT_730_IH2_IRQ);
188 else if (cpu_is_omap15xx())
189 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
190 OMAP_IRQ_BIT(INT_1510_IH2_IRQ);
191 else if (cpu_is_omap16xx())
192 level1_wake = OMAP_IRQ_BIT(INT_GPIO_BANK1) |
193 OMAP_IRQ_BIT(INT_1610_IH2_IRQ);
195 omap_writel(~level1_wake, OMAP_IH1_MIR);
197 if (cpu_is_omap730()) {
198 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
199 omap_writel(~(OMAP_IRQ_BIT(INT_730_WAKE_UP_REQ) |
200 OMAP_IRQ_BIT(INT_730_MPUIO_KEYPAD)),
201 OMAP_IH2_1_MIR);
202 } else if (cpu_is_omap15xx()) {
203 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
204 omap_writel(~level2_wake, OMAP_IH2_MIR);
205 } else if (cpu_is_omap16xx()) {
206 level2_wake |= OMAP_IRQ_BIT(INT_KEYBOARD);
207 omap_writel(~level2_wake, OMAP_IH2_0_MIR);
209 /* INT_1610_WAKE_UP_REQ is needed for GPIO wakeup... */
210 omap_writel(~OMAP_IRQ_BIT(INT_1610_WAKE_UP_REQ),
211 OMAP_IH2_1_MIR);
212 omap_writel(~0x0, OMAP_IH2_2_MIR);
213 omap_writel(~0x0, OMAP_IH2_3_MIR);
216 /* New IRQ agreement, recalculate in cascade order */
217 omap_writel(1, OMAP_IH2_CONTROL);
218 omap_writel(1, OMAP_IH1_CONTROL);
221 #define EN_DSPCK 13 /* ARM_CKCTL */
222 #define EN_APICK 6 /* ARM_IDLECT2 */
223 #define DSP_EN 1 /* ARM_RSTCT1 */
225 void omap_pm_suspend(void)
227 unsigned long arg0 = 0, arg1 = 0;
229 printk(KERN_INFO "PM: OMAP%x is trying to enter deep sleep...\n",
230 omap_rev());
232 omap_serial_wake_trigger(1);
234 if (!cpu_is_omap15xx())
235 omap_writew(0xffff, ULPD_SOFT_DISABLE_REQ_REG);
238 * Step 1: turn off interrupts (FIXME: NOTE: already disabled)
241 local_irq_disable();
242 local_fiq_disable();
245 * Step 2: save registers
247 * The omap is a strange/beautiful device. The caches, memory
248 * and register state are preserved across power saves.
249 * We have to save and restore very little register state to
250 * idle the omap.
252 * Save interrupt, MPUI, ARM and UPLD control registers.
255 if (cpu_is_omap730()) {
256 MPUI730_SAVE(OMAP_IH1_MIR);
257 MPUI730_SAVE(OMAP_IH2_0_MIR);
258 MPUI730_SAVE(OMAP_IH2_1_MIR);
259 MPUI730_SAVE(MPUI_CTRL);
260 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
261 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
262 MPUI730_SAVE(EMIFS_CONFIG);
263 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
265 } else if (cpu_is_omap15xx()) {
266 MPUI1510_SAVE(OMAP_IH1_MIR);
267 MPUI1510_SAVE(OMAP_IH2_MIR);
268 MPUI1510_SAVE(MPUI_CTRL);
269 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
270 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
271 MPUI1510_SAVE(EMIFS_CONFIG);
272 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
273 } else if (cpu_is_omap16xx()) {
274 MPUI1610_SAVE(OMAP_IH1_MIR);
275 MPUI1610_SAVE(OMAP_IH2_0_MIR);
276 MPUI1610_SAVE(OMAP_IH2_1_MIR);
277 MPUI1610_SAVE(OMAP_IH2_2_MIR);
278 MPUI1610_SAVE(OMAP_IH2_3_MIR);
279 MPUI1610_SAVE(MPUI_CTRL);
280 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
281 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
282 MPUI1610_SAVE(EMIFS_CONFIG);
283 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
286 ARM_SAVE(ARM_CKCTL);
287 ARM_SAVE(ARM_IDLECT1);
288 ARM_SAVE(ARM_IDLECT2);
289 if (!(cpu_is_omap15xx()))
290 ARM_SAVE(ARM_IDLECT3);
291 ARM_SAVE(ARM_EWUPCT);
292 ARM_SAVE(ARM_RSTCT1);
293 ARM_SAVE(ARM_RSTCT2);
294 ARM_SAVE(ARM_SYSST);
295 ULPD_SAVE(ULPD_CLOCK_CTRL);
296 ULPD_SAVE(ULPD_STATUS_REQ);
298 /* (Step 3 removed - we now allow deep sleep by default) */
301 * Step 4: OMAP DSP Shutdown
304 /* stop DSP */
305 omap_writew(omap_readw(ARM_RSTCT1) & ~(1 << DSP_EN), ARM_RSTCT1);
307 /* shut down dsp_ck */
308 if (!cpu_is_omap730())
309 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL);
311 /* temporarily enabling api_ck to access DSP registers */
312 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
314 /* save DSP registers */
315 DSP_SAVE(DSP_IDLECT2);
317 /* Stop all DSP domain clocks */
318 __raw_writew(0, DSP_IDLECT2);
321 * Step 5: Wakeup Event Setup
324 omap_pm_wakeup_setup();
327 * Step 6: ARM and Traffic controller shutdown
330 /* disable ARM watchdog */
331 omap_writel(0x00F5, OMAP_WDT_TIMER_MODE);
332 omap_writel(0x00A0, OMAP_WDT_TIMER_MODE);
335 * Step 6b: ARM and Traffic controller shutdown
337 * Step 6 continues here. Prepare jump to power management
338 * assembly code in internal SRAM.
340 * Since the omap_cpu_suspend routine has been copied to
341 * SRAM, we'll do an indirect procedure call to it and pass the
342 * contents of arm_idlect1 and arm_idlect2 so it can restore
343 * them when it wakes up and it will return.
346 arg0 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT1];
347 arg1 = arm_sleep_save[ARM_SLEEP_SAVE_ARM_IDLECT2];
350 * Step 6c: ARM and Traffic controller shutdown
352 * Jump to assembly code. The processor will stay there
353 * until wake up.
355 omap_sram_suspend(arg0, arg1);
358 * If we are here, processor is woken up!
362 * Restore DSP clocks
365 /* again temporarily enabling api_ck to access DSP registers */
366 omap_writew(omap_readw(ARM_IDLECT2) | 1 << EN_APICK, ARM_IDLECT2);
368 /* Restore DSP domain clocks */
369 DSP_RESTORE(DSP_IDLECT2);
372 * Restore ARM state, except ARM_IDLECT1/2 which omap_cpu_suspend did
375 if (!(cpu_is_omap15xx()))
376 ARM_RESTORE(ARM_IDLECT3);
377 ARM_RESTORE(ARM_CKCTL);
378 ARM_RESTORE(ARM_EWUPCT);
379 ARM_RESTORE(ARM_RSTCT1);
380 ARM_RESTORE(ARM_RSTCT2);
381 ARM_RESTORE(ARM_SYSST);
382 ULPD_RESTORE(ULPD_CLOCK_CTRL);
383 ULPD_RESTORE(ULPD_STATUS_REQ);
385 if (cpu_is_omap730()) {
386 MPUI730_RESTORE(EMIFS_CONFIG);
387 MPUI730_RESTORE(EMIFF_SDRAM_CONFIG);
388 MPUI730_RESTORE(OMAP_IH1_MIR);
389 MPUI730_RESTORE(OMAP_IH2_0_MIR);
390 MPUI730_RESTORE(OMAP_IH2_1_MIR);
391 } else if (cpu_is_omap15xx()) {
392 MPUI1510_RESTORE(MPUI_CTRL);
393 MPUI1510_RESTORE(MPUI_DSP_BOOT_CONFIG);
394 MPUI1510_RESTORE(MPUI_DSP_API_CONFIG);
395 MPUI1510_RESTORE(EMIFS_CONFIG);
396 MPUI1510_RESTORE(EMIFF_SDRAM_CONFIG);
397 MPUI1510_RESTORE(OMAP_IH1_MIR);
398 MPUI1510_RESTORE(OMAP_IH2_MIR);
399 } else if (cpu_is_omap16xx()) {
400 MPUI1610_RESTORE(MPUI_CTRL);
401 MPUI1610_RESTORE(MPUI_DSP_BOOT_CONFIG);
402 MPUI1610_RESTORE(MPUI_DSP_API_CONFIG);
403 MPUI1610_RESTORE(EMIFS_CONFIG);
404 MPUI1610_RESTORE(EMIFF_SDRAM_CONFIG);
406 MPUI1610_RESTORE(OMAP_IH1_MIR);
407 MPUI1610_RESTORE(OMAP_IH2_0_MIR);
408 MPUI1610_RESTORE(OMAP_IH2_1_MIR);
409 MPUI1610_RESTORE(OMAP_IH2_2_MIR);
410 MPUI1610_RESTORE(OMAP_IH2_3_MIR);
413 if (!cpu_is_omap15xx())
414 omap_writew(0, ULPD_SOFT_DISABLE_REQ_REG);
417 * Re-enable interrupts
420 local_irq_enable();
421 local_fiq_enable();
423 omap_serial_wake_trigger(0);
425 printk(KERN_INFO "PM: OMAP%x is re-starting from deep sleep...\n",
426 omap_rev());
429 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
430 static int g_read_completed;
433 * Read system PM registers for debugging
435 static int omap_pm_read_proc(
436 char *page_buffer,
437 char **my_first_byte,
438 off_t virtual_start,
439 int length,
440 int *eof,
441 void *data)
443 int my_buffer_offset = 0;
444 char * const my_base = page_buffer;
446 ARM_SAVE(ARM_CKCTL);
447 ARM_SAVE(ARM_IDLECT1);
448 ARM_SAVE(ARM_IDLECT2);
449 if (!(cpu_is_omap15xx()))
450 ARM_SAVE(ARM_IDLECT3);
451 ARM_SAVE(ARM_EWUPCT);
452 ARM_SAVE(ARM_RSTCT1);
453 ARM_SAVE(ARM_RSTCT2);
454 ARM_SAVE(ARM_SYSST);
456 ULPD_SAVE(ULPD_IT_STATUS);
457 ULPD_SAVE(ULPD_CLOCK_CTRL);
458 ULPD_SAVE(ULPD_SOFT_REQ);
459 ULPD_SAVE(ULPD_STATUS_REQ);
460 ULPD_SAVE(ULPD_DPLL_CTRL);
461 ULPD_SAVE(ULPD_POWER_CTRL);
463 if (cpu_is_omap730()) {
464 MPUI730_SAVE(MPUI_CTRL);
465 MPUI730_SAVE(MPUI_DSP_STATUS);
466 MPUI730_SAVE(MPUI_DSP_BOOT_CONFIG);
467 MPUI730_SAVE(MPUI_DSP_API_CONFIG);
468 MPUI730_SAVE(EMIFF_SDRAM_CONFIG);
469 MPUI730_SAVE(EMIFS_CONFIG);
470 } else if (cpu_is_omap15xx()) {
471 MPUI1510_SAVE(MPUI_CTRL);
472 MPUI1510_SAVE(MPUI_DSP_STATUS);
473 MPUI1510_SAVE(MPUI_DSP_BOOT_CONFIG);
474 MPUI1510_SAVE(MPUI_DSP_API_CONFIG);
475 MPUI1510_SAVE(EMIFF_SDRAM_CONFIG);
476 MPUI1510_SAVE(EMIFS_CONFIG);
477 } else if (cpu_is_omap16xx()) {
478 MPUI1610_SAVE(MPUI_CTRL);
479 MPUI1610_SAVE(MPUI_DSP_STATUS);
480 MPUI1610_SAVE(MPUI_DSP_BOOT_CONFIG);
481 MPUI1610_SAVE(MPUI_DSP_API_CONFIG);
482 MPUI1610_SAVE(EMIFF_SDRAM_CONFIG);
483 MPUI1610_SAVE(EMIFS_CONFIG);
486 if (virtual_start == 0) {
487 g_read_completed = 0;
489 my_buffer_offset += sprintf(my_base + my_buffer_offset,
490 "ARM_CKCTL_REG: 0x%-8x \n"
491 "ARM_IDLECT1_REG: 0x%-8x \n"
492 "ARM_IDLECT2_REG: 0x%-8x \n"
493 "ARM_IDLECT3_REG: 0x%-8x \n"
494 "ARM_EWUPCT_REG: 0x%-8x \n"
495 "ARM_RSTCT1_REG: 0x%-8x \n"
496 "ARM_RSTCT2_REG: 0x%-8x \n"
497 "ARM_SYSST_REG: 0x%-8x \n"
498 "ULPD_IT_STATUS_REG: 0x%-4x \n"
499 "ULPD_CLOCK_CTRL_REG: 0x%-4x \n"
500 "ULPD_SOFT_REQ_REG: 0x%-4x \n"
501 "ULPD_DPLL_CTRL_REG: 0x%-4x \n"
502 "ULPD_STATUS_REQ_REG: 0x%-4x \n"
503 "ULPD_POWER_CTRL_REG: 0x%-4x \n",
504 ARM_SHOW(ARM_CKCTL),
505 ARM_SHOW(ARM_IDLECT1),
506 ARM_SHOW(ARM_IDLECT2),
507 ARM_SHOW(ARM_IDLECT3),
508 ARM_SHOW(ARM_EWUPCT),
509 ARM_SHOW(ARM_RSTCT1),
510 ARM_SHOW(ARM_RSTCT2),
511 ARM_SHOW(ARM_SYSST),
512 ULPD_SHOW(ULPD_IT_STATUS),
513 ULPD_SHOW(ULPD_CLOCK_CTRL),
514 ULPD_SHOW(ULPD_SOFT_REQ),
515 ULPD_SHOW(ULPD_DPLL_CTRL),
516 ULPD_SHOW(ULPD_STATUS_REQ),
517 ULPD_SHOW(ULPD_POWER_CTRL));
519 if (cpu_is_omap730()) {
520 my_buffer_offset += sprintf(my_base + my_buffer_offset,
521 "MPUI730_CTRL_REG 0x%-8x \n"
522 "MPUI730_DSP_STATUS_REG: 0x%-8x \n"
523 "MPUI730_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
524 "MPUI730_DSP_API_CONFIG_REG: 0x%-8x \n"
525 "MPUI730_SDRAM_CONFIG_REG: 0x%-8x \n"
526 "MPUI730_EMIFS_CONFIG_REG: 0x%-8x \n",
527 MPUI730_SHOW(MPUI_CTRL),
528 MPUI730_SHOW(MPUI_DSP_STATUS),
529 MPUI730_SHOW(MPUI_DSP_BOOT_CONFIG),
530 MPUI730_SHOW(MPUI_DSP_API_CONFIG),
531 MPUI730_SHOW(EMIFF_SDRAM_CONFIG),
532 MPUI730_SHOW(EMIFS_CONFIG));
533 } else if (cpu_is_omap15xx()) {
534 my_buffer_offset += sprintf(my_base + my_buffer_offset,
535 "MPUI1510_CTRL_REG 0x%-8x \n"
536 "MPUI1510_DSP_STATUS_REG: 0x%-8x \n"
537 "MPUI1510_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
538 "MPUI1510_DSP_API_CONFIG_REG: 0x%-8x \n"
539 "MPUI1510_SDRAM_CONFIG_REG: 0x%-8x \n"
540 "MPUI1510_EMIFS_CONFIG_REG: 0x%-8x \n",
541 MPUI1510_SHOW(MPUI_CTRL),
542 MPUI1510_SHOW(MPUI_DSP_STATUS),
543 MPUI1510_SHOW(MPUI_DSP_BOOT_CONFIG),
544 MPUI1510_SHOW(MPUI_DSP_API_CONFIG),
545 MPUI1510_SHOW(EMIFF_SDRAM_CONFIG),
546 MPUI1510_SHOW(EMIFS_CONFIG));
547 } else if (cpu_is_omap16xx()) {
548 my_buffer_offset += sprintf(my_base + my_buffer_offset,
549 "MPUI1610_CTRL_REG 0x%-8x \n"
550 "MPUI1610_DSP_STATUS_REG: 0x%-8x \n"
551 "MPUI1610_DSP_BOOT_CONFIG_REG: 0x%-8x \n"
552 "MPUI1610_DSP_API_CONFIG_REG: 0x%-8x \n"
553 "MPUI1610_SDRAM_CONFIG_REG: 0x%-8x \n"
554 "MPUI1610_EMIFS_CONFIG_REG: 0x%-8x \n",
555 MPUI1610_SHOW(MPUI_CTRL),
556 MPUI1610_SHOW(MPUI_DSP_STATUS),
557 MPUI1610_SHOW(MPUI_DSP_BOOT_CONFIG),
558 MPUI1610_SHOW(MPUI_DSP_API_CONFIG),
559 MPUI1610_SHOW(EMIFF_SDRAM_CONFIG),
560 MPUI1610_SHOW(EMIFS_CONFIG));
563 g_read_completed++;
564 } else if (g_read_completed >= 1) {
565 *eof = 1;
566 return 0;
568 g_read_completed++;
570 *my_first_byte = page_buffer;
571 return my_buffer_offset;
574 static void omap_pm_init_proc(void)
576 struct proc_dir_entry *entry;
578 entry = create_proc_read_entry("driver/omap_pm",
579 S_IWUSR | S_IRUGO, NULL,
580 omap_pm_read_proc, NULL);
583 #endif /* DEBUG && CONFIG_PROC_FS */
585 static void (*saved_idle)(void) = NULL;
588 * omap_pm_prepare - Do preliminary suspend work.
591 static int omap_pm_prepare(void)
593 /* We cannot sleep in idle until we have resumed */
594 saved_idle = pm_idle;
595 pm_idle = NULL;
597 return 0;
602 * omap_pm_enter - Actually enter a sleep state.
603 * @state: State we're entering.
607 static int omap_pm_enter(suspend_state_t state)
609 switch (state)
611 case PM_SUSPEND_STANDBY:
612 case PM_SUSPEND_MEM:
613 omap_pm_suspend();
614 break;
615 default:
616 return -EINVAL;
619 return 0;
624 * omap_pm_finish - Finish up suspend sequence.
626 * This is called after we wake back up (or if entering the sleep state
627 * failed).
630 static void omap_pm_finish(void)
632 pm_idle = saved_idle;
636 static irqreturn_t omap_wakeup_interrupt(int irq, void *dev)
638 return IRQ_HANDLED;
641 static struct irqaction omap_wakeup_irq = {
642 .name = "peripheral wakeup",
643 .flags = IRQF_DISABLED,
644 .handler = omap_wakeup_interrupt
649 static struct platform_suspend_ops omap_pm_ops ={
650 .prepare = omap_pm_prepare,
651 .enter = omap_pm_enter,
652 .finish = omap_pm_finish,
653 .valid = suspend_valid_only_mem,
656 static int __init omap_pm_init(void)
659 #ifdef CONFIG_OMAP_32K_TIMER
660 int error;
661 #endif
663 printk("Power Management for TI OMAP.\n");
666 * We copy the assembler sleep/wakeup routines to SRAM.
667 * These routines need to be in SRAM as that's the only
668 * memory the MPU can see when it wakes up.
670 if (cpu_is_omap730()) {
671 omap_sram_suspend = omap_sram_push(omap730_cpu_suspend,
672 omap730_cpu_suspend_sz);
673 } else if (cpu_is_omap15xx()) {
674 omap_sram_suspend = omap_sram_push(omap1510_cpu_suspend,
675 omap1510_cpu_suspend_sz);
676 } else if (cpu_is_omap16xx()) {
677 omap_sram_suspend = omap_sram_push(omap1610_cpu_suspend,
678 omap1610_cpu_suspend_sz);
681 if (omap_sram_suspend == NULL) {
682 printk(KERN_ERR "PM not initialized: Missing SRAM support\n");
683 return -ENODEV;
686 pm_idle = omap_pm_idle;
688 if (cpu_is_omap730())
689 setup_irq(INT_730_WAKE_UP_REQ, &omap_wakeup_irq);
690 else if (cpu_is_omap16xx())
691 setup_irq(INT_1610_WAKE_UP_REQ, &omap_wakeup_irq);
693 /* Program new power ramp-up time
694 * (0 for most boards since we don't lower voltage when in deep sleep)
696 omap_writew(ULPD_SETUP_ANALOG_CELL_3_VAL, ULPD_SETUP_ANALOG_CELL_3);
698 /* Setup ULPD POWER_CTRL_REG - enter deep sleep whenever possible */
699 omap_writew(ULPD_POWER_CTRL_REG_VAL, ULPD_POWER_CTRL);
701 /* Configure IDLECT3 */
702 if (cpu_is_omap730())
703 omap_writel(OMAP730_IDLECT3_VAL, OMAP730_IDLECT3);
704 else if (cpu_is_omap16xx())
705 omap_writel(OMAP1610_IDLECT3_VAL, OMAP1610_IDLECT3);
707 suspend_set_ops(&omap_pm_ops);
709 #if defined(DEBUG) && defined(CONFIG_PROC_FS)
710 omap_pm_init_proc();
711 #endif
713 #ifdef CONFIG_OMAP_32K_TIMER
714 error = sysfs_create_file(power_kobj, &sleep_while_idle_attr.attr);
715 if (error)
716 printk(KERN_ERR "sysfs_create_file failed: %d\n", error);
717 #endif
719 if (cpu_is_omap16xx()) {
720 /* configure LOW_PWR pin */
721 omap_cfg_reg(T20_1610_LOW_PWR);
724 return 0;
726 __initcall(omap_pm_init);