arch/arm/mach-omap1/serial.c

   1 /*
   2  * linux/arch/arm/mach-omap1/serial.c
   3  *
   4  * OMAP1 serial support.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/irq.h>
  15 #include <linux/delay.h>
  16 #include <linux/serial.h>
  17 #include <linux/tty.h>
  18 #include <linux/serial_8250.h>
  19 #include <linux/serial_reg.h>
  20 #include <linux/clk.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/mach-types.h>
  24
  25 #include <mach/board.h>
  26 #include <mach/mux.h>
  27 #include <mach/gpio.h>
  28 #include <mach/fpga.h>
  29 #ifdef CONFIG_PM
  30 #include <mach/pm.h>
  31 #endif
  32
  33 static struct clk * uart1_ck;
  34 static struct clk * uart2_ck;
  35 static struct clk * uart3_ck;
  36
  37 static inline unsigned int omap_serial_in(struct plat_serial8250_port *up,
  38                                           int offset)
  39 {
  40         offset <<= up->regshift;
  41         return (unsigned int)__raw_readb(up->membase + offset);
  42 }
  43
  44 static inline void omap_serial_outp(struct plat_serial8250_port *p, int offset,
  45                                     int value)
  46 {
  47         offset <<= p->regshift;
  48         __raw_writeb(value, p->membase + offset);
  49 }
  50
  51 /*
  52  * Internal UARTs need to be initialized for the 8250 autoconfig to work
  53  * properly. Note that the TX watermark initialization may not be needed
  54  * once the 8250.c watermark handling code is merged.
  55  */
  56 static void __init omap_serial_reset(struct plat_serial8250_port *p)
  57 {
  58         omap_serial_outp(p, UART_OMAP_MDR1, 0x07);      /* disable UART */
  59         omap_serial_outp(p, UART_OMAP_SCR, 0x08);       /* TX watermark */
  60         omap_serial_outp(p, UART_OMAP_MDR1, 0x00);      /* enable UART */
  61
  62         if (!cpu_is_omap15xx()) {
  63                 omap_serial_outp(p, UART_OMAP_SYSC, 0x01);
  64                 while (!(omap_serial_in(p, UART_OMAP_SYSC) & 0x01));
  65         }
  66 }
  67
  68 static struct plat_serial8250_port serial_platform_data[] = {
  69         {
  70                 .membase        = IO_ADDRESS(OMAP_UART1_BASE),
  71                 .mapbase        = OMAP_UART1_BASE,
  72                 .irq            = INT_UART1,
  73                 .flags          = UPF_BOOT_AUTOCONF,
  74                 .iotype         = UPIO_MEM,
  75                 .regshift       = 2,
  76                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  77         },
  78         {
  79                 .membase        = IO_ADDRESS(OMAP_UART2_BASE),
  80                 .mapbase        = OMAP_UART2_BASE,
  81                 .irq            = INT_UART2,
  82                 .flags          = UPF_BOOT_AUTOCONF,
  83                 .iotype         = UPIO_MEM,
  84                 .regshift       = 2,
  85                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  86         },
  87         {
  88                 .membase        = IO_ADDRESS(OMAP_UART3_BASE),
  89                 .mapbase        = OMAP_UART3_BASE,
  90                 .irq            = INT_UART3,
  91                 .flags          = UPF_BOOT_AUTOCONF,
  92                 .iotype         = UPIO_MEM,
  93                 .regshift       = 2,
  94                 .uartclk        = OMAP16XX_BASE_BAUD * 16,
  95         },
  96         { },
  97 };
  98
  99 static struct platform_device serial_device = {
 100         .name                   = "serial8250",
 101         .id                     = PLAT8250_DEV_PLATFORM,
 102         .dev                    = {
 103                 .platform_data  = serial_platform_data,
 104         },
 105 };
 106
 107 /*
 108  * Note that on Innovator-1510 UART2 pins conflict with USB2.
 109  * By default UART2 does not work on Innovator-1510 if you have
 110  * USB OHCI enabled. To use UART2, you must disable USB2 first.
 111  */
 112 void __init omap_serial_init(void)
 113 {
 114         int i;
 115         const struct omap_uart_config *info;
 116
 117         if (cpu_is_omap730()) {
 118                 serial_platform_data[0].regshift = 0;
 119                 serial_platform_data[1].regshift = 0;
 120                 serial_platform_data[0].irq = INT_730_UART_MODEM_1;
 121                 serial_platform_data[1].irq = INT_730_UART_MODEM_IRDA_2;
 122         }
 123
 124         if (cpu_is_omap850()) {
 125                 serial_platform_data[0].regshift = 0;
 126                 serial_platform_data[1].regshift = 0;
 127                 serial_platform_data[0].irq = INT_850_UART_MODEM_1;
 128                 serial_platform_data[1].irq = INT_850_UART_MODEM_IRDA_2;
 129         }
 130
 131         if (cpu_is_omap15xx()) {
 132                 serial_platform_data[0].uartclk = OMAP1510_BASE_BAUD * 16;
 133                 serial_platform_data[1].uartclk = OMAP1510_BASE_BAUD * 16;
 134                 serial_platform_data[2].uartclk = OMAP1510_BASE_BAUD * 16;
 135         }
 136
 137         info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
 138         if (info == NULL)
 139                 return;
 140
 141         for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
 142                 unsigned char reg;
 143
 144                 if (!((1 << i) & info->enabled_uarts)) {
 145                         serial_platform_data[i].membase = NULL;
 146                         serial_platform_data[i].mapbase = 0;
 147                         continue;
 148                 }
 149
 150                 switch (i) {
 151                 case 0:
 152                         uart1_ck = clk_get(NULL, "uart1_ck");
 153                         if (IS_ERR(uart1_ck))
 154                                 printk("Could not get uart1_ck\n");
 155                         else {
 156                                 clk_enable(uart1_ck);
 157                                 if (cpu_is_omap15xx())
 158                                         clk_set_rate(uart1_ck, 12000000);
 159                         }
 160                         if (cpu_is_omap15xx()) {
 161                                 omap_cfg_reg(UART1_TX);
 162                                 omap_cfg_reg(UART1_RTS);
 163                                 if (machine_is_omap_innovator()) {
 164                                         reg = fpga_read(OMAP1510_FPGA_POWER);
 165                                         reg |= OMAP1510_FPGA_PCR_COM1_EN;
 166                                         fpga_write(reg, OMAP1510_FPGA_POWER);
 167                                         udelay(10);
 168                                 }
 169                         }
 170                         break;
 171                 case 1:
 172                         uart2_ck = clk_get(NULL, "uart2_ck");
 173                         if (IS_ERR(uart2_ck))
 174                                 printk("Could not get uart2_ck\n");
 175                         else {
 176                                 clk_enable(uart2_ck);
 177                                 if (cpu_is_omap15xx())
 178                                         clk_set_rate(uart2_ck, 12000000);
 179                                 else
 180                                         clk_set_rate(uart2_ck, 48000000);
 181                         }
 182                         if (cpu_is_omap15xx()) {
 183                                 omap_cfg_reg(UART2_TX);
 184                                 omap_cfg_reg(UART2_RTS);
 185                                 if (machine_is_omap_innovator()) {
 186                                         reg = fpga_read(OMAP1510_FPGA_POWER);
 187                                         reg |= OMAP1510_FPGA_PCR_COM2_EN;
 188                                         fpga_write(reg, OMAP1510_FPGA_POWER);
 189                                         udelay(10);
 190                                 }
 191                         }
 192                         break;
 193                 case 2:
 194                         uart3_ck = clk_get(NULL, "uart3_ck");
 195                         if (IS_ERR(uart3_ck))
 196                                 printk("Could not get uart3_ck\n");
 197                         else {
 198                                 clk_enable(uart3_ck);
 199                                 if (cpu_is_omap15xx())
 200                                         clk_set_rate(uart3_ck, 12000000);
 201                         }
 202                         if (cpu_is_omap15xx()) {
 203                                 omap_cfg_reg(UART3_TX);
 204                                 omap_cfg_reg(UART3_RX);
 205                         }
 206                         break;
 207                 }
 208                 omap_serial_reset(&serial_platform_data[i]);
 209         }
 210 }
 211
 212 #ifdef CONFIG_OMAP_SERIAL_WAKE
 213
 214 static irqreturn_t omap_serial_wake_interrupt(int irq, void *dev_id)
 215 {
 216         /* Need to do something with serial port right after wake-up? */
 217         return IRQ_HANDLED;
 218 }
 219
 220 /*
 221  * Reroutes serial RX lines to GPIO lines for the duration of
 222  * sleep to allow waking up the device from serial port even
 223  * in deep sleep.
 224  */
 225 void omap_serial_wake_trigger(int enable)
 226 {
 227         if (!cpu_is_omap16xx())
 228                 return;
 229
 230         if (uart1_ck != NULL) {
 231                 if (enable)
 232                         omap_cfg_reg(V14_16XX_GPIO37);
 233                 else
 234                         omap_cfg_reg(V14_16XX_UART1_RX);
 235         }
 236         if (uart2_ck != NULL) {
 237                 if (enable)
 238                         omap_cfg_reg(R9_16XX_GPIO18);
 239                 else
 240                         omap_cfg_reg(R9_16XX_UART2_RX);
 241         }
 242         if (uart3_ck != NULL) {
 243                 if (enable)
 244                         omap_cfg_reg(L14_16XX_GPIO49);
 245                 else
 246                         omap_cfg_reg(L14_16XX_UART3_RX);
 247         }
 248 }
 249
 250 static void __init omap_serial_set_port_wakeup(int gpio_nr)
 251 {
 252         int ret;
 253
 254         ret = gpio_request(gpio_nr, "UART wake");
 255         if (ret < 0) {
 256                 printk(KERN_ERR "Could not request UART wake GPIO: %i\n",
 257                        gpio_nr);
 258                 return;
 259         }
 260         gpio_direction_input(gpio_nr);
 261         ret = request_irq(gpio_to_irq(gpio_nr), &omap_serial_wake_interrupt,
 262                           IRQF_TRIGGER_RISING, "serial wakeup", NULL);
 263         if (ret) {
 264                 gpio_free(gpio_nr);
 265                 printk(KERN_ERR "No interrupt for UART wake GPIO: %i\n",
 266                        gpio_nr);
 267                 return;
 268         }
 269         enable_irq_wake(gpio_to_irq(gpio_nr));
 270 }
 271
 272 static int __init omap_serial_wakeup_init(void)
 273 {
 274         if (!cpu_is_omap16xx())
 275                 return 0;
 276
 277         if (uart1_ck != NULL)
 278                 omap_serial_set_port_wakeup(37);
 279         if (uart2_ck != NULL)
 280                 omap_serial_set_port_wakeup(18);
 281         if (uart3_ck != NULL)
 282                 omap_serial_set_port_wakeup(49);
 283
 284         return 0;
 285 }
 286 late_initcall(omap_serial_wakeup_init);
 287
 288 #endif  /* CONFIG_OMAP_SERIAL_WAKE */
 289
 290 static int __init omap_init(void)
 291 {
 292         return platform_device_register(&serial_device);
 293 }
 294 arch_initcall(omap_init);