arch/arm/mach-pxa/include/mach/gpio.h

   1 /*
   2  * arch/arm/mach-pxa/include/mach/gpio.h
   3  *
   4  * PXA GPIO wrappers for arch-neutral GPIO calls
   5  *
   6  * Written by Philipp Zabel <philipp.zabel@gmail.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #ifndef __ASM_ARCH_PXA_GPIO_H
  25 #define __ASM_ARCH_PXA_GPIO_H
  26
  27 #include <mach/irqs.h>
  28 #include <mach/hardware.h>
  29 #include <asm-generic/gpio.h>
  30
  31 #define GPIO_REGS_VIRT  io_p2v(0x40E00000)
  32
  33 #define BANK_OFF(n)     (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
  34 #define GPIO_REG(x)     (*(volatile u32 *)(GPIO_REGS_VIRT + (x)))
  35
  36 /* GPIO Pin Level Registers */
  37 #define GPLR0           GPIO_REG(BANK_OFF(0) + 0x00)
  38 #define GPLR1           GPIO_REG(BANK_OFF(1) + 0x00)
  39 #define GPLR2           GPIO_REG(BANK_OFF(2) + 0x00)
  40 #define GPLR3           GPIO_REG(BANK_OFF(3) + 0x00)
  41
  42 /* GPIO Pin Direction Registers */
  43 #define GPDR0           GPIO_REG(BANK_OFF(0) + 0x0c)
  44 #define GPDR1           GPIO_REG(BANK_OFF(1) + 0x0c)
  45 #define GPDR2           GPIO_REG(BANK_OFF(2) + 0x0c)
  46 #define GPDR3           GPIO_REG(BANK_OFF(3) + 0x0c)
  47
  48 /* GPIO Pin Output Set Registers */
  49 #define GPSR0           GPIO_REG(BANK_OFF(0) + 0x18)
  50 #define GPSR1           GPIO_REG(BANK_OFF(1) + 0x18)
  51 #define GPSR2           GPIO_REG(BANK_OFF(2) + 0x18)
  52 #define GPSR3           GPIO_REG(BANK_OFF(3) + 0x18)
  53
  54 /* GPIO Pin Output Clear Registers */
  55 #define GPCR0           GPIO_REG(BANK_OFF(0) + 0x24)
  56 #define GPCR1           GPIO_REG(BANK_OFF(1) + 0x24)
  57 #define GPCR2           GPIO_REG(BANK_OFF(2) + 0x24)
  58 #define GPCR3           GPIO_REG(BANK_OFF(3) + 0x24)
  59
  60 /* GPIO Rising Edge Detect Registers */
  61 #define GRER0           GPIO_REG(BANK_OFF(0) + 0x30)
  62 #define GRER1           GPIO_REG(BANK_OFF(1) + 0x30)
  63 #define GRER2           GPIO_REG(BANK_OFF(2) + 0x30)
  64 #define GRER3           GPIO_REG(BANK_OFF(3) + 0x30)
  65
  66 /* GPIO Falling Edge Detect Registers */
  67 #define GFER0           GPIO_REG(BANK_OFF(0) + 0x3c)
  68 #define GFER1           GPIO_REG(BANK_OFF(1) + 0x3c)
  69 #define GFER2           GPIO_REG(BANK_OFF(2) + 0x3c)
  70 #define GFER3           GPIO_REG(BANK_OFF(3) + 0x3c)
  71
  72 /* GPIO Edge Detect Status Registers */
  73 #define GEDR0           GPIO_REG(BANK_OFF(0) + 0x48)
  74 #define GEDR1           GPIO_REG(BANK_OFF(1) + 0x48)
  75 #define GEDR2           GPIO_REG(BANK_OFF(2) + 0x48)
  76 #define GEDR3           GPIO_REG(BANK_OFF(3) + 0x48)
  77
  78 /* GPIO Alternate Function Select Registers */
  79 #define GAFR0_L         GPIO_REG(0x0054)
  80 #define GAFR0_U         GPIO_REG(0x0058)
  81 #define GAFR1_L         GPIO_REG(0x005C)
  82 #define GAFR1_U         GPIO_REG(0x0060)
  83 #define GAFR2_L         GPIO_REG(0x0064)
  84 #define GAFR2_U         GPIO_REG(0x0068)
  85 #define GAFR3_L         GPIO_REG(0x006C)
  86 #define GAFR3_U         GPIO_REG(0x0070)
  87
  88 /* More handy macros.  The argument is a literal GPIO number. */
  89
  90 #define GPIO_bit(x)     (1 << ((x) & 0x1f))
  91
  92 #define GPLR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x00)
  93 #define GPDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x0c)
  94 #define GPSR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x18)
  95 #define GPCR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x24)
  96 #define GRER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x30)
  97 #define GFER(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x3c)
  98 #define GEDR(x)         GPIO_REG(BANK_OFF((x) >> 5) + 0x48)
  99 #define GAFR(x)         GPIO_REG(0x54 + (((x) & 0x70) >> 2))
 100
 101
 102 #define NR_BUILTIN_GPIO 128
 103
 104 #define gpio_to_bank(gpio)      ((gpio) >> 5)
 105 #define gpio_to_irq(gpio)       IRQ_GPIO(gpio)
 106 #define irq_to_gpio(irq)        IRQ_TO_GPIO(irq)
 107
 108 #ifdef CONFIG_CPU_PXA26x
 109 /* GPIO86/87/88/89 on PXA26x have their direction bits in GPDR2 inverted,
 110  * as well as their Alternate Function value being '1' for GPIO in GAFRx.
 111  */
 112 static inline int __gpio_is_inverted(unsigned gpio)
 113 {
 114         return cpu_is_pxa25x() && gpio > 85;
 115 }
 116 #else
 117 static inline int __gpio_is_inverted(unsigned gpio) { return 0; }
 118 #endif
 119
 120 /*
 121  * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 122  * function of a GPIO, and GPDRx cannot be altered once configured. It
 123  * is attributed as "occupied" here (I know this terminology isn't
 124  * accurate, you are welcome to propose a better one :-)
 125  */
 126 static inline int __gpio_is_occupied(unsigned gpio)
 127 {
 128         if (cpu_is_pxa27x() || cpu_is_pxa25x()) {
 129                 int af = (GAFR(gpio) >> ((gpio & 0xf) * 2)) & 0x3;
 130                 int dir = GPDR(gpio) & GPIO_bit(gpio);
 131
 132                 if (__gpio_is_inverted(gpio))
 133                         return af != 1 || dir == 0;
 134                 else
 135                         return af != 0 || dir != 0;
 136         } else
 137                 return GPDR(gpio) & GPIO_bit(gpio);
 138 }
 139
 140 #include <plat/gpio.h>
 141 #endif