arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/sched.h>
  20 #include <linux/cnt32_to_63.h>
  21
  22 #include <asm/div64.h>
  23 #include <asm/mach/irq.h>
  24 #include <asm/mach/time.h>
  25 #include <mach/regs-ost.h>
  26
  27 /*
  28  * This is PXA's sched_clock implementation. This has a resolution
  29  * of at least 308 ns and a maximum value of 208 days.
  30  *
  31  * The return value is guaranteed to be monotonic in that range as
  32  * long as there is always less than 582 seconds between successive
  33  * calls to sched_clock() which should always be the case in practice.
  34  */
  35
  36 #define OSCR2NS_SCALE_FACTOR 10
  37
  38 static unsigned long oscr2ns_scale;
  39
  40 static void __init set_oscr2ns_scale(unsigned long oscr_rate)
  41 {
  42         unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
  43         do_div(v, oscr_rate);
  44         oscr2ns_scale = v;
  45         /*
  46          * We want an even value to automatically clear the top bit
  47          * returned by cnt32_to_63() without an additional run time
  48          * instruction. So if the LSB is 1 then round it up.
  49          */
  50         if (oscr2ns_scale & 1)
  51                 oscr2ns_scale++;
  52 }
  53
  54 unsigned long long sched_clock(void)
  55 {
  56         unsigned long long v = cnt32_to_63(OSCR);
  57         return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
  58 }
  59
  60
  61 #define MIN_OSCR_DELTA 16
  62
  63 static irqreturn_t
  64 pxa_ost0_interrupt(int irq, void *dev_id)
  65 {
  66         struct clock_event_device *c = dev_id;
  67
  68         /* Disarm the compare/match, signal the event. */
  69         OIER &= ~OIER_E0;
  70         OSSR = OSSR_M0;
  71         c->event_handler(c);
  72
  73         return IRQ_HANDLED;
  74 }
  75
  76 static int
  77 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
  78 {
  79         unsigned long flags, next, oscr;
  80
  81         raw_local_irq_save(flags);
  82         OIER |= OIER_E0;
  83         next = OSCR + delta;
  84         OSMR0 = next;
  85         oscr = OSCR;
  86         raw_local_irq_restore(flags);
  87
  88         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
  89 }
  90
  91 static void
  92 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
  93 {
  94         unsigned long irqflags;
  95
  96         switch (mode) {
  97         case CLOCK_EVT_MODE_ONESHOT:
  98                 raw_local_irq_save(irqflags);
  99                 OIER &= ~OIER_E0;
 100                 OSSR = OSSR_M0;
 101                 raw_local_irq_restore(irqflags);
 102                 break;
 103
 104         case CLOCK_EVT_MODE_UNUSED:
 105         case CLOCK_EVT_MODE_SHUTDOWN:
 106                 /* initializing, released, or preparing for suspend */
 107                 raw_local_irq_save(irqflags);
 108                 OIER &= ~OIER_E0;
 109                 OSSR = OSSR_M0;
 110                 raw_local_irq_restore(irqflags);
 111                 break;
 112
 113         case CLOCK_EVT_MODE_RESUME:
 114         case CLOCK_EVT_MODE_PERIODIC:
 115                 break;
 116         }
 117 }
 118
 119 static struct clock_event_device ckevt_pxa_osmr0 = {
 120         .name           = "osmr0",
 121         .features       = CLOCK_EVT_FEAT_ONESHOT,
 122         .shift          = 32,
 123         .rating         = 200,
 124         .set_next_event = pxa_osmr0_set_next_event,
 125         .set_mode       = pxa_osmr0_set_mode,
 126 };
 127
 128 static cycle_t pxa_read_oscr(struct clocksource *cs)
 129 {
 130         return OSCR;
 131 }
 132
 133 static struct clocksource cksrc_pxa_oscr0 = {
 134         .name           = "oscr0",
 135         .rating         = 200,
 136         .read           = pxa_read_oscr,
 137         .mask           = CLOCKSOURCE_MASK(32),
 138         .shift          = 20,
 139         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 140 };
 141
 142 static struct irqaction pxa_ost0_irq = {
 143         .name           = "ost0",
 144         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 145         .handler        = pxa_ost0_interrupt,
 146         .dev_id         = &ckevt_pxa_osmr0,
 147 };
 148
 149 static void __init pxa_timer_init(void)
 150 {
 151         unsigned long clock_tick_rate = get_clock_tick_rate();
 152
 153         OIER = 0;
 154         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 155
 156         set_oscr2ns_scale(clock_tick_rate);
 157
 158         ckevt_pxa_osmr0.mult =
 159                 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
 160         ckevt_pxa_osmr0.max_delta_ns =
 161                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 162         ckevt_pxa_osmr0.min_delta_ns =
 163                 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
 164         ckevt_pxa_osmr0.cpumask = cpumask_of(0);
 165
 166         cksrc_pxa_oscr0.mult =
 167                 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
 168
 169         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 170
 171         clocksource_register(&cksrc_pxa_oscr0);
 172         clockevents_register_device(&ckevt_pxa_osmr0);
 173 }
 174
 175 #ifdef CONFIG_PM
 176 static unsigned long osmr[4], oier, oscr;
 177
 178 static void pxa_timer_suspend(void)
 179 {
 180         osmr[0] = OSMR0;
 181         osmr[1] = OSMR1;
 182         osmr[2] = OSMR2;
 183         osmr[3] = OSMR3;
 184         oier = OIER;
 185         oscr = OSCR;
 186 }
 187
 188 static void pxa_timer_resume(void)
 189 {
 190         /*
 191          * Ensure that we have at least MIN_OSCR_DELTA between match
 192          * register 0 and the OSCR, to guarantee that we will receive
 193          * the one-shot timer interrupt.  We adjust OSMR0 in preference
 194          * to OSCR to guarantee that OSCR is monotonically incrementing.
 195          */
 196         if (osmr[0] - oscr < MIN_OSCR_DELTA)
 197                 osmr[0] += MIN_OSCR_DELTA;
 198
 199         OSMR0 = osmr[0];
 200         OSMR1 = osmr[1];
 201         OSMR2 = osmr[2];
 202         OSMR3 = osmr[3];
 203         OIER = oier;
 204         OSCR = oscr;
 205 }
 206 #else
 207 #define pxa_timer_suspend NULL
 208 #define pxa_timer_resume NULL
 209 #endif
 210
 211 struct sys_timer pxa_timer = {
 212         .init           = pxa_timer_init,
 213         .suspend        = pxa_timer_suspend,
 214         .resume         = pxa_timer_resume,
 215 };