arch/arm/plat-s3c64xx/irq-eint.c

   1 /* arch/arm/plat-s3c64xx/irq-eint.c
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      Ben Dooks <ben@simtec.co.uk>
   6  *      http://armlinux.simtec.co.uk/
   7  *
   8  * S3C64XX - Interrupt handling for IRQ_EINT(x)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/gpio.h>
  18 #include <linux/irq.h>
  19 #include <linux/io.h>
  20
  21 #include <asm/hardware/vic.h>
  22
  23 #include <plat/regs-irqtype.h>
  24 #include <plat/regs-gpio.h>
  25 #include <plat/gpio-cfg.h>
  26
  27 #include <mach/map.h>
  28 #include <plat/cpu.h>
  29
  30 #define eint_offset(irq)        ((irq) - IRQ_EINT(0))
  31 #define eint_irq_to_bit(irq)    (1 << eint_offset(irq))
  32
  33 static inline void s3c_irq_eint_mask(unsigned int irq)
  34 {
  35         u32 mask;
  36
  37         mask = __raw_readl(S3C64XX_EINT0MASK);
  38         mask |= eint_irq_to_bit(irq);
  39         __raw_writel(mask, S3C64XX_EINT0MASK);
  40 }
  41
  42 static void s3c_irq_eint_unmask(unsigned int irq)
  43 {
  44         u32 mask;
  45
  46         mask = __raw_readl(S3C64XX_EINT0MASK);
  47         mask &= ~eint_irq_to_bit(irq);
  48         __raw_writel(mask, S3C64XX_EINT0MASK);
  49 }
  50
  51 static inline void s3c_irq_eint_ack(unsigned int irq)
  52 {
  53         __raw_writel(eint_irq_to_bit(irq), S3C64XX_EINT0PEND);
  54 }
  55
  56 static void s3c_irq_eint_maskack(unsigned int irq)
  57 {
  58         /* compiler should in-line these */
  59         s3c_irq_eint_mask(irq);
  60         s3c_irq_eint_ack(irq);
  61 }
  62
  63 static int s3c_irq_eint_set_type(unsigned int irq, unsigned int type)
  64 {
  65         int offs = eint_offset(irq);
  66         int pin;
  67         int shift;
  68         u32 ctrl, mask;
  69         u32 newvalue = 0;
  70         void __iomem *reg;
  71
  72         if (offs > 27)
  73                 return -EINVAL;
  74
  75         if (offs <= 15)
  76                 reg = S3C64XX_EINT0CON0;
  77         else
  78                 reg = S3C64XX_EINT0CON1;
  79
  80         switch (type) {
  81         case IRQ_TYPE_NONE:
  82                 printk(KERN_WARNING "No edge setting!\n");
  83                 break;
  84
  85         case IRQ_TYPE_EDGE_RISING:
  86                 newvalue = S3C2410_EXTINT_RISEEDGE;
  87                 break;
  88
  89         case IRQ_TYPE_EDGE_FALLING:
  90                 newvalue = S3C2410_EXTINT_FALLEDGE;
  91                 break;
  92
  93         case IRQ_TYPE_EDGE_BOTH:
  94                 newvalue = S3C2410_EXTINT_BOTHEDGE;
  95                 break;
  96
  97         case IRQ_TYPE_LEVEL_LOW:
  98                 newvalue = S3C2410_EXTINT_LOWLEV;
  99                 break;
 100
 101         case IRQ_TYPE_LEVEL_HIGH:
 102                 newvalue = S3C2410_EXTINT_HILEV;
 103                 break;
 104
 105         default:
 106                 printk(KERN_ERR "No such irq type %d", type);
 107                 return -1;
 108         }
 109
 110         shift = (offs / 2) * 4;
 111         mask = 0x7 << shift;
 112
 113         ctrl = __raw_readl(reg);
 114         ctrl &= ~mask;
 115         ctrl |= newvalue << shift;
 116         __raw_writel(ctrl, reg);
 117
 118         /* set the GPIO pin appropriately */
 119
 120         if (offs < 23)
 121                 pin = S3C64XX_GPN(offs);
 122         else
 123                 pin = S3C64XX_GPM(offs - 23);
 124
 125         s3c_gpio_cfgpin(pin, S3C_GPIO_SFN(2));
 126
 127         return 0;
 128 }
 129
 130 static struct irq_chip s3c_irq_eint = {
 131         .name           = "s3c-eint",
 132         .mask           = s3c_irq_eint_mask,
 133         .unmask         = s3c_irq_eint_unmask,
 134         .mask_ack       = s3c_irq_eint_maskack,
 135         .ack            = s3c_irq_eint_ack,
 136         .set_type       = s3c_irq_eint_set_type,
 137 };
 138
 139 /* s3c_irq_demux_eint
 140  *
 141  * This function demuxes the IRQ from the group0 external interrupts,
 142  * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
 143  * the specific handlers s3c_irq_demux_eintX_Y.
 144  */
 145 static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
 146 {
 147         u32 status = __raw_readl(S3C64XX_EINT0PEND);
 148         u32 mask = __raw_readl(S3C64XX_EINT0MASK);
 149         unsigned int irq;
 150
 151         status &= ~mask;
 152         status >>= start;
 153         status &= (1 << (end - start + 1)) - 1;
 154
 155         for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
 156                 if (status & 1)
 157                         generic_handle_irq(irq);
 158
 159                 status >>= 1;
 160         }
 161 }
 162
 163 static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
 164 {
 165         s3c_irq_demux_eint(0, 3);
 166 }
 167
 168 static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
 169 {
 170         s3c_irq_demux_eint(4, 11);
 171 }
 172
 173 static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
 174 {
 175         s3c_irq_demux_eint(12, 19);
 176 }
 177
 178 static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
 179 {
 180         s3c_irq_demux_eint(20, 27);
 181 }
 182
 183 static int __init s3c64xx_init_irq_eint(void)
 184 {
 185         int irq;
 186
 187         for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
 188                 set_irq_chip(irq, &s3c_irq_eint);
 189                 set_irq_handler(irq, handle_level_irq);
 190                 set_irq_flags(irq, IRQF_VALID);
 191         }
 192
 193         set_irq_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
 194         set_irq_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
 195         set_irq_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
 196         set_irq_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
 197
 198         return 0;
 199 }
 200
 201 arch_initcall(s3c64xx_init_irq_eint);