arch/powerpc/boot/4xx.c

   1 /*
   2  * Copyright 2007 David Gibson, IBM Corporation.
   3  *
   4  * Based on earlier code:
   5  *   Matt Porter <mporter@kernel.crashing.org>
   6  *   Copyright 2002-2005 MontaVista Software Inc.
   7  *
   8  *   Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
   9  *   Copyright (c) 2003, 2004 Zultys Technologies
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License
  13  * as published by the Free Software Foundation; either version
  14  * 2 of the License, or (at your option) any later version.
  15  */
  16 #include <stddef.h>
  17 #include "types.h"
  18 #include "string.h"
  19 #include "stdio.h"
  20 #include "ops.h"
  21 #include "reg.h"
  22 #include "dcr.h"
  23
  24 static unsigned long chip_11_errata(unsigned long memsize)
  25 {
  26         unsigned long pvr;
  27
  28         pvr = mfpvr();
  29
  30         switch (pvr & 0xf0000ff0) {
  31                 case 0x40000850:
  32                 case 0x400008d0:
  33                 case 0x200008d0:
  34                         memsize -= 4096;
  35                         break;
  36                 default:
  37                         break;
  38         }
  39
  40         return memsize;
  41 }
  42
  43 /* Read the 4xx SDRAM controller to get size of system memory. */
  44 void ibm4xx_sdram_fixup_memsize(void)
  45 {
  46         int i;
  47         unsigned long memsize, bank_config;
  48
  49         memsize = 0;
  50         for (i = 0; i < ARRAY_SIZE(sdram_bxcr); i++) {
  51                 bank_config = SDRAM0_READ(sdram_bxcr[i]);
  52                 if (bank_config & SDRAM_CONFIG_BANK_ENABLE)
  53                         memsize += SDRAM_CONFIG_BANK_SIZE(bank_config);
  54         }
  55
  56         memsize = chip_11_errata(memsize);
  57         dt_fixup_memory(0, memsize);
  58 }
  59
  60 /* Read the 440SPe MQ controller to get size of system memory. */
  61 #define DCRN_MQ0_B0BAS          0x40
  62 #define DCRN_MQ0_B1BAS          0x41
  63 #define DCRN_MQ0_B2BAS          0x42
  64 #define DCRN_MQ0_B3BAS          0x43
  65
  66 static u64 ibm440spe_decode_bas(u32 bas)
  67 {
  68         u64 base = ((u64)(bas & 0xFFE00000u)) << 2;
  69
  70         /* open coded because I'm paranoid about invalid values */
  71         switch ((bas >> 4) & 0xFFF) {
  72         case 0:
  73                 return 0;
  74         case 0xffc:
  75                 return base + 0x000800000ull;
  76         case 0xff8:
  77                 return base + 0x001000000ull;
  78         case 0xff0:
  79                 return base + 0x002000000ull;
  80         case 0xfe0:
  81                 return base + 0x004000000ull;
  82         case 0xfc0:
  83                 return base + 0x008000000ull;
  84         case 0xf80:
  85                 return base + 0x010000000ull;
  86         case 0xf00:
  87                 return base + 0x020000000ull;
  88         case 0xe00:
  89                 return base + 0x040000000ull;
  90         case 0xc00:
  91                 return base + 0x080000000ull;
  92         case 0x800:
  93                 return base + 0x100000000ull;
  94         }
  95         printf("Memory BAS value 0x%08x unsupported !\n", bas);
  96         return 0;
  97 }
  98
  99 void ibm440spe_fixup_memsize(void)
 100 {
 101         u64 banktop, memsize = 0;
 102
 103         /* Ultimately, we should directly construct the memory node
 104          * so we are able to handle holes in the memory address space
 105          */
 106         banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B0BAS));
 107         if (banktop > memsize)
 108                 memsize = banktop;
 109         banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B1BAS));
 110         if (banktop > memsize)
 111                 memsize = banktop;
 112         banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B2BAS));
 113         if (banktop > memsize)
 114                 memsize = banktop;
 115         banktop = ibm440spe_decode_bas(mfdcr(DCRN_MQ0_B3BAS));
 116         if (banktop > memsize)
 117                 memsize = banktop;
 118
 119         dt_fixup_memory(0, memsize);
 120 }
 121
 122
 123 /* 4xx DDR1/2 Denali memory controller support */
 124 /* DDR0 registers */
 125 #define DDR0_02                 2
 126 #define DDR0_08                 8
 127 #define DDR0_10                 10
 128 #define DDR0_14                 14
 129 #define DDR0_42                 42
 130 #define DDR0_43                 43
 131
 132 /* DDR0_02 */
 133 #define DDR_START               0x1
 134 #define DDR_START_SHIFT         0
 135 #define DDR_MAX_CS_REG          0x3
 136 #define DDR_MAX_CS_REG_SHIFT    24
 137 #define DDR_MAX_COL_REG         0xf
 138 #define DDR_MAX_COL_REG_SHIFT   16
 139 #define DDR_MAX_ROW_REG         0xf
 140 #define DDR_MAX_ROW_REG_SHIFT   8
 141 /* DDR0_08 */
 142 #define DDR_DDR2_MODE           0x1
 143 #define DDR_DDR2_MODE_SHIFT     0
 144 /* DDR0_10 */
 145 #define DDR_CS_MAP              0x3
 146 #define DDR_CS_MAP_SHIFT        8
 147 /* DDR0_14 */
 148 #define DDR_REDUC               0x1
 149 #define DDR_REDUC_SHIFT         16
 150 /* DDR0_42 */
 151 #define DDR_APIN                0x7
 152 #define DDR_APIN_SHIFT          24
 153 /* DDR0_43 */
 154 #define DDR_COL_SZ              0x7
 155 #define DDR_COL_SZ_SHIFT        8
 156 #define DDR_BANK8               0x1
 157 #define DDR_BANK8_SHIFT         0
 158
 159 #define DDR_GET_VAL(val, mask, shift)   (((val) >> (shift)) & (mask))
 160
 161 /*
 162  * Some U-Boot versions set the number of chipselects to two
 163  * for Sequoia/Rainier boards while they only have one chipselect
 164  * hardwired. Hardcode the number of chipselects to one
 165  * for sequioa/rainer board models or read the actual value
 166  * from the memory controller register DDR0_10 otherwise.
 167  */
 168 static inline u32 ibm4xx_denali_get_cs(void)
 169 {
 170         void *devp;
 171         char model[64];
 172         u32 val, cs;
 173
 174         devp = finddevice("/");
 175         if (!devp)
 176                 goto read_cs;
 177
 178         if (getprop(devp, "model", model, sizeof(model)) <= 0)
 179                 goto read_cs;
 180
 181         model[sizeof(model)-1] = 0;
 182
 183         if (!strcmp(model, "amcc,sequoia") ||
 184             !strcmp(model, "amcc,rainier"))
 185                 return 1;
 186
 187 read_cs:
 188         /* get CS value */
 189         val = SDRAM0_READ(DDR0_10);
 190
 191         val = DDR_GET_VAL(val, DDR_CS_MAP, DDR_CS_MAP_SHIFT);
 192         cs = 0;
 193         while (val) {
 194                 if (val & 0x1)
 195                         cs++;
 196                 val = val >> 1;
 197         }
 198         return cs;
 199 }
 200
 201 void ibm4xx_denali_fixup_memsize(void)
 202 {
 203         u32 val, max_cs, max_col, max_row;
 204         u32 cs, col, row, bank, dpath;
 205         unsigned long memsize;
 206
 207         val = SDRAM0_READ(DDR0_02);
 208         if (!DDR_GET_VAL(val, DDR_START, DDR_START_SHIFT))
 209                 fatal("DDR controller is not initialized\n");
 210
 211         /* get maximum cs col and row values */
 212         max_cs  = DDR_GET_VAL(val, DDR_MAX_CS_REG, DDR_MAX_CS_REG_SHIFT);
 213         max_col = DDR_GET_VAL(val, DDR_MAX_COL_REG, DDR_MAX_COL_REG_SHIFT);
 214         max_row = DDR_GET_VAL(val, DDR_MAX_ROW_REG, DDR_MAX_ROW_REG_SHIFT);
 215
 216         cs = ibm4xx_denali_get_cs();
 217         if (!cs)
 218                 fatal("No memory installed\n");
 219         if (cs > max_cs)
 220                 fatal("DDR wrong CS configuration\n");
 221
 222         /* get data path bytes */
 223         val = SDRAM0_READ(DDR0_14);
 224
 225         if (DDR_GET_VAL(val, DDR_REDUC, DDR_REDUC_SHIFT))
 226                 dpath = 4; /* 32 bits */
 227         else
 228                 dpath = 8; /* 64 bits */
 229
 230         /* get address pins (rows) */
 231         val = SDRAM0_READ(DDR0_42);
 232
 233         row = DDR_GET_VAL(val, DDR_APIN, DDR_APIN_SHIFT);
 234         if (row > max_row)
 235                 fatal("DDR wrong APIN configuration\n");
 236         row = max_row - row;
 237
 238         /* get collomn size and banks */
 239         val = SDRAM0_READ(DDR0_43);
 240
 241         col = DDR_GET_VAL(val, DDR_COL_SZ, DDR_COL_SZ_SHIFT);
 242         if (col > max_col)
 243                 fatal("DDR wrong COL configuration\n");
 244         col = max_col - col;
 245
 246         if (DDR_GET_VAL(val, DDR_BANK8, DDR_BANK8_SHIFT))
 247                 bank = 8; /* 8 banks */
 248         else
 249                 bank = 4; /* 4 banks */
 250
 251         memsize = cs * (1 << (col+row)) * bank * dpath;
 252         memsize = chip_11_errata(memsize);
 253         dt_fixup_memory(0, memsize);
 254 }
 255
 256 #define SPRN_DBCR0_40X 0x3F2
 257 #define SPRN_DBCR0_44X 0x134
 258 #define DBCR0_RST_SYSTEM 0x30000000
 259
 260 void ibm44x_dbcr_reset(void)
 261 {
 262         unsigned long tmp;
 263
 264         asm volatile (
 265                 "mfspr  %0,%1\n"
 266                 "oris   %0,%0,%2@h\n"
 267                 "mtspr  %1,%0"
 268                 : "=&r"(tmp) : "i"(SPRN_DBCR0_44X), "i"(DBCR0_RST_SYSTEM)
 269                 );
 270
 271 }
 272
 273 void ibm40x_dbcr_reset(void)
 274 {
 275         unsigned long tmp;
 276
 277         asm volatile (
 278                 "mfspr  %0,%1\n"
 279                 "oris   %0,%0,%2@h\n"
 280                 "mtspr  %1,%0"
 281                 : "=&r"(tmp) : "i"(SPRN_DBCR0_40X), "i"(DBCR0_RST_SYSTEM)
 282                 );
 283 }
 284
 285 #define EMAC_RESET 0x20000000
 286 void ibm4xx_quiesce_eth(u32 *emac0, u32 *emac1)
 287 {
 288         /* Quiesce the MAL and EMAC(s) since PIBS/OpenBIOS don't
 289          * do this for us
 290          */
 291         if (emac0)
 292                 *emac0 = EMAC_RESET;
 293         if (emac1)
 294                 *emac1 = EMAC_RESET;
 295
 296         mtdcr(DCRN_MAL0_CFG, MAL_RESET);
 297         while (mfdcr(DCRN_MAL0_CFG) & MAL_RESET)
 298                 ; /* loop until reset takes effect */
 299 }
 300
 301 /* Read 4xx EBC bus bridge registers to get mappings of the peripheral
 302  * banks into the OPB address space */
 303 void ibm4xx_fixup_ebc_ranges(const char *ebc)
 304 {
 305         void *devp;
 306         u32 bxcr;
 307         u32 ranges[EBC_NUM_BANKS*4];
 308         u32 *p = ranges;
 309         int i;
 310
 311         for (i = 0; i < EBC_NUM_BANKS; i++) {
 312                 mtdcr(DCRN_EBC0_CFGADDR, EBC_BXCR(i));
 313                 bxcr = mfdcr(DCRN_EBC0_CFGDATA);
 314
 315                 if ((bxcr & EBC_BXCR_BU) != EBC_BXCR_BU_OFF) {
 316                         *p++ = i;
 317                         *p++ = 0;
 318                         *p++ = bxcr & EBC_BXCR_BAS;
 319                         *p++ = EBC_BXCR_BANK_SIZE(bxcr);
 320                 }
 321         }
 322
 323         devp = finddevice(ebc);
 324         if (! devp)
 325                 fatal("Couldn't locate EBC node %s\n\r", ebc);
 326
 327         setprop(devp, "ranges", ranges, (p - ranges) * sizeof(u32));
 328 }
 329
 330 /* Calculate 440GP clocks */
 331 void ibm440gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
 332 {
 333         u32 sys0 = mfdcr(DCRN_CPC0_SYS0);
 334         u32 cr0 = mfdcr(DCRN_CPC0_CR0);
 335         u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
 336         u32 opdv = CPC0_SYS0_OPDV(sys0);
 337         u32 epdv = CPC0_SYS0_EPDV(sys0);
 338
 339         if (sys0 & CPC0_SYS0_BYPASS) {
 340                 /* Bypass system PLL */
 341                 cpu = plb = sys_clk;
 342         } else {
 343                 if (sys0 & CPC0_SYS0_EXTSL)
 344                         /* PerClk */
 345                         m = CPC0_SYS0_FWDVB(sys0) * opdv * epdv;
 346                 else
 347                         /* CPU clock */
 348                         m = CPC0_SYS0_FBDV(sys0) * CPC0_SYS0_FWDVA(sys0);
 349                 cpu = sys_clk * m / CPC0_SYS0_FWDVA(sys0);
 350                 plb = sys_clk * m / CPC0_SYS0_FWDVB(sys0);
 351         }
 352
 353         opb = plb / opdv;
 354         ebc = opb / epdv;
 355
 356         /* FIXME: Check if this is for all 440GP, or just Ebony */
 357         if ((mfpvr() & 0xf0000fff) == 0x40000440)
 358                 /* Rev. B 440GP, use external system clock */
 359                 tb = sys_clk;
 360         else
 361                 /* Rev. C 440GP, errata force us to use internal clock */
 362                 tb = cpu;
 363
 364         if (cr0 & CPC0_CR0_U0EC)
 365                 /* External UART clock */
 366                 uart0 = ser_clk;
 367         else
 368                 /* Internal UART clock */
 369                 uart0 = plb / CPC0_CR0_UDIV(cr0);
 370
 371         if (cr0 & CPC0_CR0_U1EC)
 372                 /* External UART clock */
 373                 uart1 = ser_clk;
 374         else
 375                 /* Internal UART clock */
 376                 uart1 = plb / CPC0_CR0_UDIV(cr0);
 377
 378         printf("PPC440GP: SysClk = %dMHz (%x)\n\r",
 379                (sys_clk + 500000) / 1000000, sys_clk);
 380
 381         dt_fixup_cpu_clocks(cpu, tb, 0);
 382
 383         dt_fixup_clock("/plb", plb);
 384         dt_fixup_clock("/plb/opb", opb);
 385         dt_fixup_clock("/plb/opb/ebc", ebc);
 386         dt_fixup_clock("/plb/opb/serial@40000200", uart0);
 387         dt_fixup_clock("/plb/opb/serial@40000300", uart1);
 388 }
 389
 390 #define SPRN_CCR1 0x378
 391
 392 static inline u32 __fix_zero(u32 v, u32 def)
 393 {
 394         return v ? v : def;
 395 }
 396
 397 static unsigned int __ibm440eplike_fixup_clocks(unsigned int sys_clk,
 398                                                 unsigned int tmr_clk,
 399                                                 int per_clk_from_opb)
 400 {
 401         /* PLL config */
 402         u32 pllc  = CPR0_READ(DCRN_CPR0_PLLC);
 403         u32 plld  = CPR0_READ(DCRN_CPR0_PLLD);
 404
 405         /* Dividers */
 406         u32 fbdv   = __fix_zero((plld >> 24) & 0x1f, 32);
 407         u32 fwdva  = __fix_zero((plld >> 16) & 0xf, 16);
 408         u32 fwdvb  = __fix_zero((plld >> 8) & 7, 8);
 409         u32 lfbdv  = __fix_zero(plld & 0x3f, 64);
 410         u32 pradv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMAD) >> 24) & 7, 8);
 411         u32 prbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PRIMBD) >> 24) & 7, 8);
 412         u32 opbdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_OPBD) >> 24) & 3, 4);
 413         u32 perdv0 = __fix_zero((CPR0_READ(DCRN_CPR0_PERD) >> 24) & 3, 4);
 414
 415         /* Input clocks for primary dividers */
 416         u32 clk_a, clk_b;
 417
 418         /* Resulting clocks */
 419         u32 cpu, plb, opb, ebc, vco;
 420
 421         /* Timebase */
 422         u32 ccr1, tb = tmr_clk;
 423
 424         if (pllc & 0x40000000) {
 425                 u32 m;
 426
 427                 /* Feedback path */
 428                 switch ((pllc >> 24) & 7) {
 429                 case 0:
 430                         /* PLLOUTx */
 431                         m = ((pllc & 0x20000000) ? fwdvb : fwdva) * lfbdv;
 432                         break;
 433                 case 1:
 434                         /* CPU */
 435                         m = fwdva * pradv0;
 436                         break;
 437                 case 5:
 438                         /* PERClk */
 439                         m = fwdvb * prbdv0 * opbdv0 * perdv0;
 440                         break;
 441                 default:
 442                         printf("WARNING ! Invalid PLL feedback source !\n");
 443                         goto bypass;
 444                 }
 445                 m *= fbdv;
 446                 vco = sys_clk * m;
 447                 clk_a = vco / fwdva;
 448                 clk_b = vco / fwdvb;
 449         } else {
 450 bypass:
 451                 /* Bypass system PLL */
 452                 vco = 0;
 453                 clk_a = clk_b = sys_clk;
 454         }
 455
 456         cpu = clk_a / pradv0;
 457         plb = clk_b / prbdv0;
 458         opb = plb / opbdv0;
 459         ebc = (per_clk_from_opb ? opb : plb) / perdv0;
 460
 461         /* Figure out timebase.  Either CPU or default TmrClk */
 462         ccr1 = mfspr(SPRN_CCR1);
 463
 464         /* If passed a 0 tmr_clk, force CPU clock */
 465         if (tb == 0) {
 466                 ccr1 &= ~0x80u;
 467                 mtspr(SPRN_CCR1, ccr1);
 468         }
 469         if ((ccr1 & 0x0080) == 0)
 470                 tb = cpu;
 471
 472         dt_fixup_cpu_clocks(cpu, tb, 0);
 473         dt_fixup_clock("/plb", plb);
 474         dt_fixup_clock("/plb/opb", opb);
 475         dt_fixup_clock("/plb/opb/ebc", ebc);
 476
 477         return plb;
 478 }
 479
 480 static void eplike_fixup_uart_clk(int index, const char *path,
 481                                   unsigned int ser_clk,
 482                                   unsigned int plb_clk)
 483 {
 484         unsigned int sdr;
 485         unsigned int clock;
 486
 487         switch (index) {
 488         case 0:
 489                 sdr = SDR0_READ(DCRN_SDR0_UART0);
 490                 break;
 491         case 1:
 492                 sdr = SDR0_READ(DCRN_SDR0_UART1);
 493                 break;
 494         case 2:
 495                 sdr = SDR0_READ(DCRN_SDR0_UART2);
 496                 break;
 497         case 3:
 498                 sdr = SDR0_READ(DCRN_SDR0_UART3);
 499                 break;
 500         default:
 501                 return;
 502         }
 503
 504         if (sdr & 0x00800000u)
 505                 clock = ser_clk;
 506         else
 507                 clock = plb_clk / __fix_zero(sdr & 0xff, 256);
 508
 509         dt_fixup_clock(path, clock);
 510 }
 511
 512 void ibm440ep_fixup_clocks(unsigned int sys_clk,
 513                            unsigned int ser_clk,
 514                            unsigned int tmr_clk)
 515 {
 516         unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 0);
 517
 518         /* serial clocks beed fixup based on int/ext */
 519         eplike_fixup_uart_clk(0, "/plb/opb/serial@ef600300", ser_clk, plb_clk);
 520         eplike_fixup_uart_clk(1, "/plb/opb/serial@ef600400", ser_clk, plb_clk);
 521         eplike_fixup_uart_clk(2, "/plb/opb/serial@ef600500", ser_clk, plb_clk);
 522         eplike_fixup_uart_clk(3, "/plb/opb/serial@ef600600", ser_clk, plb_clk);
 523 }
 524
 525 void ibm440gx_fixup_clocks(unsigned int sys_clk,
 526                            unsigned int ser_clk,
 527                            unsigned int tmr_clk)
 528 {
 529         unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
 530
 531         /* serial clocks beed fixup based on int/ext */
 532         eplike_fixup_uart_clk(0, "/plb/opb/serial@40000200", ser_clk, plb_clk);
 533         eplike_fixup_uart_clk(1, "/plb/opb/serial@40000300", ser_clk, plb_clk);
 534 }
 535
 536 void ibm440spe_fixup_clocks(unsigned int sys_clk,
 537                             unsigned int ser_clk,
 538                             unsigned int tmr_clk)
 539 {
 540         unsigned int plb_clk = __ibm440eplike_fixup_clocks(sys_clk, tmr_clk, 1);
 541
 542         /* serial clocks beed fixup based on int/ext */
 543         eplike_fixup_uart_clk(0, "/plb/opb/serial@10000200", ser_clk, plb_clk);
 544         eplike_fixup_uart_clk(1, "/plb/opb/serial@10000300", ser_clk, plb_clk);
 545         eplike_fixup_uart_clk(2, "/plb/opb/serial@10000600", ser_clk, plb_clk);
 546 }
 547
 548 void ibm405gp_fixup_clocks(unsigned int sys_clk, unsigned int ser_clk)
 549 {
 550         u32 pllmr = mfdcr(DCRN_CPC0_PLLMR);
 551         u32 cpc0_cr0 = mfdcr(DCRN_405_CPC0_CR0);
 552         u32 cpc0_cr1 = mfdcr(DCRN_405_CPC0_CR1);
 553         u32 psr = mfdcr(DCRN_405_CPC0_PSR);
 554         u32 cpu, plb, opb, ebc, tb, uart0, uart1, m;
 555         u32 fwdv, fwdvb, fbdv, cbdv, opdv, epdv, ppdv, udiv;
 556
 557         fwdv = (8 - ((pllmr & 0xe0000000) >> 29));
 558         fbdv = (pllmr & 0x1e000000) >> 25;
 559         if (fbdv == 0)
 560                 fbdv = 16;
 561         cbdv = ((pllmr & 0x00060000) >> 17) + 1; /* CPU:PLB */
 562         opdv = ((pllmr & 0x00018000) >> 15) + 1; /* PLB:OPB */
 563         ppdv = ((pllmr & 0x00001800) >> 13) + 1; /* PLB:PCI */
 564         epdv = ((pllmr & 0x00001800) >> 11) + 2; /* PLB:EBC */
 565         udiv = ((cpc0_cr0 & 0x3e) >> 1) + 1;
 566
 567         /* check for 405GPr */
 568         if ((mfpvr() & 0xfffffff0) == (0x50910951 & 0xfffffff0)) {
 569                 fwdvb = 8 - (pllmr & 0x00000007);
 570                 if (!(psr & 0x00001000)) /* PCI async mode enable == 0 */
 571                         if (psr & 0x00000020) /* New mode enable */
 572                                 m = fwdvb * 2 * ppdv;
 573                         else
 574                                 m = fwdvb * cbdv * ppdv;
 575                 else if (psr & 0x00000020) /* New mode enable */
 576                         if (psr & 0x00000800) /* PerClk synch mode */
 577                                 m = fwdvb * 2 * epdv;
 578                         else
 579                                 m = fbdv * fwdv;
 580                 else if (epdv == fbdv)
 581                         m = fbdv * cbdv * epdv;
 582                 else
 583                         m = fbdv * fwdvb * cbdv;
 584
 585                 cpu = sys_clk * m / fwdv;
 586                 plb = sys_clk * m / (fwdvb * cbdv);
 587         } else {
 588                 m = fwdv * fbdv * cbdv;
 589                 cpu = sys_clk * m / fwdv;
 590                 plb = cpu / cbdv;
 591         }
 592         opb = plb / opdv;
 593         ebc = plb / epdv;
 594
 595         if (cpc0_cr0 & 0x80)
 596                 /* uart0 uses the external clock */
 597                 uart0 = ser_clk;
 598         else
 599                 uart0 = cpu / udiv;
 600
 601         if (cpc0_cr0 & 0x40)
 602                 /* uart1 uses the external clock */
 603                 uart1 = ser_clk;
 604         else
 605                 uart1 = cpu / udiv;
 606
 607         /* setup the timebase clock to tick at the cpu frequency */
 608         cpc0_cr1 = cpc0_cr1 & ~0x00800000;
 609         mtdcr(DCRN_405_CPC0_CR1, cpc0_cr1);
 610         tb = cpu;
 611
 612         dt_fixup_cpu_clocks(cpu, tb, 0);
 613         dt_fixup_clock("/plb", plb);
 614         dt_fixup_clock("/plb/opb", opb);
 615         dt_fixup_clock("/plb/ebc", ebc);
 616         dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
 617         dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
 618 }
 619
 620
 621 void ibm405ep_fixup_clocks(unsigned int sys_clk)
 622 {
 623         u32 pllmr0 = mfdcr(DCRN_CPC0_PLLMR0);
 624         u32 pllmr1 = mfdcr(DCRN_CPC0_PLLMR1);
 625         u32 cpc0_ucr = mfdcr(DCRN_CPC0_UCR);
 626         u32 cpu, plb, opb, ebc, uart0, uart1;
 627         u32 fwdva, fwdvb, fbdv, cbdv, opdv, epdv;
 628         u32 pllmr0_ccdv, tb, m;
 629
 630         fwdva = 8 - ((pllmr1 & 0x00070000) >> 16);
 631         fwdvb = 8 - ((pllmr1 & 0x00007000) >> 12);
 632         fbdv = (pllmr1 & 0x00f00000) >> 20;
 633         if (fbdv == 0)
 634                 fbdv = 16;
 635
 636         cbdv = ((pllmr0 & 0x00030000) >> 16) + 1; /* CPU:PLB */
 637         epdv = ((pllmr0 & 0x00000300) >> 8) + 2;  /* PLB:EBC */
 638         opdv = ((pllmr0 & 0x00003000) >> 12) + 1; /* PLB:OPB */
 639
 640         m = fbdv * fwdvb;
 641
 642         pllmr0_ccdv = ((pllmr0 & 0x00300000) >> 20) + 1;
 643         if (pllmr1 & 0x80000000)
 644                 cpu = sys_clk * m / (fwdva * pllmr0_ccdv);
 645         else
 646                 cpu = sys_clk / pllmr0_ccdv;
 647
 648         plb = cpu / cbdv;
 649         opb = plb / opdv;
 650         ebc = plb / epdv;
 651         tb = cpu;
 652         uart0 = cpu / (cpc0_ucr & 0x0000007f);
 653         uart1 = cpu / ((cpc0_ucr & 0x00007f00) >> 8);
 654
 655         dt_fixup_cpu_clocks(cpu, tb, 0);
 656         dt_fixup_clock("/plb", plb);
 657         dt_fixup_clock("/plb/opb", opb);
 658         dt_fixup_clock("/plb/ebc", ebc);
 659         dt_fixup_clock("/plb/opb/serial@ef600300", uart0);
 660         dt_fixup_clock("/plb/opb/serial@ef600400", uart1);
 661 }