| blob | 57c595bf10717f23036a9d292b6025c26f273afa |
1 /*
2 * MPC8323E EMDS Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * To enable external serial I/O on a Freescale MPC 8323 SYS/MDS board, do
12 * this:
13 *
14 * 1) On chip U61, lift (disconnect) pins 21 (TXD) and 22 (RXD) from the board.
15 * 2) Solder a wire from U61-21 to P19A-23. P19 is a grid of pins on the board
16 * next to the serial ports.
17 * 3) Solder a wire from U61-22 to P19K-22.
18 *
19 * Note that there's a typo in the schematic. The board labels the last column
20 * of pins "P19K", but in the schematic, that column is called "P19J". So if
21 * you're going by the schematic, the pin is called "P19J-K22".
22 */
24 /dts-v1/;
26 / {
27 model = "MPC8323EMDS";
28 compatible = "MPC8323EMDS", "MPC832xMDS", "MPC83xxMDS";
29 #address-cells = <1>;
30 #size-cells = <1>;
32 aliases {
33 ethernet0 = &enet0;
34 ethernet1 = &enet1;
35 serial0 = &serial0;
36 serial1 = &serial1;
37 pci0 = &pci0;
38 };
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
44 PowerPC,8323@0 {
45 device_type = "cpu";
46 reg = <0x0>;
47 d-cache-line-size = <32>; // 32 bytes
48 i-cache-line-size = <32>; // 32 bytes
49 d-cache-size = <16384>; // L1, 16K
50 i-cache-size = <16384>; // L1, 16K
51 timebase-frequency = <0>;
52 bus-frequency = <0>;
53 clock-frequency = <0>;
54 };
55 };
57 memory {
58 device_type = "memory";
59 reg = <0x00000000 0x08000000>;
60 };
62 bcsr@f8000000 {
63 compatible = "fsl,mpc8323mds-bcsr";
64 reg = <0xf8000000 0x8000>;
65 };
67 soc8323@e0000000 {
68 #address-cells = <1>;
69 #size-cells = <1>;
70 device_type = "soc";
71 compatible = "simple-bus";
72 ranges = <0x0 0xe0000000 0x00100000>;
73 reg = <0xe0000000 0x00000200>;
74 bus-frequency = <132000000>;
76 wdt@200 {
77 device_type = "watchdog";
78 compatible = "mpc83xx_wdt";
79 reg = <0x200 0x100>;
80 };
82 i2c@3000 {
83 #address-cells = <1>;
84 #size-cells = <0>;
85 cell-index = <0>;
86 compatible = "fsl-i2c";
87 reg = <0x3000 0x100>;
88 interrupts = <14 0x8>;
89 interrupt-parent = <&ipic>;
90 dfsrr;
92 rtc@68 {
93 compatible = "dallas,ds1374";
94 reg = <0x68>;
95 };
96 };
98 serial0: serial@4500 {
99 cell-index = <0>;
100 device_type = "serial";
101 compatible = "ns16550";
102 reg = <0x4500 0x100>;
103 clock-frequency = <0>;
104 interrupts = <9 0x8>;
105 interrupt-parent = <&ipic>;
106 };
108 serial1: serial@4600 {
109 cell-index = <1>;
110 device_type = "serial";
111 compatible = "ns16550";
112 reg = <0x4600 0x100>;
113 clock-frequency = <0>;
114 interrupts = <10 0x8>;
115 interrupt-parent = <&ipic>;
116 };
118 dma@82a8 {
119 #address-cells = <1>;
120 #size-cells = <1>;
121 compatible = "fsl,mpc8323-dma", "fsl,elo-dma";
122 reg = <0x82a8 4>;
123 ranges = <0 0x8100 0x1a8>;
124 interrupt-parent = <&ipic>;
125 interrupts = <71 8>;
126 cell-index = <0>;
127 dma-channel@0 {
128 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
129 reg = <0 0x80>;
130 cell-index = <0>;
131 interrupt-parent = <&ipic>;
132 interrupts = <71 8>;
133 };
134 dma-channel@80 {
135 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
136 reg = <0x80 0x80>;
137 cell-index = <1>;
138 interrupt-parent = <&ipic>;
139 interrupts = <71 8>;
140 };
141 dma-channel@100 {
142 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
143 reg = <0x100 0x80>;
144 cell-index = <2>;
145 interrupt-parent = <&ipic>;
146 interrupts = <71 8>;
147 };
148 dma-channel@180 {
149 compatible = "fsl,mpc8323-dma-channel", "fsl,elo-dma-channel";
150 reg = <0x180 0x28>;
151 cell-index = <3>;
152 interrupt-parent = <&ipic>;
153 interrupts = <71 8>;
154 };
155 };
157 crypto@30000 {
158 compatible = "fsl,sec2.2", "fsl,sec2.1", "fsl,sec2.0";
159 reg = <0x30000 0x10000>;
160 interrupts = <11 0x8>;
161 interrupt-parent = <&ipic>;
162 fsl,num-channels = <1>;
163 fsl,channel-fifo-len = <24>;
164 fsl,exec-units-mask = <0x4c>;
165 fsl,descriptor-types-mask = <0x0122003f>;
166 };
168 ipic: pic@700 {
169 interrupt-controller;
170 #address-cells = <0>;
171 #interrupt-cells = <2>;
172 reg = <0x700 0x100>;
173 device_type = "ipic";
174 };
176 par_io@1400 {
177 reg = <0x1400 0x100>;
178 device_type = "par_io";
179 num-ports = <7>;
181 pio3: ucc_pin@03 {
182 pio-map = <
183 /* port pin dir open_drain assignment has_irq */
184 3 4 3 0 2 0 /* MDIO */
185 3 5 1 0 2 0 /* MDC */
186 0 13 2 0 1 0 /* RX_CLK (CLK9) */
187 3 24 2 0 1 0 /* TX_CLK (CLK10) */
188 1 0 1 0 1 0 /* TxD0 */
189 1 1 1 0 1 0 /* TxD1 */
190 1 2 1 0 1 0 /* TxD2 */
191 1 3 1 0 1 0 /* TxD3 */
192 1 4 2 0 1 0 /* RxD0 */
193 1 5 2 0 1 0 /* RxD1 */
194 1 6 2 0 1 0 /* RxD2 */
195 1 7 2 0 1 0 /* RxD3 */
196 1 8 2 0 1 0 /* RX_ER */
197 1 9 1 0 1 0 /* TX_ER */
198 1 10 2 0 1 0 /* RX_DV */
199 1 11 2 0 1 0 /* COL */
200 1 12 1 0 1 0 /* TX_EN */
201 1 13 2 0 1 0>; /* CRS */
202 };
203 pio4: ucc_pin@04 {
204 pio-map = <
205 /* port pin dir open_drain assignment has_irq */
206 3 31 2 0 1 0 /* RX_CLK (CLK7) */
207 3 6 2 0 1 0 /* TX_CLK (CLK8) */
208 1 18 1 0 1 0 /* TxD0 */
209 1 19 1 0 1 0 /* TxD1 */
210 1 20 1 0 1 0 /* TxD2 */
211 1 21 1 0 1 0 /* TxD3 */
212 1 22 2 0 1 0 /* RxD0 */
213 1 23 2 0 1 0 /* RxD1 */
214 1 24 2 0 1 0 /* RxD2 */
215 1 25 2 0 1 0 /* RxD3 */
216 1 26 2 0 1 0 /* RX_ER */
217 1 27 1 0 1 0 /* TX_ER */
218 1 28 2 0 1 0 /* RX_DV */
219 1 29 2 0 1 0 /* COL */
220 1 30 1 0 1 0 /* TX_EN */
221 1 31 2 0 1 0>; /* CRS */
222 };
223 pio5: ucc_pin@05 {
224 pio-map = <
225 /*
226 * open has
227 * port pin dir drain sel irq
228 */
229 2 0 1 0 2 0 /* TxD5 */
230 2 8 2 0 2 0 /* RxD5 */
232 2 29 2 0 0 0 /* CTS5 */
233 2 31 1 0 2 0 /* RTS5 */
235 2 24 2 0 0 0 /* CD */
237 >;
238 };
240 };
241 };
243 qe@e0100000 {
244 #address-cells = <1>;
245 #size-cells = <1>;
246 device_type = "qe";
247 compatible = "fsl,qe";
248 ranges = <0x0 0xe0100000 0x00100000>;
249 reg = <0xe0100000 0x480>;
250 brg-frequency = <0>;
251 bus-frequency = <198000000>;
253 muram@10000 {
254 #address-cells = <1>;
255 #size-cells = <1>;
256 compatible = "fsl,qe-muram", "fsl,cpm-muram";
257 ranges = <0x0 0x00010000 0x00004000>;
259 data-only@0 {
260 compatible = "fsl,qe-muram-data",
261 "fsl,cpm-muram-data";
262 reg = <0x0 0x4000>;
263 };
264 };
266 spi@4c0 {
267 cell-index = <0>;
268 compatible = "fsl,spi";
269 reg = <0x4c0 0x40>;
270 interrupts = <2>;
271 interrupt-parent = <&qeic>;
272 mode = "cpu";
273 };
275 spi@500 {
276 cell-index = <1>;
277 compatible = "fsl,spi";
278 reg = <0x500 0x40>;
279 interrupts = <1>;
280 interrupt-parent = <&qeic>;
281 mode = "cpu";
282 };
284 usb@6c0 {
285 compatible = "qe_udc";
286 reg = <0x6c0 0x40 0x8b00 0x100>;
287 interrupts = <11>;
288 interrupt-parent = <&qeic>;
289 mode = "slave";
290 };
292 enet0: ucc@2200 {
293 device_type = "network";
294 compatible = "ucc_geth";
295 cell-index = <3>;
296 reg = <0x2200 0x200>;
297 interrupts = <34>;
298 interrupt-parent = <&qeic>;
299 local-mac-address = [ 00 00 00 00 00 00 ];
300 rx-clock-name = "clk9";
301 tx-clock-name = "clk10";
302 phy-handle = <&phy3>;
303 pio-handle = <&pio3>;
304 };
306 enet1: ucc@3200 {
307 device_type = "network";
308 compatible = "ucc_geth";
309 cell-index = <4>;
310 reg = <0x3200 0x200>;
311 interrupts = <35>;
312 interrupt-parent = <&qeic>;
313 local-mac-address = [ 00 00 00 00 00 00 ];
314 rx-clock-name = "clk7";
315 tx-clock-name = "clk8";
316 phy-handle = <&phy4>;
317 pio-handle = <&pio4>;
318 };
320 ucc@2400 {
321 device_type = "serial";
322 compatible = "ucc_uart";
323 cell-index = <5>; /* The UCC number, 1-7*/
324 port-number = <0>; /* Which ttyQEx device */
325 soft-uart; /* We need Soft-UART */
326 reg = <0x2400 0x200>;
327 interrupts = <40>; /* From Table 18-12 */
328 interrupt-parent = < &qeic >;
329 /*
330 * For Soft-UART, we need to set TX to 1X, which
331 * means specifying separate clock sources.
332 */
333 rx-clock-name = "brg5";
334 tx-clock-name = "brg6";
335 pio-handle = < &pio5 >;
336 };
339 mdio@2320 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <0x2320 0x18>;
343 compatible = "fsl,ucc-mdio";
345 phy3: ethernet-phy@03 {
346 interrupt-parent = <&ipic>;
347 interrupts = <17 0x8>;
348 reg = <0x3>;
349 device_type = "ethernet-phy";
350 };
351 phy4: ethernet-phy@04 {
352 interrupt-parent = <&ipic>;
353 interrupts = <18 0x8>;
354 reg = <0x4>;
355 device_type = "ethernet-phy";
356 };
357 };
359 qeic: interrupt-controller@80 {
360 interrupt-controller;
361 compatible = "fsl,qe-ic";
362 #address-cells = <0>;
363 #interrupt-cells = <1>;
364 reg = <0x80 0x80>;
365 big-endian;
366 interrupts = <32 0x8 33 0x8>; //high:32 low:33
367 interrupt-parent = <&ipic>;
368 };
369 };
371 pci0: pci@e0008500 {
372 cell-index = <1>;
373 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
374 interrupt-map = <
375 /* IDSEL 0x11 AD17 */
376 0x8800 0x0 0x0 0x1 &ipic 20 0x8
377 0x8800 0x0 0x0 0x2 &ipic 21 0x8
378 0x8800 0x0 0x0 0x3 &ipic 22 0x8
379 0x8800 0x0 0x0 0x4 &ipic 23 0x8
381 /* IDSEL 0x12 AD18 */
382 0x9000 0x0 0x0 0x1 &ipic 22 0x8
383 0x9000 0x0 0x0 0x2 &ipic 23 0x8
384 0x9000 0x0 0x0 0x3 &ipic 20 0x8
385 0x9000 0x0 0x0 0x4 &ipic 21 0x8
387 /* IDSEL 0x13 AD19 */
388 0x9800 0x0 0x0 0x1 &ipic 23 0x8
389 0x9800 0x0 0x0 0x2 &ipic 20 0x8
390 0x9800 0x0 0x0 0x3 &ipic 21 0x8
391 0x9800 0x0 0x0 0x4 &ipic 22 0x8
393 /* IDSEL 0x15 AD21*/
394 0xa800 0x0 0x0 0x1 &ipic 20 0x8
395 0xa800 0x0 0x0 0x2 &ipic 21 0x8
396 0xa800 0x0 0x0 0x3 &ipic 22 0x8
397 0xa800 0x0 0x0 0x4 &ipic 23 0x8
399 /* IDSEL 0x16 AD22*/
400 0xb000 0x0 0x0 0x1 &ipic 23 0x8
401 0xb000 0x0 0x0 0x2 &ipic 20 0x8
402 0xb000 0x0 0x0 0x3 &ipic 21 0x8
403 0xb000 0x0 0x0 0x4 &ipic 22 0x8
405 /* IDSEL 0x17 AD23*/
406 0xb800 0x0 0x0 0x1 &ipic 22 0x8
407 0xb800 0x0 0x0 0x2 &ipic 23 0x8
408 0xb800 0x0 0x0 0x3 &ipic 20 0x8
409 0xb800 0x0 0x0 0x4 &ipic 21 0x8
411 /* IDSEL 0x18 AD24*/
412 0xc000 0x0 0x0 0x1 &ipic 21 0x8
413 0xc000 0x0 0x0 0x2 &ipic 22 0x8
414 0xc000 0x0 0x0 0x3 &ipic 23 0x8
415 0xc000 0x0 0x0 0x4 &ipic 20 0x8>;
416 interrupt-parent = <&ipic>;
417 interrupts = <66 0x8>;
418 bus-range = <0x0 0x0>;
419 ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
420 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
421 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
422 clock-frequency = <0>;
423 #interrupt-cells = <1>;
424 #size-cells = <2>;
425 #address-cells = <3>;
426 reg = <0xe0008500 0x100 /* internal registers */
427 0xe0008300 0x8>; /* config space access registers */
428 compatible = "fsl,mpc8349-pci";
429 device_type = "pci";
430 };
431 };