| blob | 37b789510d68bc160b191a53717a916e293ea361 |
1 /*
2 * MPC8360E RDK Device Tree Source
3 *
4 * Copyright 2006 Freescale Semiconductor Inc.
5 * Copyright 2007-2008 MontaVista Software, Inc.
6 *
7 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
15 /dts-v1/;
17 / {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "fsl,mpc8360rdk";
22 aliases {
23 serial0 = &serial0;
24 serial1 = &serial1;
25 serial2 = &serial2;
26 serial3 = &serial3;
27 ethernet0 = &enet0;
28 ethernet1 = &enet1;
29 ethernet2 = &enet2;
30 ethernet3 = &enet3;
31 pci0 = &pci0;
32 };
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
38 PowerPC,8360@0 {
39 device_type = "cpu";
40 reg = <0>;
41 d-cache-line-size = <32>;
42 i-cache-line-size = <32>;
43 d-cache-size = <32768>;
44 i-cache-size = <32768>;
45 /* filled by u-boot */
46 timebase-frequency = <0>;
47 bus-frequency = <0>;
48 clock-frequency = <0>;
49 };
50 };
52 memory {
53 device_type = "memory";
54 /* filled by u-boot */
55 reg = <0 0>;
56 };
58 soc@e0000000 {
59 #address-cells = <1>;
60 #size-cells = <1>;
61 device_type = "soc";
62 compatible = "fsl,mpc8360-immr", "fsl,immr", "fsl,soc",
63 "simple-bus";
64 ranges = <0 0xe0000000 0x200000>;
65 reg = <0xe0000000 0x200>;
66 /* filled by u-boot */
67 bus-frequency = <0>;
69 wdt@200 {
70 compatible = "mpc83xx_wdt";
71 reg = <0x200 0x100>;
72 };
74 i2c@3000 {
75 #address-cells = <1>;
76 #size-cells = <0>;
77 cell-index = <0>;
78 compatible = "fsl-i2c";
79 reg = <0x3000 0x100>;
80 interrupts = <14 8>;
81 interrupt-parent = <&ipic>;
82 dfsrr;
83 };
85 i2c@3100 {
86 #address-cells = <1>;
87 #size-cells = <0>;
88 cell-index = <1>;
89 compatible = "fsl-i2c";
90 reg = <0x3100 0x100>;
91 interrupts = <16 8>;
92 interrupt-parent = <&ipic>;
93 dfsrr;
94 };
96 serial0: serial@4500 {
97 device_type = "serial";
98 compatible = "ns16550";
99 reg = <0x4500 0x100>;
100 interrupts = <9 8>;
101 interrupt-parent = <&ipic>;
102 /* filled by u-boot */
103 clock-frequency = <0>;
104 };
106 serial1: serial@4600 {
107 device_type = "serial";
108 compatible = "ns16550";
109 reg = <0x4600 0x100>;
110 interrupts = <10 8>;
111 interrupt-parent = <&ipic>;
112 /* filled by u-boot */
113 clock-frequency = <0>;
114 };
116 dma@82a8 {
117 #address-cells = <1>;
118 #size-cells = <1>;
119 compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
120 reg = <0x82a8 4>;
121 ranges = <0 0x8100 0x1a8>;
122 interrupt-parent = <&ipic>;
123 interrupts = <71 8>;
124 cell-index = <0>;
125 dma-channel@0 {
126 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
127 reg = <0 0x80>;
128 cell-index = <0>;
129 interrupt-parent = <&ipic>;
130 interrupts = <71 8>;
131 };
132 dma-channel@80 {
133 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
134 reg = <0x80 0x80>;
135 cell-index = <1>;
136 interrupt-parent = <&ipic>;
137 interrupts = <71 8>;
138 };
139 dma-channel@100 {
140 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
141 reg = <0x100 0x80>;
142 cell-index = <2>;
143 interrupt-parent = <&ipic>;
144 interrupts = <71 8>;
145 };
146 dma-channel@180 {
147 compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
148 reg = <0x180 0x28>;
149 cell-index = <3>;
150 interrupt-parent = <&ipic>;
151 interrupts = <71 8>;
152 };
153 };
155 crypto@30000 {
156 compatible = "fsl,sec2.0";
157 reg = <0x30000 0x10000>;
158 interrupts = <11 0x8>;
159 interrupt-parent = <&ipic>;
160 fsl,num-channels = <4>;
161 fsl,channel-fifo-len = <24>;
162 fsl,exec-units-mask = <0x7e>;
163 fsl,descriptor-types-mask = <0x01010ebf>;
164 };
166 ipic: interrupt-controller@700 {
167 #address-cells = <0>;
168 #interrupt-cells = <2>;
169 compatible = "fsl,pq2pro-pic", "fsl,ipic";
170 interrupt-controller;
171 reg = <0x700 0x100>;
172 };
174 qe_pio_b: gpio-controller@1418 {
175 #gpio-cells = <2>;
176 compatible = "fsl,mpc8360-qe-pario-bank",
177 "fsl,mpc8323-qe-pario-bank";
178 reg = <0x1418 0x18>;
179 gpio-controller;
180 };
182 qe_pio_e: gpio-controller@1460 {
183 #gpio-cells = <2>;
184 compatible = "fsl,mpc8360-qe-pario-bank",
185 "fsl,mpc8323-qe-pario-bank";
186 reg = <0x1460 0x18>;
187 gpio-controller;
188 };
190 qe@100000 {
191 #address-cells = <1>;
192 #size-cells = <1>;
193 device_type = "qe";
194 compatible = "fsl,qe", "simple-bus";
195 ranges = <0 0x100000 0x100000>;
196 reg = <0x100000 0x480>;
197 /* filled by u-boot */
198 clock-frequency = <0>;
199 bus-frequency = <0>;
200 brg-frequency = <0>;
202 muram@10000 {
203 #address-cells = <1>;
204 #size-cells = <1>;
205 compatible = "fsl,qe-muram", "fsl,cpm-muram";
206 ranges = <0 0x10000 0xc000>;
208 data-only@0 {
209 compatible = "fsl,qe-muram-data",
210 "fsl,cpm-muram-data";
211 reg = <0 0xc000>;
212 };
213 };
215 timer@440 {
216 compatible = "fsl,mpc8360-qe-gtm",
217 "fsl,qe-gtm", "fsl,gtm";
218 reg = <0x440 0x40>;
219 interrupts = <12 13 14 15>;
220 interrupt-parent = <&qeic>;
221 clock-frequency = <166666666>;
222 };
224 usb@6c0 {
225 compatible = "fsl,mpc8360-qe-usb",
226 "fsl,mpc8323-qe-usb";
227 reg = <0x6c0 0x40 0x8b00 0x100>;
228 interrupts = <11>;
229 interrupt-parent = <&qeic>;
230 fsl,fullspeed-clock = "clk21";
231 gpios = <&qe_pio_b 2 0 /* USBOE */
232 &qe_pio_b 3 0 /* USBTP */
233 &qe_pio_b 8 0 /* USBTN */
234 &qe_pio_b 9 0 /* USBRP */
235 &qe_pio_b 11 0 /* USBRN */
236 &qe_pio_e 20 0 /* SPEED */
237 &qe_pio_e 21 1 /* POWER */>;
238 };
240 spi@4c0 {
241 cell-index = <0>;
242 compatible = "fsl,spi";
243 reg = <0x4c0 0x40>;
244 interrupts = <2>;
245 interrupt-parent = <&qeic>;
246 mode = "cpu-qe";
247 };
249 spi@500 {
250 cell-index = <1>;
251 compatible = "fsl,spi";
252 reg = <0x500 0x40>;
253 interrupts = <1>;
254 interrupt-parent = <&qeic>;
255 mode = "cpu-qe";
256 };
258 enet0: ucc@2000 {
259 device_type = "network";
260 compatible = "ucc_geth";
261 cell-index = <1>;
262 reg = <0x2000 0x200>;
263 interrupts = <32>;
264 interrupt-parent = <&qeic>;
265 rx-clock-name = "none";
266 tx-clock-name = "clk9";
267 phy-handle = <&phy2>;
268 phy-connection-type = "rgmii-rxid";
269 /* filled by u-boot */
270 local-mac-address = [ 00 00 00 00 00 00 ];
271 };
273 enet1: ucc@3000 {
274 device_type = "network";
275 compatible = "ucc_geth";
276 cell-index = <2>;
277 reg = <0x3000 0x200>;
278 interrupts = <33>;
279 interrupt-parent = <&qeic>;
280 rx-clock-name = "none";
281 tx-clock-name = "clk4";
282 phy-handle = <&phy4>;
283 phy-connection-type = "rgmii-rxid";
284 /* filled by u-boot */
285 local-mac-address = [ 00 00 00 00 00 00 ];
286 };
288 enet2: ucc@2600 {
289 device_type = "network";
290 compatible = "ucc_geth";
291 cell-index = <7>;
292 reg = <0x2600 0x200>;
293 interrupts = <42>;
294 interrupt-parent = <&qeic>;
295 rx-clock-name = "clk20";
296 tx-clock-name = "clk19";
297 phy-handle = <&phy1>;
298 phy-connection-type = "mii";
299 /* filled by u-boot */
300 local-mac-address = [ 00 00 00 00 00 00 ];
301 };
303 enet3: ucc@3200 {
304 device_type = "network";
305 compatible = "ucc_geth";
306 cell-index = <4>;
307 reg = <0x3200 0x200>;
308 interrupts = <35>;
309 interrupt-parent = <&qeic>;
310 rx-clock-name = "clk8";
311 tx-clock-name = "clk7";
312 phy-handle = <&phy3>;
313 phy-connection-type = "mii";
314 /* filled by u-boot */
315 local-mac-address = [ 00 00 00 00 00 00 ];
316 };
318 mdio@2120 {
319 #address-cells = <1>;
320 #size-cells = <0>;
321 compatible = "fsl,ucc-mdio";
322 reg = <0x2120 0x18>;
324 phy1: ethernet-phy@1 {
325 device_type = "ethernet-phy";
326 compatible = "national,DP83848VV";
327 reg = <1>;
328 };
330 phy2: ethernet-phy@2 {
331 device_type = "ethernet-phy";
332 compatible = "broadcom,BCM5481UA2KMLG";
333 reg = <2>;
334 };
336 phy3: ethernet-phy@3 {
337 device_type = "ethernet-phy";
338 compatible = "national,DP83848VV";
339 reg = <3>;
340 };
342 phy4: ethernet-phy@4 {
343 device_type = "ethernet-phy";
344 compatible = "broadcom,BCM5481UA2KMLG";
345 reg = <4>;
346 };
347 };
349 serial2: ucc@2400 {
350 device_type = "serial";
351 compatible = "ucc_uart";
352 reg = <0x2400 0x200>;
353 cell-index = <5>;
354 port-number = <0>;
355 rx-clock-name = "brg7";
356 tx-clock-name = "brg8";
357 interrupts = <40>;
358 interrupt-parent = <&qeic>;
359 soft-uart;
360 };
362 serial3: ucc@3400 {
363 device_type = "serial";
364 compatible = "ucc_uart";
365 reg = <0x3400 0x200>;
366 cell-index = <6>;
367 port-number = <1>;
368 rx-clock-name = "brg13";
369 tx-clock-name = "brg14";
370 interrupts = <41>;
371 interrupt-parent = <&qeic>;
372 soft-uart;
373 };
375 qeic: interrupt-controller@80 {
376 #address-cells = <0>;
377 #interrupt-cells = <1>;
378 compatible = "fsl,qe-ic";
379 interrupt-controller;
380 reg = <0x80 0x80>;
381 big-endian;
382 interrupts = <32 8 33 8>;
383 interrupt-parent = <&ipic>;
384 };
385 };
386 };
388 localbus@e0005000 {
389 #address-cells = <2>;
390 #size-cells = <1>;
391 compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
392 "simple-bus";
393 reg = <0xe0005000 0xd8>;
394 ranges = <0 0 0xff800000 0x0800000
395 1 0 0x60000000 0x0001000
396 2 0 0x70000000 0x4000000>;
398 flash@0,0 {
399 compatible = "intel,PC28F640P30T85", "cfi-flash";
400 reg = <0 0 0x800000>;
401 bank-width = <2>;
402 device-width = <1>;
403 };
405 upm@1,0 {
406 compatible = "fsl,upm-nand";
407 reg = <1 0 1>;
408 fsl,upm-addr-offset = <16>;
409 fsl,upm-cmd-offset = <8>;
410 gpios = <&qe_pio_e 18 0>;
412 flash {
413 compatible = "stm,nand512-a";
414 };
415 };
417 display@2,0 {
418 device_type = "display";
419 compatible = "fujitsu,MB86277", "fujitsu,mint";
420 reg = <2 0 0x4000000>;
421 fujitsu,sh3;
422 little-endian;
423 /* filled by u-boot */
424 address = <0>;
425 depth = <0>;
426 width = <0>;
427 height = <0>;
428 linebytes = <0>;
429 /* linux,opened; - added by uboot */
430 };
431 };
433 pci0: pci@e0008500 {
434 #address-cells = <3>;
435 #size-cells = <2>;
436 #interrupt-cells = <1>;
437 device_type = "pci";
438 compatible = "fsl,mpc8360-pci", "fsl,mpc8349-pci";
439 reg = <0xe0008500 0x100 /* internal registers */
440 0xe0008300 0x8>; /* config space access registers */
441 ranges = <0x02000000 0 0x90000000 0x90000000 0 0x10000000
442 0x42000000 0 0x80000000 0x80000000 0 0x10000000
443 0x01000000 0 0xe0300000 0xe0300000 0 0x00100000>;
444 interrupts = <66 8>;
445 interrupt-parent = <&ipic>;
446 interrupt-map-mask = <0xf800 0 0 7>;
447 interrupt-map = </* miniPCI0 IDSEL 0x14 AD20 */
448 0xa000 0 0 1 &ipic 18 8
449 0xa000 0 0 2 &ipic 19 8
451 /* PCI1 IDSEL 0x15 AD21 */
452 0xa800 0 0 1 &ipic 19 8
453 0xa800 0 0 2 &ipic 20 8
454 0xa800 0 0 3 &ipic 21 8
455 0xa800 0 0 4 &ipic 18 8>;
456 /* filled by u-boot */
457 bus-range = <0 0>;
458 clock-frequency = <0>;
459 };
460 };