arch/powerpc/boot/dts/mpc8540ads.dts

   1 /*
   2  * MPC8540 ADS Device Tree Source
   3  *
   4  * Copyright 2006, 2008 Freescale Semiconductor Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11
  12 /dts-v1/;
  13
  14 / {
  15         model = "MPC8540ADS";
  16         compatible = "MPC8540ADS", "MPC85xxADS";
  17         #address-cells = <1>;
  18         #size-cells = <1>;
  19
  20         aliases {
  21                 ethernet0 = &enet0;
  22                 ethernet1 = &enet1;
  23                 ethernet2 = &enet2;
  24                 serial0 = &serial0;
  25                 serial1 = &serial1;
  26                 pci0 = &pci0;
  27         };
  28
  29         cpus {
  30                 #address-cells = <1>;
  31                 #size-cells = <0>;
  32
  33                 PowerPC,8540@0 {
  34                         device_type = "cpu";
  35                         reg = <0x0>;
  36                         d-cache-line-size = <32>;       // 32 bytes
  37                         i-cache-line-size = <32>;       // 32 bytes
  38                         d-cache-size = <0x8000>;                // L1, 32K
  39                         i-cache-size = <0x8000>;                // L1, 32K
  40                         timebase-frequency = <0>;       //  33 MHz, from uboot
  41                         bus-frequency = <0>;    // 166 MHz
  42                         clock-frequency = <0>;  // 825 MHz, from uboot
  43                         next-level-cache = <&L2>;
  44                 };
  45         };
  46
  47         memory {
  48                 device_type = "memory";
  49                 reg = <0x0 0x8000000>;  // 128M at 0x0
  50         };
  51
  52         soc8540@e0000000 {
  53                 #address-cells = <1>;
  54                 #size-cells = <1>;
  55                 device_type = "soc";
  56                 compatible = "simple-bus";
  57                 ranges = <0x0 0xe0000000 0x100000>;
  58                 reg = <0xe0000000 0x100000>;    // CCSRBAR 1M
  59                 bus-frequency = <0>;
  60
  61                 memory-controller@2000 {
  62                         compatible = "fsl,8540-memory-controller";
  63                         reg = <0x2000 0x1000>;
  64                         interrupt-parent = <&mpic>;
  65                         interrupts = <18 2>;
  66                 };
  67
  68                 L2: l2-cache-controller@20000 {
  69                         compatible = "fsl,8540-l2-cache-controller";
  70                         reg = <0x20000 0x1000>;
  71                         cache-line-size = <32>; // 32 bytes
  72                         cache-size = <0x40000>; // L2, 256K
  73                         interrupt-parent = <&mpic>;
  74                         interrupts = <16 2>;
  75                 };
  76
  77                 i2c@3000 {
  78                         #address-cells = <1>;
  79                         #size-cells = <0>;
  80                         cell-index = <0>;
  81                         compatible = "fsl-i2c";
  82                         reg = <0x3000 0x100>;
  83                         interrupts = <43 2>;
  84                         interrupt-parent = <&mpic>;
  85                         dfsrr;
  86                 };
  87
  88                 dma@21300 {
  89                         #address-cells = <1>;
  90                         #size-cells = <1>;
  91                         compatible = "fsl,mpc8540-dma", "fsl,eloplus-dma";
  92                         reg = <0x21300 0x4>;
  93                         ranges = <0x0 0x21100 0x200>;
  94                         cell-index = <0>;
  95                         dma-channel@0 {
  96                                 compatible = "fsl,mpc8540-dma-channel",
  97                                                 "fsl,eloplus-dma-channel";
  98                                 reg = <0x0 0x80>;
  99                                 cell-index = <0>;
 100                                 interrupt-parent = <&mpic>;
 101                                 interrupts = <20 2>;
 102                         };
 103                         dma-channel@80 {
 104                                 compatible = "fsl,mpc8540-dma-channel",
 105                                                 "fsl,eloplus-dma-channel";
 106                                 reg = <0x80 0x80>;
 107                                 cell-index = <1>;
 108                                 interrupt-parent = <&mpic>;
 109                                 interrupts = <21 2>;
 110                         };
 111                         dma-channel@100 {
 112                                 compatible = "fsl,mpc8540-dma-channel",
 113                                                 "fsl,eloplus-dma-channel";
 114                                 reg = <0x100 0x80>;
 115                                 cell-index = <2>;
 116                                 interrupt-parent = <&mpic>;
 117                                 interrupts = <22 2>;
 118                         };
 119                         dma-channel@180 {
 120                                 compatible = "fsl,mpc8540-dma-channel",
 121                                                 "fsl,eloplus-dma-channel";
 122                                 reg = <0x180 0x80>;
 123                                 cell-index = <3>;
 124                                 interrupt-parent = <&mpic>;
 125                                 interrupts = <23 2>;
 126                         };
 127                 };
 128
 129                 enet0: ethernet@24000 {
 130                         #address-cells = <1>;
 131                         #size-cells = <1>;
 132                         cell-index = <0>;
 133                         device_type = "network";
 134                         model = "TSEC";
 135                         compatible = "gianfar";
 136                         reg = <0x24000 0x1000>;
 137                         ranges = <0x0 0x24000 0x1000>;
 138                         local-mac-address = [ 00 00 00 00 00 00 ];
 139                         interrupts = <29 2 30 2 34 2>;
 140                         interrupt-parent = <&mpic>;
 141                         tbi-handle = <&tbi0>;
 142                         phy-handle = <&phy0>;
 143
 144                         mdio@520 {
 145                                 #address-cells = <1>;
 146                                 #size-cells = <0>;
 147                                 compatible = "fsl,gianfar-mdio";
 148                                 reg = <0x520 0x20>;
 149
 150                                 phy0: ethernet-phy@0 {
 151                                         interrupt-parent = <&mpic>;
 152                                         interrupts = <5 1>;
 153                                         reg = <0x0>;
 154                                         device_type = "ethernet-phy";
 155                                 };
 156                                 phy1: ethernet-phy@1 {
 157                                         interrupt-parent = <&mpic>;
 158                                         interrupts = <5 1>;
 159                                         reg = <0x1>;
 160                                         device_type = "ethernet-phy";
 161                                 };
 162                                 phy3: ethernet-phy@3 {
 163                                         interrupt-parent = <&mpic>;
 164                                         interrupts = <7 1>;
 165                                         reg = <0x3>;
 166                                         device_type = "ethernet-phy";
 167                                 };
 168                                 tbi0: tbi-phy@11 {
 169                                         reg = <0x11>;
 170                                         device_type = "tbi-phy";
 171                                 };
 172                         };
 173                 };
 174
 175                 enet1: ethernet@25000 {
 176                         #address-cells = <1>;
 177                         #size-cells = <1>;
 178                         cell-index = <1>;
 179                         device_type = "network";
 180                         model = "TSEC";
 181                         compatible = "gianfar";
 182                         reg = <0x25000 0x1000>;
 183                         ranges = <0x0 0x25000 0x1000>;
 184                         local-mac-address = [ 00 00 00 00 00 00 ];
 185                         interrupts = <35 2 36 2 40 2>;
 186                         interrupt-parent = <&mpic>;
 187                         tbi-handle = <&tbi1>;
 188                         phy-handle = <&phy1>;
 189
 190                         mdio@520 {
 191                                 #address-cells = <1>;
 192                                 #size-cells = <0>;
 193                                 compatible = "fsl,gianfar-tbi";
 194                                 reg = <0x520 0x20>;
 195
 196                                 tbi1: tbi-phy@11 {
 197                                         reg = <0x11>;
 198                                         device_type = "tbi-phy";
 199                                 };
 200                         };
 201                 };
 202
 203                 enet2: ethernet@26000 {
 204                         #address-cells = <1>;
 205                         #size-cells = <1>;
 206                         cell-index = <2>;
 207                         device_type = "network";
 208                         model = "FEC";
 209                         compatible = "gianfar";
 210                         reg = <0x26000 0x1000>;
 211                         ranges = <0x0 0x26000 0x1000>;
 212                         local-mac-address = [ 00 00 00 00 00 00 ];
 213                         interrupts = <41 2>;
 214                         interrupt-parent = <&mpic>;
 215                         tbi-handle = <&tbi2>;
 216                         phy-handle = <&phy3>;
 217
 218                         mdio@520 {
 219                                 #address-cells = <1>;
 220                                 #size-cells = <0>;
 221                                 compatible = "fsl,gianfar-tbi";
 222                                 reg = <0x520 0x20>;
 223
 224                                 tbi2: tbi-phy@11 {
 225                                         reg = <0x11>;
 226                                         device_type = "tbi-phy";
 227                                 };
 228                         };
 229                 };
 230
 231                 serial0: serial@4500 {
 232                         cell-index = <0>;
 233                         device_type = "serial";
 234                         compatible = "ns16550";
 235                         reg = <0x4500 0x100>;   // reg base, size
 236                         clock-frequency = <0>;  // should we fill in in uboot?
 237                         interrupts = <42 2>;
 238                         interrupt-parent = <&mpic>;
 239                 };
 240
 241                 serial1: serial@4600 {
 242                         cell-index = <1>;
 243                         device_type = "serial";
 244                         compatible = "ns16550";
 245                         reg = <0x4600 0x100>;   // reg base, size
 246                         clock-frequency = <0>;  // should we fill in in uboot?
 247                         interrupts = <42 2>;
 248                         interrupt-parent = <&mpic>;
 249                 };
 250                 mpic: pic@40000 {
 251                         interrupt-controller;
 252                         #address-cells = <0>;
 253                         #interrupt-cells = <2>;
 254                         reg = <0x40000 0x40000>;
 255                         compatible = "chrp,open-pic";
 256                         device_type = "open-pic";
 257                 };
 258         };
 259
 260         pci0: pci@e0008000 {
 261                 cell-index = <0>;
 262                 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
 263                 interrupt-map = <
 264
 265                         /* IDSEL 0x02 */
 266                         0x1000 0x0 0x0 0x1 &mpic 0x1 0x1
 267                         0x1000 0x0 0x0 0x2 &mpic 0x2 0x1
 268                         0x1000 0x0 0x0 0x3 &mpic 0x3 0x1
 269                         0x1000 0x0 0x0 0x4 &mpic 0x4 0x1
 270
 271                         /* IDSEL 0x03 */
 272                         0x1800 0x0 0x0 0x1 &mpic 0x4 0x1
 273                         0x1800 0x0 0x0 0x2 &mpic 0x1 0x1
 274                         0x1800 0x0 0x0 0x3 &mpic 0x2 0x1
 275                         0x1800 0x0 0x0 0x4 &mpic 0x3 0x1
 276
 277                         /* IDSEL 0x04 */
 278                         0x2000 0x0 0x0 0x1 &mpic 0x3 0x1
 279                         0x2000 0x0 0x0 0x2 &mpic 0x4 0x1
 280                         0x2000 0x0 0x0 0x3 &mpic 0x1 0x1
 281                         0x2000 0x0 0x0 0x4 &mpic 0x2 0x1
 282
 283                         /* IDSEL 0x05 */
 284                         0x2800 0x0 0x0 0x1 &mpic 0x2 0x1
 285                         0x2800 0x0 0x0 0x2 &mpic 0x3 0x1
 286                         0x2800 0x0 0x0 0x3 &mpic 0x4 0x1
 287                         0x2800 0x0 0x0 0x4 &mpic 0x1 0x1
 288
 289                         /* IDSEL 0x0c */
 290                         0x6000 0x0 0x0 0x1 &mpic 0x1 0x1
 291                         0x6000 0x0 0x0 0x2 &mpic 0x2 0x1
 292                         0x6000 0x0 0x0 0x3 &mpic 0x3 0x1
 293                         0x6000 0x0 0x0 0x4 &mpic 0x4 0x1
 294
 295                         /* IDSEL 0x0d */
 296                         0x6800 0x0 0x0 0x1 &mpic 0x4 0x1
 297                         0x6800 0x0 0x0 0x2 &mpic 0x1 0x1
 298                         0x6800 0x0 0x0 0x3 &mpic 0x2 0x1
 299                         0x6800 0x0 0x0 0x4 &mpic 0x3 0x1
 300
 301                         /* IDSEL 0x0e */
 302                         0x7000 0x0 0x0 0x1 &mpic 0x3 0x1
 303                         0x7000 0x0 0x0 0x2 &mpic 0x4 0x1
 304                         0x7000 0x0 0x0 0x3 &mpic 0x1 0x1
 305                         0x7000 0x0 0x0 0x4 &mpic 0x2 0x1
 306
 307                         /* IDSEL 0x0f */
 308                         0x7800 0x0 0x0 0x1 &mpic 0x2 0x1
 309                         0x7800 0x0 0x0 0x2 &mpic 0x3 0x1
 310                         0x7800 0x0 0x0 0x3 &mpic 0x4 0x1
 311                         0x7800 0x0 0x0 0x4 &mpic 0x1 0x1
 312
 313                         /* IDSEL 0x12 */
 314                         0x9000 0x0 0x0 0x1 &mpic 0x1 0x1
 315                         0x9000 0x0 0x0 0x2 &mpic 0x2 0x1
 316                         0x9000 0x0 0x0 0x3 &mpic 0x3 0x1
 317                         0x9000 0x0 0x0 0x4 &mpic 0x4 0x1
 318
 319                         /* IDSEL 0x13 */
 320                         0x9800 0x0 0x0 0x1 &mpic 0x4 0x1
 321                         0x9800 0x0 0x0 0x2 &mpic 0x1 0x1
 322                         0x9800 0x0 0x0 0x3 &mpic 0x2 0x1
 323                         0x9800 0x0 0x0 0x4 &mpic 0x3 0x1
 324
 325                         /* IDSEL 0x14 */
 326                         0xa000 0x0 0x0 0x1 &mpic 0x3 0x1
 327                         0xa000 0x0 0x0 0x2 &mpic 0x4 0x1
 328                         0xa000 0x0 0x0 0x3 &mpic 0x1 0x1
 329                         0xa000 0x0 0x0 0x4 &mpic 0x2 0x1
 330
 331                         /* IDSEL 0x15 */
 332                         0xa800 0x0 0x0 0x1 &mpic 0x2 0x1
 333                         0xa800 0x0 0x0 0x2 &mpic 0x3 0x1
 334                         0xa800 0x0 0x0 0x3 &mpic 0x4 0x1
 335                         0xa800 0x0 0x0 0x4 &mpic 0x1 0x1>;
 336                 interrupt-parent = <&mpic>;
 337                 interrupts = <24 2>;
 338                 bus-range = <0 0>;
 339                 ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
 340                           0x1000000 0x0 0x0 0xe2000000 0x0 0x100000>;
 341                 clock-frequency = <66666666>;
 342                 #interrupt-cells = <1>;
 343                 #size-cells = <2>;
 344                 #address-cells = <3>;
 345                 reg = <0xe0008000 0x1000>;
 346                 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
 347                 device_type = "pci";
 348         };
 349 };