| blob | dbd81a76474265134e0b2c8e3bbd30d2d05efb12 |
1 /*
2 * MPC8572 DS Device Tree Source
3 *
4 * Copyright 2007-2009 Freescale Semiconductor Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
12 /dts-v1/;
13 / {
14 model = "fsl,MPC8572DS";
15 compatible = "fsl,MPC8572DS";
16 #address-cells = <2>;
17 #size-cells = <2>;
19 aliases {
20 ethernet0 = &enet0;
21 ethernet1 = &enet1;
22 ethernet2 = &enet2;
23 ethernet3 = &enet3;
24 serial0 = &serial0;
25 serial1 = &serial1;
26 pci0 = &pci0;
27 pci1 = &pci1;
28 pci2 = &pci2;
29 };
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
35 PowerPC,8572@0 {
36 device_type = "cpu";
37 reg = <0x0>;
38 d-cache-line-size = <32>; // 32 bytes
39 i-cache-line-size = <32>; // 32 bytes
40 d-cache-size = <0x8000>; // L1, 32K
41 i-cache-size = <0x8000>; // L1, 32K
42 timebase-frequency = <0>;
43 bus-frequency = <0>;
44 clock-frequency = <0>;
45 next-level-cache = <&L2>;
46 };
48 PowerPC,8572@1 {
49 device_type = "cpu";
50 reg = <0x1>;
51 d-cache-line-size = <32>; // 32 bytes
52 i-cache-line-size = <32>; // 32 bytes
53 d-cache-size = <0x8000>; // L1, 32K
54 i-cache-size = <0x8000>; // L1, 32K
55 timebase-frequency = <0>;
56 bus-frequency = <0>;
57 clock-frequency = <0>;
58 next-level-cache = <&L2>;
59 };
60 };
62 memory {
63 device_type = "memory";
64 };
66 localbus@fffe05000 {
67 #address-cells = <2>;
68 #size-cells = <1>;
69 compatible = "fsl,mpc8572-elbc", "fsl,elbc", "simple-bus";
70 reg = <0xf 0xffe05000 0 0x1000>;
71 interrupts = <19 2>;
72 interrupt-parent = <&mpic>;
74 ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
75 0x1 0x0 0xf 0xe0000000 0x08000000
76 0x2 0x0 0xf 0xffa00000 0x00040000
77 0x3 0x0 0xf 0xffdf0000 0x00008000
78 0x4 0x0 0xf 0xffa40000 0x00040000
79 0x5 0x0 0xf 0xffa80000 0x00040000
80 0x6 0x0 0xf 0xffac0000 0x00040000>;
82 nor@0,0 {
83 #address-cells = <1>;
84 #size-cells = <1>;
85 compatible = "cfi-flash";
86 reg = <0x0 0x0 0x8000000>;
87 bank-width = <2>;
88 device-width = <1>;
90 ramdisk@0 {
91 reg = <0x0 0x03000000>;
92 read-only;
93 };
95 diagnostic@3000000 {
96 reg = <0x03000000 0x00e00000>;
97 read-only;
98 };
100 dink@3e00000 {
101 reg = <0x03e00000 0x00200000>;
102 read-only;
103 };
105 kernel@4000000 {
106 reg = <0x04000000 0x00400000>;
107 read-only;
108 };
110 jffs2@4400000 {
111 reg = <0x04400000 0x03b00000>;
112 };
114 dtb@7f00000 {
115 reg = <0x07f00000 0x00080000>;
116 read-only;
117 };
119 u-boot@7f80000 {
120 reg = <0x07f80000 0x00080000>;
121 read-only;
122 };
123 };
125 nand@2,0 {
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,mpc8572-fcm-nand",
129 "fsl,elbc-fcm-nand";
130 reg = <0x2 0x0 0x40000>;
132 u-boot@0 {
133 reg = <0x0 0x02000000>;
134 read-only;
135 };
137 jffs2@2000000 {
138 reg = <0x02000000 0x10000000>;
139 };
141 ramdisk@12000000 {
142 reg = <0x12000000 0x08000000>;
143 read-only;
144 };
146 kernel@1a000000 {
147 reg = <0x1a000000 0x04000000>;
148 };
150 dtb@1e000000 {
151 reg = <0x1e000000 0x01000000>;
152 read-only;
153 };
155 empty@1f000000 {
156 reg = <0x1f000000 0x21000000>;
157 };
158 };
160 nand@4,0 {
161 compatible = "fsl,mpc8572-fcm-nand",
162 "fsl,elbc-fcm-nand";
163 reg = <0x4 0x0 0x40000>;
164 };
166 nand@5,0 {
167 compatible = "fsl,mpc8572-fcm-nand",
168 "fsl,elbc-fcm-nand";
169 reg = <0x5 0x0 0x40000>;
170 };
172 nand@6,0 {
173 compatible = "fsl,mpc8572-fcm-nand",
174 "fsl,elbc-fcm-nand";
175 reg = <0x6 0x0 0x40000>;
176 };
177 };
179 soc8572@fffe00000 {
180 #address-cells = <1>;
181 #size-cells = <1>;
182 device_type = "soc";
183 compatible = "simple-bus";
184 ranges = <0x0 0xf 0xffe00000 0x100000>;
185 reg = <0xf 0xffe00000 0 0x1000>; // CCSRBAR & soc regs, remove once parse code for immrbase fixed
186 bus-frequency = <0>; // Filled out by uboot.
188 memory-controller@2000 {
189 compatible = "fsl,mpc8572-memory-controller";
190 reg = <0x2000 0x1000>;
191 interrupt-parent = <&mpic>;
192 interrupts = <18 2>;
193 };
195 memory-controller@6000 {
196 compatible = "fsl,mpc8572-memory-controller";
197 reg = <0x6000 0x1000>;
198 interrupt-parent = <&mpic>;
199 interrupts = <18 2>;
200 };
202 L2: l2-cache-controller@20000 {
203 compatible = "fsl,mpc8572-l2-cache-controller";
204 reg = <0x20000 0x1000>;
205 cache-line-size = <32>; // 32 bytes
206 cache-size = <0x100000>; // L2, 1M
207 interrupt-parent = <&mpic>;
208 interrupts = <16 2>;
209 };
211 i2c@3000 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 cell-index = <0>;
215 compatible = "fsl-i2c";
216 reg = <0x3000 0x100>;
217 interrupts = <43 2>;
218 interrupt-parent = <&mpic>;
219 dfsrr;
220 };
222 i2c@3100 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 cell-index = <1>;
226 compatible = "fsl-i2c";
227 reg = <0x3100 0x100>;
228 interrupts = <43 2>;
229 interrupt-parent = <&mpic>;
230 dfsrr;
231 };
233 dma@c300 {
234 #address-cells = <1>;
235 #size-cells = <1>;
236 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
237 reg = <0xc300 0x4>;
238 ranges = <0x0 0xc100 0x200>;
239 cell-index = <1>;
240 dma-channel@0 {
241 compatible = "fsl,mpc8572-dma-channel",
242 "fsl,eloplus-dma-channel";
243 reg = <0x0 0x80>;
244 cell-index = <0>;
245 interrupt-parent = <&mpic>;
246 interrupts = <76 2>;
247 };
248 dma-channel@80 {
249 compatible = "fsl,mpc8572-dma-channel",
250 "fsl,eloplus-dma-channel";
251 reg = <0x80 0x80>;
252 cell-index = <1>;
253 interrupt-parent = <&mpic>;
254 interrupts = <77 2>;
255 };
256 dma-channel@100 {
257 compatible = "fsl,mpc8572-dma-channel",
258 "fsl,eloplus-dma-channel";
259 reg = <0x100 0x80>;
260 cell-index = <2>;
261 interrupt-parent = <&mpic>;
262 interrupts = <78 2>;
263 };
264 dma-channel@180 {
265 compatible = "fsl,mpc8572-dma-channel",
266 "fsl,eloplus-dma-channel";
267 reg = <0x180 0x80>;
268 cell-index = <3>;
269 interrupt-parent = <&mpic>;
270 interrupts = <79 2>;
271 };
272 };
274 dma@21300 {
275 #address-cells = <1>;
276 #size-cells = <1>;
277 compatible = "fsl,mpc8572-dma", "fsl,eloplus-dma";
278 reg = <0x21300 0x4>;
279 ranges = <0x0 0x21100 0x200>;
280 cell-index = <0>;
281 dma-channel@0 {
282 compatible = "fsl,mpc8572-dma-channel",
283 "fsl,eloplus-dma-channel";
284 reg = <0x0 0x80>;
285 cell-index = <0>;
286 interrupt-parent = <&mpic>;
287 interrupts = <20 2>;
288 };
289 dma-channel@80 {
290 compatible = "fsl,mpc8572-dma-channel",
291 "fsl,eloplus-dma-channel";
292 reg = <0x80 0x80>;
293 cell-index = <1>;
294 interrupt-parent = <&mpic>;
295 interrupts = <21 2>;
296 };
297 dma-channel@100 {
298 compatible = "fsl,mpc8572-dma-channel",
299 "fsl,eloplus-dma-channel";
300 reg = <0x100 0x80>;
301 cell-index = <2>;
302 interrupt-parent = <&mpic>;
303 interrupts = <22 2>;
304 };
305 dma-channel@180 {
306 compatible = "fsl,mpc8572-dma-channel",
307 "fsl,eloplus-dma-channel";
308 reg = <0x180 0x80>;
309 cell-index = <3>;
310 interrupt-parent = <&mpic>;
311 interrupts = <23 2>;
312 };
313 };
315 enet0: ethernet@24000 {
316 #address-cells = <1>;
317 #size-cells = <1>;
318 cell-index = <0>;
319 device_type = "network";
320 model = "eTSEC";
321 compatible = "gianfar";
322 reg = <0x24000 0x1000>;
323 ranges = <0x0 0x24000 0x1000>;
324 local-mac-address = [ 00 00 00 00 00 00 ];
325 interrupts = <29 2 30 2 34 2>;
326 interrupt-parent = <&mpic>;
327 tbi-handle = <&tbi0>;
328 phy-handle = <&phy0>;
329 phy-connection-type = "rgmii-id";
331 mdio@520 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 compatible = "fsl,gianfar-mdio";
335 reg = <0x520 0x20>;
337 phy0: ethernet-phy@0 {
338 interrupt-parent = <&mpic>;
339 interrupts = <10 1>;
340 reg = <0x0>;
341 };
342 phy1: ethernet-phy@1 {
343 interrupt-parent = <&mpic>;
344 interrupts = <10 1>;
345 reg = <0x1>;
346 };
347 phy2: ethernet-phy@2 {
348 interrupt-parent = <&mpic>;
349 interrupts = <10 1>;
350 reg = <0x2>;
351 };
352 phy3: ethernet-phy@3 {
353 interrupt-parent = <&mpic>;
354 interrupts = <10 1>;
355 reg = <0x3>;
356 };
358 tbi0: tbi-phy@11 {
359 reg = <0x11>;
360 device_type = "tbi-phy";
361 };
362 };
363 };
365 enet1: ethernet@25000 {
366 #address-cells = <1>;
367 #size-cells = <1>;
368 cell-index = <1>;
369 device_type = "network";
370 model = "eTSEC";
371 compatible = "gianfar";
372 reg = <0x25000 0x1000>;
373 ranges = <0x0 0x25000 0x1000>;
374 local-mac-address = [ 00 00 00 00 00 00 ];
375 interrupts = <35 2 36 2 40 2>;
376 interrupt-parent = <&mpic>;
377 tbi-handle = <&tbi1>;
378 phy-handle = <&phy1>;
379 phy-connection-type = "rgmii-id";
381 mdio@520 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 compatible = "fsl,gianfar-tbi";
385 reg = <0x520 0x20>;
387 tbi1: tbi-phy@11 {
388 reg = <0x11>;
389 device_type = "tbi-phy";
390 };
391 };
392 };
394 enet2: ethernet@26000 {
395 #address-cells = <1>;
396 #size-cells = <1>;
397 cell-index = <2>;
398 device_type = "network";
399 model = "eTSEC";
400 compatible = "gianfar";
401 reg = <0x26000 0x1000>;
402 ranges = <0x0 0x26000 0x1000>;
403 local-mac-address = [ 00 00 00 00 00 00 ];
404 interrupts = <31 2 32 2 33 2>;
405 interrupt-parent = <&mpic>;
406 tbi-handle = <&tbi2>;
407 phy-handle = <&phy2>;
408 phy-connection-type = "rgmii-id";
410 mdio@520 {
411 #address-cells = <1>;
412 #size-cells = <0>;
413 compatible = "fsl,gianfar-tbi";
414 reg = <0x520 0x20>;
416 tbi2: tbi-phy@11 {
417 reg = <0x11>;
418 device_type = "tbi-phy";
419 };
420 };
421 };
423 enet3: ethernet@27000 {
424 #address-cells = <1>;
425 #size-cells = <1>;
426 cell-index = <3>;
427 device_type = "network";
428 model = "eTSEC";
429 compatible = "gianfar";
430 reg = <0x27000 0x1000>;
431 ranges = <0x0 0x27000 0x1000>;
432 local-mac-address = [ 00 00 00 00 00 00 ];
433 interrupts = <37 2 38 2 39 2>;
434 interrupt-parent = <&mpic>;
435 tbi-handle = <&tbi3>;
436 phy-handle = <&phy3>;
437 phy-connection-type = "rgmii-id";
439 mdio@520 {
440 #address-cells = <1>;
441 #size-cells = <0>;
442 compatible = "fsl,gianfar-tbi";
443 reg = <0x520 0x20>;
445 tbi3: tbi-phy@11 {
446 reg = <0x11>;
447 device_type = "tbi-phy";
448 };
449 };
450 };
452 serial0: serial@4500 {
453 cell-index = <0>;
454 device_type = "serial";
455 compatible = "ns16550";
456 reg = <0x4500 0x100>;
457 clock-frequency = <0>;
458 interrupts = <42 2>;
459 interrupt-parent = <&mpic>;
460 };
462 serial1: serial@4600 {
463 cell-index = <1>;
464 device_type = "serial";
465 compatible = "ns16550";
466 reg = <0x4600 0x100>;
467 clock-frequency = <0>;
468 interrupts = <42 2>;
469 interrupt-parent = <&mpic>;
470 };
472 global-utilities@e0000 { //global utilities block
473 compatible = "fsl,mpc8572-guts";
474 reg = <0xe0000 0x1000>;
475 fsl,has-rstcr;
476 };
478 msi@41600 {
479 compatible = "fsl,mpc8572-msi", "fsl,mpic-msi";
480 reg = <0x41600 0x80>;
481 msi-available-ranges = <0 0x100>;
482 interrupts = <
483 0xe0 0
484 0xe1 0
485 0xe2 0
486 0xe3 0
487 0xe4 0
488 0xe5 0
489 0xe6 0
490 0xe7 0>;
491 interrupt-parent = <&mpic>;
492 };
494 crypto@30000 {
495 compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
496 "fsl,sec2.1", "fsl,sec2.0";
497 reg = <0x30000 0x10000>;
498 interrupts = <45 2 58 2>;
499 interrupt-parent = <&mpic>;
500 fsl,num-channels = <4>;
501 fsl,channel-fifo-len = <24>;
502 fsl,exec-units-mask = <0x9fe>;
503 fsl,descriptor-types-mask = <0x3ab0ebf>;
504 };
506 mpic: pic@40000 {
507 interrupt-controller;
508 #address-cells = <0>;
509 #interrupt-cells = <2>;
510 reg = <0x40000 0x40000>;
511 compatible = "chrp,open-pic";
512 device_type = "open-pic";
513 };
514 };
516 pci0: pcie@fffe08000 {
517 cell-index = <0>;
518 compatible = "fsl,mpc8548-pcie";
519 device_type = "pci";
520 #interrupt-cells = <1>;
521 #size-cells = <2>;
522 #address-cells = <3>;
523 reg = <0xf 0xffe08000 0 0x1000>;
524 bus-range = <0 255>;
525 ranges = <0x2000000 0x0 0xc0000000 0xc 0x00000000 0x0 0x20000000
526 0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000>;
527 clock-frequency = <33333333>;
528 interrupt-parent = <&mpic>;
529 interrupts = <24 2>;
530 interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
531 interrupt-map = <
532 /* IDSEL 0x11 func 0 - PCI slot 1 */
533 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
534 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
535 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
536 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
538 /* IDSEL 0x11 func 1 - PCI slot 1 */
539 0x8900 0x0 0x0 0x1 &mpic 0x2 0x1
540 0x8900 0x0 0x0 0x2 &mpic 0x3 0x1
541 0x8900 0x0 0x0 0x3 &mpic 0x4 0x1
542 0x8900 0x0 0x0 0x4 &mpic 0x1 0x1
544 /* IDSEL 0x11 func 2 - PCI slot 1 */
545 0x8a00 0x0 0x0 0x1 &mpic 0x2 0x1
546 0x8a00 0x0 0x0 0x2 &mpic 0x3 0x1
547 0x8a00 0x0 0x0 0x3 &mpic 0x4 0x1
548 0x8a00 0x0 0x0 0x4 &mpic 0x1 0x1
550 /* IDSEL 0x11 func 3 - PCI slot 1 */
551 0x8b00 0x0 0x0 0x1 &mpic 0x2 0x1
552 0x8b00 0x0 0x0 0x2 &mpic 0x3 0x1
553 0x8b00 0x0 0x0 0x3 &mpic 0x4 0x1
554 0x8b00 0x0 0x0 0x4 &mpic 0x1 0x1
556 /* IDSEL 0x11 func 4 - PCI slot 1 */
557 0x8c00 0x0 0x0 0x1 &mpic 0x2 0x1
558 0x8c00 0x0 0x0 0x2 &mpic 0x3 0x1
559 0x8c00 0x0 0x0 0x3 &mpic 0x4 0x1
560 0x8c00 0x0 0x0 0x4 &mpic 0x1 0x1
562 /* IDSEL 0x11 func 5 - PCI slot 1 */
563 0x8d00 0x0 0x0 0x1 &mpic 0x2 0x1
564 0x8d00 0x0 0x0 0x2 &mpic 0x3 0x1
565 0x8d00 0x0 0x0 0x3 &mpic 0x4 0x1
566 0x8d00 0x0 0x0 0x4 &mpic 0x1 0x1
568 /* IDSEL 0x11 func 6 - PCI slot 1 */
569 0x8e00 0x0 0x0 0x1 &mpic 0x2 0x1
570 0x8e00 0x0 0x0 0x2 &mpic 0x3 0x1
571 0x8e00 0x0 0x0 0x3 &mpic 0x4 0x1
572 0x8e00 0x0 0x0 0x4 &mpic 0x1 0x1
574 /* IDSEL 0x11 func 7 - PCI slot 1 */
575 0x8f00 0x0 0x0 0x1 &mpic 0x2 0x1
576 0x8f00 0x0 0x0 0x2 &mpic 0x3 0x1
577 0x8f00 0x0 0x0 0x3 &mpic 0x4 0x1
578 0x8f00 0x0 0x0 0x4 &mpic 0x1 0x1
580 /* IDSEL 0x12 func 0 - PCI slot 2 */
581 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
582 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
583 0x9000 0x0 0x0 0x3 &mpic 0x1 0x1
584 0x9000 0x0 0x0 0x4 &mpic 0x2 0x1
586 /* IDSEL 0x12 func 1 - PCI slot 2 */
587 0x9100 0x0 0x0 0x1 &mpic 0x3 0x1
588 0x9100 0x0 0x0 0x2 &mpic 0x4 0x1
589 0x9100 0x0 0x0 0x3 &mpic 0x1 0x1
590 0x9100 0x0 0x0 0x4 &mpic 0x2 0x1
592 /* IDSEL 0x12 func 2 - PCI slot 2 */
593 0x9200 0x0 0x0 0x1 &mpic 0x3 0x1
594 0x9200 0x0 0x0 0x2 &mpic 0x4 0x1
595 0x9200 0x0 0x0 0x3 &mpic 0x1 0x1
596 0x9200 0x0 0x0 0x4 &mpic 0x2 0x1
598 /* IDSEL 0x12 func 3 - PCI slot 2 */
599 0x9300 0x0 0x0 0x1 &mpic 0x3 0x1
600 0x9300 0x0 0x0 0x2 &mpic 0x4 0x1
601 0x9300 0x0 0x0 0x3 &mpic 0x1 0x1
602 0x9300 0x0 0x0 0x4 &mpic 0x2 0x1
604 /* IDSEL 0x12 func 4 - PCI slot 2 */
605 0x9400 0x0 0x0 0x1 &mpic 0x3 0x1
606 0x9400 0x0 0x0 0x2 &mpic 0x4 0x1
607 0x9400 0x0 0x0 0x3 &mpic 0x1 0x1
608 0x9400 0x0 0x0 0x4 &mpic 0x2 0x1
610 /* IDSEL 0x12 func 5 - PCI slot 2 */
611 0x9500 0x0 0x0 0x1 &mpic 0x3 0x1
612 0x9500 0x0 0x0 0x2 &mpic 0x4 0x1
613 0x9500 0x0 0x0 0x3 &mpic 0x1 0x1
614 0x9500 0x0 0x0 0x4 &mpic 0x2 0x1
616 /* IDSEL 0x12 func 6 - PCI slot 2 */
617 0x9600 0x0 0x0 0x1 &mpic 0x3 0x1
618 0x9600 0x0 0x0 0x2 &mpic 0x4 0x1
619 0x9600 0x0 0x0 0x3 &mpic 0x1 0x1
620 0x9600 0x0 0x0 0x4 &mpic 0x2 0x1
622 /* IDSEL 0x12 func 7 - PCI slot 2 */
623 0x9700 0x0 0x0 0x1 &mpic 0x3 0x1
624 0x9700 0x0 0x0 0x2 &mpic 0x4 0x1
625 0x9700 0x0 0x0 0x3 &mpic 0x1 0x1
626 0x9700 0x0 0x0 0x4 &mpic 0x2 0x1
628 // IDSEL 0x1c USB
629 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
630 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
631 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
632 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
634 // IDSEL 0x1d Audio
635 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
637 // IDSEL 0x1e Legacy
638 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
639 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
641 // IDSEL 0x1f IDE/SATA
642 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
643 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
645 >;
647 pcie@0 {
648 reg = <0x0 0x0 0x0 0x0 0x0>;
649 #size-cells = <2>;
650 #address-cells = <3>;
651 device_type = "pci";
652 ranges = <0x2000000 0x0 0xc0000000
653 0x2000000 0x0 0xc0000000
654 0x0 0x20000000
656 0x1000000 0x0 0x0
657 0x1000000 0x0 0x0
658 0x0 0x10000>;
659 uli1575@0 {
660 reg = <0x0 0x0 0x0 0x0 0x0>;
661 #size-cells = <2>;
662 #address-cells = <3>;
663 ranges = <0x2000000 0x0 0xc0000000
664 0x2000000 0x0 0xc0000000
665 0x0 0x20000000
667 0x1000000 0x0 0x0
668 0x1000000 0x0 0x0
669 0x0 0x10000>;
670 isa@1e {
671 device_type = "isa";
672 #interrupt-cells = <2>;
673 #size-cells = <1>;
674 #address-cells = <2>;
675 reg = <0xf000 0x0 0x0 0x0 0x0>;
676 ranges = <0x1 0x0 0x1000000 0x0 0x0
677 0x1000>;
678 interrupt-parent = <&i8259>;
680 i8259: interrupt-controller@20 {
681 reg = <0x1 0x20 0x2
682 0x1 0xa0 0x2
683 0x1 0x4d0 0x2>;
684 interrupt-controller;
685 device_type = "interrupt-controller";
686 #address-cells = <0>;
687 #interrupt-cells = <2>;
688 compatible = "chrp,iic";
689 interrupts = <9 2>;
690 interrupt-parent = <&mpic>;
691 };
693 i8042@60 {
694 #size-cells = <0>;
695 #address-cells = <1>;
696 reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
697 interrupts = <1 3 12 3>;
698 interrupt-parent =
699 <&i8259>;
701 keyboard@0 {
702 reg = <0x0>;
703 compatible = "pnpPNP,303";
704 };
706 mouse@1 {
707 reg = <0x1>;
708 compatible = "pnpPNP,f03";
709 };
710 };
712 rtc@70 {
713 compatible = "pnpPNP,b00";
714 reg = <0x1 0x70 0x2>;
715 };
717 gpio@400 {
718 reg = <0x1 0x400 0x80>;
719 };
720 };
721 };
722 };
724 };
726 pci1: pcie@fffe09000 {
727 cell-index = <1>;
728 compatible = "fsl,mpc8548-pcie";
729 device_type = "pci";
730 #interrupt-cells = <1>;
731 #size-cells = <2>;
732 #address-cells = <3>;
733 reg = <0xf 0xffe09000 0 0x1000>;
734 bus-range = <0 255>;
735 ranges = <0x2000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000
736 0x1000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000>;
737 clock-frequency = <33333333>;
738 interrupt-parent = <&mpic>;
739 interrupts = <25 2>;
740 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
741 interrupt-map = <
742 /* IDSEL 0x0 */
743 0000 0x0 0x0 0x1 &mpic 0x4 0x1
744 0000 0x0 0x0 0x2 &mpic 0x5 0x1
745 0000 0x0 0x0 0x3 &mpic 0x6 0x1
746 0000 0x0 0x0 0x4 &mpic 0x7 0x1
747 >;
748 pcie@0 {
749 reg = <0x0 0x0 0x0 0x0 0x0>;
750 #size-cells = <2>;
751 #address-cells = <3>;
752 device_type = "pci";
753 ranges = <0x2000000 0x0 0xc0000000
754 0x2000000 0x0 0xc0000000
755 0x0 0x20000000
757 0x1000000 0x0 0x0
758 0x1000000 0x0 0x0
759 0x0 0x10000>;
760 };
761 };
763 pci2: pcie@fffe0a000 {
764 cell-index = <2>;
765 compatible = "fsl,mpc8548-pcie";
766 device_type = "pci";
767 #interrupt-cells = <1>;
768 #size-cells = <2>;
769 #address-cells = <3>;
770 reg = <0xf 0xffe0a000 0 0x1000>;
771 bus-range = <0 255>;
772 ranges = <0x2000000 0x0 0xc0000000 0xc 0x40000000 0x0 0x20000000
773 0x1000000 0x0 0x00000000 0xf 0xffc20000 0x0 0x00010000>;
774 clock-frequency = <33333333>;
775 interrupt-parent = <&mpic>;
776 interrupts = <26 2>;
777 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
778 interrupt-map = <
779 /* IDSEL 0x0 */
780 0000 0x0 0x0 0x1 &mpic 0x0 0x1
781 0000 0x0 0x0 0x2 &mpic 0x1 0x1
782 0000 0x0 0x0 0x3 &mpic 0x2 0x1
783 0000 0x0 0x0 0x4 &mpic 0x3 0x1
784 >;
785 pcie@0 {
786 reg = <0x0 0x0 0x0 0x0 0x0>;
787 #size-cells = <2>;
788 #address-cells = <3>;
789 device_type = "pci";
790 ranges = <0x2000000 0x0 0xc0000000
791 0x2000000 0x0 0xc0000000
792 0x0 0x20000000
794 0x1000000 0x0 0x0
795 0x1000000 0x0 0x0
796 0x0 0x10000>;
797 };
798 };
799 };