| blob | c4564b81e47305e478aa6b6591118cd4712616f9 |
1 /*
2 * SBC8560 Device Tree Source
3 *
4 * Copyright 2007 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
14 /dts-v1/;
16 / {
17 model = "SBC8560";
18 compatible = "SBC8560";
19 #address-cells = <1>;
20 #size-cells = <1>;
22 aliases {
23 ethernet0 = &enet0;
24 ethernet1 = &enet1;
25 ethernet2 = &enet2;
26 ethernet3 = &enet3;
27 serial0 = &serial0;
28 serial1 = &serial1;
29 pci0 = &pci0;
30 };
32 cpus {
33 #address-cells = <1>;
34 #size-cells = <0>;
36 PowerPC,8560@0 {
37 device_type = "cpu";
38 reg = <0>;
39 d-cache-line-size = <0x20>; // 32 bytes
40 i-cache-line-size = <0x20>; // 32 bytes
41 d-cache-size = <0x8000>; // L1, 32K
42 i-cache-size = <0x8000>; // L1, 32K
43 timebase-frequency = <0>; // From uboot
44 bus-frequency = <0>;
45 clock-frequency = <0>;
46 next-level-cache = <&L2>;
47 };
48 };
50 memory {
51 device_type = "memory";
52 reg = <0x00000000 0x20000000>;
53 };
55 soc@ff700000 {
56 #address-cells = <1>;
57 #size-cells = <1>;
58 device_type = "soc";
59 ranges = <0x0 0xff700000 0x00100000>;
60 reg = <0xff700000 0x00100000>;
61 clock-frequency = <0>;
63 memory-controller@2000 {
64 compatible = "fsl,mpc8560-memory-controller";
65 reg = <0x2000 0x1000>;
66 interrupt-parent = <&mpic>;
67 interrupts = <0x12 0x2>;
68 };
70 L2: l2-cache-controller@20000 {
71 compatible = "fsl,mpc8560-l2-cache-controller";
72 reg = <0x20000 0x1000>;
73 cache-line-size = <0x20>; // 32 bytes
74 cache-size = <0x40000>; // L2, 256K
75 interrupt-parent = <&mpic>;
76 interrupts = <0x10 0x2>;
77 };
79 i2c@3000 {
80 #address-cells = <1>;
81 #size-cells = <0>;
82 cell-index = <0>;
83 compatible = "fsl-i2c";
84 reg = <0x3000 0x100>;
85 interrupts = <0x2b 0x2>;
86 interrupt-parent = <&mpic>;
87 dfsrr;
88 };
90 i2c@3100 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 cell-index = <1>;
94 compatible = "fsl-i2c";
95 reg = <0x3100 0x100>;
96 interrupts = <0x2b 0x2>;
97 interrupt-parent = <&mpic>;
98 dfsrr;
99 };
101 dma@21300 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
105 reg = <0x21300 0x4>;
106 ranges = <0x0 0x21100 0x200>;
107 cell-index = <0>;
108 dma-channel@0 {
109 compatible = "fsl,mpc8560-dma-channel",
110 "fsl,eloplus-dma-channel";
111 reg = <0x0 0x80>;
112 cell-index = <0>;
113 interrupt-parent = <&mpic>;
114 interrupts = <20 2>;
115 };
116 dma-channel@80 {
117 compatible = "fsl,mpc8560-dma-channel",
118 "fsl,eloplus-dma-channel";
119 reg = <0x80 0x80>;
120 cell-index = <1>;
121 interrupt-parent = <&mpic>;
122 interrupts = <21 2>;
123 };
124 dma-channel@100 {
125 compatible = "fsl,mpc8560-dma-channel",
126 "fsl,eloplus-dma-channel";
127 reg = <0x100 0x80>;
128 cell-index = <2>;
129 interrupt-parent = <&mpic>;
130 interrupts = <22 2>;
131 };
132 dma-channel@180 {
133 compatible = "fsl,mpc8560-dma-channel",
134 "fsl,eloplus-dma-channel";
135 reg = <0x180 0x80>;
136 cell-index = <3>;
137 interrupt-parent = <&mpic>;
138 interrupts = <23 2>;
139 };
140 };
142 enet0: ethernet@24000 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 cell-index = <0>;
146 device_type = "network";
147 model = "TSEC";
148 compatible = "gianfar";
149 reg = <0x24000 0x1000>;
150 ranges = <0x0 0x24000 0x1000>;
151 local-mac-address = [ 00 00 00 00 00 00 ];
152 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
153 interrupt-parent = <&mpic>;
154 tbi-handle = <&tbi0>;
155 phy-handle = <&phy0>;
157 mdio@520 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 compatible = "fsl,gianfar-mdio";
161 reg = <0x520 0x20>;
162 phy0: ethernet-phy@19 {
163 interrupt-parent = <&mpic>;
164 interrupts = <0x6 0x1>;
165 reg = <0x19>;
166 device_type = "ethernet-phy";
167 };
168 phy1: ethernet-phy@1a {
169 interrupt-parent = <&mpic>;
170 interrupts = <0x7 0x1>;
171 reg = <0x1a>;
172 device_type = "ethernet-phy";
173 };
174 phy2: ethernet-phy@1b {
175 interrupt-parent = <&mpic>;
176 interrupts = <0x8 0x1>;
177 reg = <0x1b>;
178 device_type = "ethernet-phy";
179 };
180 phy3: ethernet-phy@1c {
181 interrupt-parent = <&mpic>;
182 interrupts = <0x8 0x1>;
183 reg = <0x1c>;
184 device_type = "ethernet-phy";
185 };
186 tbi0: tbi-phy@11 {
187 reg = <0x11>;
188 device_type = "tbi-phy";
189 };
190 };
191 };
193 enet1: ethernet@25000 {
194 #address-cells = <1>;
195 #size-cells = <1>;
196 cell-index = <1>;
197 device_type = "network";
198 model = "TSEC";
199 compatible = "gianfar";
200 reg = <0x25000 0x1000>;
201 ranges = <0x0 0x25000 0x1000>;
202 local-mac-address = [ 00 00 00 00 00 00 ];
203 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
204 interrupt-parent = <&mpic>;
205 tbi-handle = <&tbi1>;
206 phy-handle = <&phy1>;
208 mdio@520 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "fsl,gianfar-tbi";
212 reg = <0x520 0x20>;
214 tbi1: tbi-phy@11 {
215 reg = <0x11>;
216 device_type = "tbi-phy";
217 };
218 };
219 };
221 mpic: pic@40000 {
222 interrupt-controller;
223 #address-cells = <0>;
224 #interrupt-cells = <2>;
225 compatible = "chrp,open-pic";
226 reg = <0x40000 0x40000>;
227 device_type = "open-pic";
228 };
230 cpm@919c0 {
231 #address-cells = <1>;
232 #size-cells = <1>;
233 compatible = "fsl,mpc8560-cpm", "fsl,cpm2";
234 reg = <0x919c0 0x30>;
235 ranges;
237 muram@80000 {
238 #address-cells = <1>;
239 #size-cells = <1>;
240 ranges = <0x0 0x80000 0x10000>;
242 data@0 {
243 compatible = "fsl,cpm-muram-data";
244 reg = <0x0 0x4000 0x9000 0x2000>;
245 };
246 };
248 brg@919f0 {
249 compatible = "fsl,mpc8560-brg",
250 "fsl,cpm2-brg",
251 "fsl,cpm-brg";
252 reg = <0x919f0 0x10 0x915f0 0x10>;
253 clock-frequency = <165000000>;
254 };
256 cpmpic: pic@90c00 {
257 interrupt-controller;
258 #address-cells = <0>;
259 #interrupt-cells = <2>;
260 interrupts = <0x2e 0x2>;
261 interrupt-parent = <&mpic>;
262 reg = <0x90c00 0x80>;
263 compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
264 };
266 enet2: ethernet@91320 {
267 device_type = "network";
268 compatible = "fsl,mpc8560-fcc-enet",
269 "fsl,cpm2-fcc-enet";
270 reg = <0x91320 0x20 0x88500 0x100 0x913b0 0x1>;
271 local-mac-address = [ 00 00 00 00 00 00 ];
272 fsl,cpm-command = <0x16200300>;
273 interrupts = <0x21 0x8>;
274 interrupt-parent = <&cpmpic>;
275 phy-handle = <&phy2>;
276 };
278 enet3: ethernet@91340 {
279 device_type = "network";
280 compatible = "fsl,mpc8560-fcc-enet",
281 "fsl,cpm2-fcc-enet";
282 reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
283 local-mac-address = [ 00 00 00 00 00 00 ];
284 fsl,cpm-command = <0x1a400300>;
285 interrupts = <0x22 0x8>;
286 interrupt-parent = <&cpmpic>;
287 phy-handle = <&phy3>;
288 };
289 };
291 global-utilities@e0000 {
292 compatible = "fsl,mpc8560-guts";
293 reg = <0xe0000 0x1000>;
294 fsl,has-rstcr;
295 };
296 };
298 pci0: pci@ff708000 {
299 cell-index = <0>;
300 #interrupt-cells = <1>;
301 #size-cells = <2>;
302 #address-cells = <3>;
303 compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
304 device_type = "pci";
305 reg = <0xff708000 0x1000>;
306 clock-frequency = <66666666>;
307 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
308 interrupt-map = <
310 /* IDSEL 0x02 */
311 0x1000 0x0 0x0 0x1 &mpic 0x2 0x1
312 0x1000 0x0 0x0 0x2 &mpic 0x3 0x1
313 0x1000 0x0 0x0 0x3 &mpic 0x4 0x1
314 0x1000 0x0 0x0 0x4 &mpic 0x5 0x1>;
316 interrupt-parent = <&mpic>;
317 interrupts = <0x18 0x2>;
318 bus-range = <0x0 0x0>;
319 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
320 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
321 };
323 localbus@ff705000 {
324 compatible = "fsl,mpc8560-localbus";
325 #address-cells = <2>;
326 #size-cells = <1>;
327 reg = <0xff705000 0x100>; // BRx, ORx, etc.
329 ranges = <
330 0x0 0x0 0xff800000 0x0800000 // 8MB boot flash
331 0x1 0x0 0xe4000000 0x4000000 // 64MB flash
332 0x3 0x0 0x20000000 0x4000000 // 64MB SDRAM
333 0x4 0x0 0x24000000 0x4000000 // 64MB SDRAM
334 0x5 0x0 0xfc000000 0x0c00000 // EPLD
335 0x6 0x0 0xe0000000 0x4000000 // 64MB flash
336 0x7 0x0 0x80000000 0x0200000 // ATM1,2
337 >;
339 epld@5,0 {
340 compatible = "wrs,epld-localbus";
341 #address-cells = <2>;
342 #size-cells = <1>;
343 reg = <0x5 0x0 0xc00000>;
344 ranges = <
345 0x0 0x0 0x5 0x000000 0x1fff // LED disp.
346 0x1 0x0 0x5 0x100000 0x1fff // switches
347 0x2 0x0 0x5 0x200000 0x1fff // ID reg.
348 0x3 0x0 0x5 0x300000 0x1fff // status reg.
349 0x4 0x0 0x5 0x400000 0x1fff // reset reg.
350 0x5 0x0 0x5 0x500000 0x1fff // Wind port
351 0x7 0x0 0x5 0x700000 0x1fff // UART #1
352 0x8 0x0 0x5 0x800000 0x1fff // UART #2
353 0x9 0x0 0x5 0x900000 0x1fff // RTC
354 0xb 0x0 0x5 0xb00000 0x1fff // EEPROM
355 >;
357 bidr@2,0 {
358 compatible = "wrs,sbc8560-bidr";
359 reg = <0x2 0x0 0x10>;
360 };
362 bcsr@3,0 {
363 compatible = "wrs,sbc8560-bcsr";
364 reg = <0x3 0x0 0x10>;
365 };
367 brstcr@4,0 {
368 compatible = "wrs,sbc8560-brstcr";
369 reg = <0x4 0x0 0x10>;
370 };
372 serial0: serial@7,0 {
373 device_type = "serial";
374 compatible = "ns16550";
375 reg = <0x7 0x0 0x100>;
376 clock-frequency = <1843200>;
377 interrupts = <0x9 0x2>;
378 interrupt-parent = <&mpic>;
379 };
381 serial1: serial@8,0 {
382 device_type = "serial";
383 compatible = "ns16550";
384 reg = <0x8 0x0 0x100>;
385 clock-frequency = <1843200>;
386 interrupts = <0xa 0x2>;
387 interrupt-parent = <&mpic>;
388 };
390 rtc@9,0 {
391 compatible = "m48t59";
392 reg = <0x9 0x0 0x1fff>;
393 };
394 };
395 };
396 };