| blob | e3e914e78caa2e6fdec7f5181e6a2e0a39d97a72 |
1 /*
2 * SBC8641D Device Tree Source
3 *
4 * Copyright 2008 Wind River Systems Inc.
5 *
6 * Paul Gortmaker (see MAINTAINERS for contact information)
7 *
8 * Based largely on the mpc8641_hpcn.dts by Freescale Semiconductor Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
16 /dts-v1/;
18 / {
19 model = "SBC8641D";
20 compatible = "wind,sbc8641";
21 #address-cells = <1>;
22 #size-cells = <1>;
24 aliases {
25 ethernet0 = &enet0;
26 ethernet1 = &enet1;
27 ethernet2 = &enet2;
28 ethernet3 = &enet3;
29 serial0 = &serial0;
30 serial1 = &serial1;
31 pci0 = &pci0;
32 pci1 = &pci1;
33 };
35 cpus {
36 #address-cells = <1>;
37 #size-cells = <0>;
39 PowerPC,8641@0 {
40 device_type = "cpu";
41 reg = <0>;
42 d-cache-line-size = <32>;
43 i-cache-line-size = <32>;
44 d-cache-size = <32768>; // L1
45 i-cache-size = <32768>; // L1
46 timebase-frequency = <0>; // From uboot
47 bus-frequency = <0>; // From uboot
48 clock-frequency = <0>; // From uboot
49 };
50 PowerPC,8641@1 {
51 device_type = "cpu";
52 reg = <1>;
53 d-cache-line-size = <32>;
54 i-cache-line-size = <32>;
55 d-cache-size = <32768>;
56 i-cache-size = <32768>;
57 timebase-frequency = <0>; // From uboot
58 bus-frequency = <0>; // From uboot
59 clock-frequency = <0>; // From uboot
60 };
61 };
63 memory {
64 device_type = "memory";
65 reg = <0x00000000 0x20000000>; // 512M at 0x0
66 };
68 localbus@f8005000 {
69 #address-cells = <2>;
70 #size-cells = <1>;
71 compatible = "fsl,mpc8641-localbus", "simple-bus";
72 reg = <0xf8005000 0x1000>;
73 interrupts = <19 2>;
74 interrupt-parent = <&mpic>;
76 ranges = <0 0 0xff000000 0x01000000 // 16MB Boot flash
77 1 0 0xf0000000 0x00010000 // 64KB EEPROM
78 2 0 0xf1000000 0x00100000 // EPLD (1MB)
79 3 0 0xe0000000 0x04000000 // 64MB LB SDRAM (CS3)
80 4 0 0xe4000000 0x04000000 // 64MB LB SDRAM (CS4)
81 6 0 0xf4000000 0x00100000 // LCD display (1MB)
82 7 0 0xe8000000 0x04000000>; // 64MB OneNAND
84 flash@0,0 {
85 compatible = "cfi-flash";
86 reg = <0 0 0x01000000>;
87 bank-width = <2>;
88 device-width = <2>;
89 #address-cells = <1>;
90 #size-cells = <1>;
91 partition@0 {
92 label = "dtb";
93 reg = <0x00000000 0x00100000>;
94 read-only;
95 };
96 partition@300000 {
97 label = "kernel";
98 reg = <0x00100000 0x00400000>;
99 read-only;
100 };
101 partition@400000 {
102 label = "fs";
103 reg = <0x00500000 0x00a00000>;
104 };
105 partition@700000 {
106 label = "firmware";
107 reg = <0x00f00000 0x00100000>;
108 read-only;
109 };
110 };
112 epld@2,0 {
113 compatible = "wrs,epld-localbus";
114 #address-cells = <2>;
115 #size-cells = <1>;
116 reg = <2 0 0x100000>;
117 ranges = <0 0 5 0 1 // User switches
118 1 0 5 1 1 // Board ID/Rev
119 3 0 5 3 1>; // LEDs
120 };
121 };
123 soc@f8000000 {
124 #address-cells = <1>;
125 #size-cells = <1>;
126 device_type = "soc";
127 compatible = "simple-bus";
128 ranges = <0x00000000 0xf8000000 0x00100000>;
129 reg = <0xf8000000 0x00001000>; // CCSRBAR
130 bus-frequency = <0>;
132 i2c@3000 {
133 #address-cells = <1>;
134 #size-cells = <0>;
135 cell-index = <0>;
136 compatible = "fsl-i2c";
137 reg = <0x3000 0x100>;
138 interrupts = <43 2>;
139 interrupt-parent = <&mpic>;
140 dfsrr;
141 };
143 i2c@3100 {
144 #address-cells = <1>;
145 #size-cells = <0>;
146 cell-index = <1>;
147 compatible = "fsl-i2c";
148 reg = <0x3100 0x100>;
149 interrupts = <43 2>;
150 interrupt-parent = <&mpic>;
151 dfsrr;
152 };
154 dma@21300 {
155 #address-cells = <1>;
156 #size-cells = <1>;
157 compatible = "fsl,mpc8641-dma", "fsl,eloplus-dma";
158 reg = <0x21300 0x4>;
159 ranges = <0x0 0x21100 0x200>;
160 cell-index = <0>;
161 dma-channel@0 {
162 compatible = "fsl,mpc8641-dma-channel",
163 "fsl,eloplus-dma-channel";
164 reg = <0x0 0x80>;
165 cell-index = <0>;
166 interrupt-parent = <&mpic>;
167 interrupts = <20 2>;
168 };
169 dma-channel@80 {
170 compatible = "fsl,mpc8641-dma-channel",
171 "fsl,eloplus-dma-channel";
172 reg = <0x80 0x80>;
173 cell-index = <1>;
174 interrupt-parent = <&mpic>;
175 interrupts = <21 2>;
176 };
177 dma-channel@100 {
178 compatible = "fsl,mpc8641-dma-channel",
179 "fsl,eloplus-dma-channel";
180 reg = <0x100 0x80>;
181 cell-index = <2>;
182 interrupt-parent = <&mpic>;
183 interrupts = <22 2>;
184 };
185 dma-channel@180 {
186 compatible = "fsl,mpc8641-dma-channel",
187 "fsl,eloplus-dma-channel";
188 reg = <0x180 0x80>;
189 cell-index = <3>;
190 interrupt-parent = <&mpic>;
191 interrupts = <23 2>;
192 };
193 };
195 enet0: ethernet@24000 {
196 #address-cells = <1>;
197 #size-cells = <1>;
198 cell-index = <0>;
199 device_type = "network";
200 model = "TSEC";
201 compatible = "gianfar";
202 reg = <0x24000 0x1000>;
203 ranges = <0x0 0x24000 0x1000>;
204 local-mac-address = [ 00 00 00 00 00 00 ];
205 interrupts = <29 2 30 2 34 2>;
206 interrupt-parent = <&mpic>;
207 tbi-handle = <&tbi0>;
208 phy-handle = <&phy0>;
209 phy-connection-type = "rgmii-id";
211 mdio@520 {
212 #address-cells = <1>;
213 #size-cells = <0>;
214 compatible = "fsl,gianfar-mdio";
215 reg = <0x520 0x20>;
217 phy0: ethernet-phy@1f {
218 interrupt-parent = <&mpic>;
219 interrupts = <10 1>;
220 reg = <0x1f>;
221 device_type = "ethernet-phy";
222 };
223 phy1: ethernet-phy@0 {
224 interrupt-parent = <&mpic>;
225 interrupts = <10 1>;
226 reg = <0>;
227 device_type = "ethernet-phy";
228 };
229 phy2: ethernet-phy@1 {
230 interrupt-parent = <&mpic>;
231 interrupts = <10 1>;
232 reg = <1>;
233 device_type = "ethernet-phy";
234 };
235 phy3: ethernet-phy@2 {
236 interrupt-parent = <&mpic>;
237 interrupts = <10 1>;
238 reg = <2>;
239 device_type = "ethernet-phy";
240 };
241 tbi0: tbi-phy@11 {
242 reg = <0x11>;
243 device_type = "tbi-phy";
244 };
245 };
246 };
248 enet1: ethernet@25000 {
249 #address-cells = <1>;
250 #size-cells = <1>;
251 cell-index = <1>;
252 device_type = "network";
253 model = "TSEC";
254 compatible = "gianfar";
255 reg = <0x25000 0x1000>;
256 ranges = <0x0 0x25000 0x1000>;
257 local-mac-address = [ 00 00 00 00 00 00 ];
258 interrupts = <35 2 36 2 40 2>;
259 interrupt-parent = <&mpic>;
260 tbi-handle = <&tbi1>;
261 phy-handle = <&phy1>;
262 phy-connection-type = "rgmii-id";
264 mdio@520 {
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "fsl,gianfar-tbi";
268 reg = <0x520 0x20>;
270 tbi1: tbi-phy@11 {
271 reg = <0x11>;
272 device_type = "tbi-phy";
273 };
274 };
275 };
277 enet2: ethernet@26000 {
278 #address-cells = <1>;
279 #size-cells = <1>;
280 cell-index = <2>;
281 device_type = "network";
282 model = "TSEC";
283 compatible = "gianfar";
284 reg = <0x26000 0x1000>;
285 ranges = <0x0 0x26000 0x1000>;
286 local-mac-address = [ 00 00 00 00 00 00 ];
287 interrupts = <31 2 32 2 33 2>;
288 interrupt-parent = <&mpic>;
289 tbi-handle = <&tbi2>;
290 phy-handle = <&phy2>;
291 phy-connection-type = "rgmii-id";
293 mdio@520 {
294 #address-cells = <1>;
295 #size-cells = <0>;
296 compatible = "fsl,gianfar-tbi";
297 reg = <0x520 0x20>;
299 tbi2: tbi-phy@11 {
300 reg = <0x11>;
301 device_type = "tbi-phy";
302 };
303 };
304 };
306 enet3: ethernet@27000 {
307 #address-cells = <1>;
308 #size-cells = <1>;
309 cell-index = <3>;
310 device_type = "network";
311 model = "TSEC";
312 compatible = "gianfar";
313 reg = <0x27000 0x1000>;
314 ranges = <0x0 0x27000 0x1000>;
315 local-mac-address = [ 00 00 00 00 00 00 ];
316 interrupts = <37 2 38 2 39 2>;
317 interrupt-parent = <&mpic>;
318 tbi-handle = <&tbi3>;
319 phy-handle = <&phy3>;
320 phy-connection-type = "rgmii-id";
322 mdio@520 {
323 #address-cells = <1>;
324 #size-cells = <0>;
325 compatible = "fsl,gianfar-tbi";
326 reg = <0x520 0x20>;
328 tbi3: tbi-phy@11 {
329 reg = <0x11>;
330 device_type = "tbi-phy";
331 };
332 };
333 };
335 serial0: serial@4500 {
336 cell-index = <0>;
337 device_type = "serial";
338 compatible = "ns16550";
339 reg = <0x4500 0x100>;
340 clock-frequency = <0>;
341 interrupts = <42 2>;
342 interrupt-parent = <&mpic>;
343 };
345 serial1: serial@4600 {
346 cell-index = <1>;
347 device_type = "serial";
348 compatible = "ns16550";
349 reg = <0x4600 0x100>;
350 clock-frequency = <0>;
351 interrupts = <28 2>;
352 interrupt-parent = <&mpic>;
353 };
355 mpic: pic@40000 {
356 clock-frequency = <0>;
357 interrupt-controller;
358 #address-cells = <0>;
359 #interrupt-cells = <2>;
360 reg = <0x40000 0x40000>;
361 compatible = "chrp,open-pic";
362 device_type = "open-pic";
363 big-endian;
364 };
366 global-utilities@e0000 {
367 compatible = "fsl,mpc8641-guts";
368 reg = <0xe0000 0x1000>;
369 fsl,has-rstcr;
370 };
371 };
373 pci0: pcie@f8008000 {
374 cell-index = <0>;
375 compatible = "fsl,mpc8641-pcie";
376 device_type = "pci";
377 #interrupt-cells = <1>;
378 #size-cells = <2>;
379 #address-cells = <3>;
380 reg = <0xf8008000 0x1000>;
381 bus-range = <0x0 0xff>;
382 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
383 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
384 clock-frequency = <33333333>;
385 interrupt-parent = <&mpic>;
386 interrupts = <24 2>;
387 interrupt-map-mask = <0xff00 0 0 7>;
388 interrupt-map = <
389 /* IDSEL 0x0 */
390 0x0000 0 0 1 &mpic 0 1
391 0x0000 0 0 2 &mpic 1 1
392 0x0000 0 0 3 &mpic 2 1
393 0x0000 0 0 4 &mpic 3 1
394 >;
396 pcie@0 {
397 reg = <0 0 0 0 0>;
398 #size-cells = <2>;
399 #address-cells = <3>;
400 device_type = "pci";
401 ranges = <0x02000000 0x0 0x80000000
402 0x02000000 0x0 0x80000000
403 0x0 0x20000000
405 0x01000000 0x0 0x00000000
406 0x01000000 0x0 0x00000000
407 0x0 0x00100000>;
408 };
410 };
412 pci1: pcie@f8009000 {
413 cell-index = <1>;
414 compatible = "fsl,mpc8641-pcie";
415 device_type = "pci";
416 #interrupt-cells = <1>;
417 #size-cells = <2>;
418 #address-cells = <3>;
419 reg = <0xf8009000 0x1000>;
420 bus-range = <0 0xff>;
421 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
422 0x01000000 0x0 0x00000000 0xe3000000 0x0 0x00100000>;
423 clock-frequency = <33333333>;
424 interrupt-parent = <&mpic>;
425 interrupts = <25 2>;
426 interrupt-map-mask = <0xf800 0 0 7>;
427 interrupt-map = <
428 /* IDSEL 0x0 */
429 0x0000 0 0 1 &mpic 4 1
430 0x0000 0 0 2 &mpic 5 1
431 0x0000 0 0 3 &mpic 6 1
432 0x0000 0 0 4 &mpic 7 1
433 >;
435 pcie@0 {
436 reg = <0 0 0 0 0>;
437 #size-cells = <2>;
438 #address-cells = <3>;
439 device_type = "pci";
440 ranges = <0x02000000 0x0 0xa0000000
441 0x02000000 0x0 0xa0000000
442 0x0 0x20000000
444 0x01000000 0x0 0x00000000
445 0x01000000 0x0 0x00000000
446 0x0 0x00100000>;
447 };
448 };
449 };