2 * arch/powerpc/platforms/83xx/mpc832x_rdb.c
4 * Copyright (C) Freescale Semiconductor, Inc. 2007. All rights reserved.
7 * MPC832x RDB board specific routines.
8 * This file is based on mpc832x_mds.c and mpc8313_rdb.c
9 * Author: Michael Barkowski <michael.barkowski@freescale.com>
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
17 #include <linux/pci.h>
18 #include <linux/interrupt.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/mmc_spi.h>
21 #include <linux/mmc/host.h>
22 #include <linux/of_platform.h>
23 #include <linux/fsl_devices.h>
29 #include <asm/qe_ic.h>
30 #include <sysdev/fsl_soc.h>
31 #include <sysdev/fsl_pci.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 #ifdef CONFIG_QUICC_ENGINE
43 static int __init
of_fsl_spi_probe(char *type
, char *compatible
, u32 sysclk
,
44 struct spi_board_info
*board_infos
,
45 unsigned int num_board_infos
,
46 void (*cs_control
)(struct spi_device
*dev
,
49 struct device_node
*np
;
52 for_each_compatible_node(np
, type
, compatible
) {
56 struct resource res
[2];
57 struct platform_device
*pdev
;
58 struct fsl_spi_platform_data pdata
= {
59 .cs_control
= cs_control
,
62 memset(res
, 0, sizeof(res
));
64 pdata
.sysclk
= sysclk
;
66 prop
= of_get_property(np
, "reg", NULL
);
69 pdata
.bus_num
= *(u32
*)prop
;
71 prop
= of_get_property(np
, "cell-index", NULL
);
75 prop
= of_get_property(np
, "mode", NULL
);
76 if (prop
&& !strcmp(prop
, "cpu-qe"))
79 for (j
= 0; j
< num_board_infos
; j
++) {
80 if (board_infos
[j
].bus_num
== pdata
.bus_num
)
81 pdata
.max_chipselect
++;
84 if (!pdata
.max_chipselect
)
87 ret
= of_address_to_resource(np
, 0, &res
[0]);
91 ret
= of_irq_to_resource(np
, 0, &res
[1]);
95 pdev
= platform_device_alloc("mpc83xx_spi", i
);
99 ret
= platform_device_add_data(pdev
, &pdata
, sizeof(pdata
));
103 ret
= platform_device_add_resources(pdev
, res
,
108 ret
= platform_device_add(pdev
);
114 platform_device_del(pdev
);
116 pr_err("%s: registration failed\n", np
->full_name
);
124 static int __init
fsl_spi_init(struct spi_board_info
*board_infos
,
125 unsigned int num_board_infos
,
126 void (*cs_control
)(struct spi_device
*spi
,
132 /* SPI controller is either clocked from QE or SoC clock */
133 sysclk
= get_brgfreq();
135 sysclk
= fsl_get_sys_freq();
140 ret
= of_fsl_spi_probe(NULL
, "fsl,spi", sysclk
, board_infos
,
141 num_board_infos
, cs_control
);
143 of_fsl_spi_probe("spi", "fsl_spi", sysclk
, board_infos
,
144 num_board_infos
, cs_control
);
146 return spi_register_board_info(board_infos
, num_board_infos
);
149 static void mpc83xx_spi_cs_control(struct spi_device
*spi
, bool on
)
151 pr_debug("%s %d %d\n", __func__
, spi
->chip_select
, on
);
152 par_io_data_set(3, 13, on
);
155 static struct mmc_spi_platform_data mpc832x_mmc_pdata
= {
156 .ocr_mask
= MMC_VDD_33_34
,
159 static struct spi_board_info mpc832x_spi_boardinfo
= {
162 .max_speed_hz
= 50000000,
163 .modalias
= "mmc_spi",
164 .platform_data
= &mpc832x_mmc_pdata
,
167 static int __init
mpc832x_spi_init(void)
169 par_io_config_pin(3, 0, 3, 0, 1, 0); /* SPI1 MOSI, I/O */
170 par_io_config_pin(3, 1, 3, 0, 1, 0); /* SPI1 MISO, I/O */
171 par_io_config_pin(3, 2, 3, 0, 1, 0); /* SPI1 CLK, I/O */
172 par_io_config_pin(3, 3, 2, 0, 1, 0); /* SPI1 SEL, I */
174 par_io_config_pin(3, 13, 1, 0, 0, 0); /* !SD_CS, O */
175 par_io_config_pin(3, 14, 2, 0, 0, 0); /* SD_INSERT, I */
176 par_io_config_pin(3, 15, 2, 0, 0, 0); /* SD_PROTECT,I */
179 * Don't bother with legacy stuff when device tree contains
182 if (of_find_compatible_node(NULL
, NULL
, "mmc-spi-slot"))
184 return fsl_spi_init(&mpc832x_spi_boardinfo
, 1, mpc83xx_spi_cs_control
);
186 machine_device_initcall(mpc832x_rdb
, mpc832x_spi_init
);
187 #endif /* CONFIG_QUICC_ENGINE */
189 /* ************************************************************************
191 * Setup the architecture
194 static void __init
mpc832x_rdb_setup_arch(void)
196 #if defined(CONFIG_PCI) || defined(CONFIG_QUICC_ENGINE)
197 struct device_node
*np
;
201 ppc_md
.progress("mpc832x_rdb_setup_arch()", 0);
204 for_each_compatible_node(np
, "pci", "fsl,mpc8349-pci")
205 mpc83xx_add_bridge(np
);
208 #ifdef CONFIG_QUICC_ENGINE
211 if ((np
= of_find_node_by_name(NULL
, "par_io")) != NULL
) {
215 for (np
= NULL
; (np
= of_find_node_by_name(np
, "ucc")) != NULL
;)
216 par_io_of_config(np
);
218 #endif /* CONFIG_QUICC_ENGINE */
221 static struct of_device_id mpc832x_ids
[] = {
223 { .compatible
= "soc", },
224 { .compatible
= "simple-bus", },
226 { .compatible
= "fsl,qe", },
230 static int __init
mpc832x_declare_of_platform_devices(void)
232 /* Publish the QE devices */
233 of_platform_bus_probe(NULL
, mpc832x_ids
, NULL
);
237 machine_device_initcall(mpc832x_rdb
, mpc832x_declare_of_platform_devices
);
239 static void __init
mpc832x_rdb_init_IRQ(void)
242 struct device_node
*np
;
244 np
= of_find_node_by_type(NULL
, "ipic");
250 /* Initialize the default interrupt mapping priorities,
251 * in case the boot rom changed something on us.
253 ipic_set_default_priority();
256 #ifdef CONFIG_QUICC_ENGINE
257 np
= of_find_compatible_node(NULL
, NULL
, "fsl,qe-ic");
259 np
= of_find_node_by_type(NULL
, "qeic");
263 qe_ic_init(np
, 0, qe_ic_cascade_low_ipic
, qe_ic_cascade_high_ipic
);
265 #endif /* CONFIG_QUICC_ENGINE */
269 * Called very early, MMU is off, device-tree isn't unflattened
271 static int __init
mpc832x_rdb_probe(void)
273 unsigned long root
= of_get_flat_dt_root();
275 return of_flat_dt_is_compatible(root
, "MPC832xRDB");
278 define_machine(mpc832x_rdb
) {
279 .name
= "MPC832x RDB",
280 .probe
= mpc832x_rdb_probe
,
281 .setup_arch
= mpc832x_rdb_setup_arch
,
282 .init_IRQ
= mpc832x_rdb_init_IRQ
,
283 .get_irq
= ipic_get_irq
,
284 .restart
= mpc83xx_restart
,
285 .time_init
= mpc83xx_time_init
,
286 .calibrate_decr
= generic_calibrate_decr
,
287 .progress
= udbg_progress
,