arch/powerpc/platforms/pseries/xics.c

   1 /*
   2  * arch/powerpc/platforms/pseries/xics.c
   3  *
   4  * Copyright 2000 IBM Corporation.
   5  *
   6  *  This program is free software; you can redistribute it and/or
   7  *  modify it under the terms of the GNU General Public License
   8  *  as published by the Free Software Foundation; either version
   9  *  2 of the License, or (at your option) any later version.
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/irq.h>
  16 #include <linux/smp.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/init.h>
  19 #include <linux/radix-tree.h>
  20 #include <linux/cpu.h>
  21 #include <linux/of.h>
  22
  23 #include <asm/firmware.h>
  24 #include <asm/io.h>
  25 #include <asm/pgtable.h>
  26 #include <asm/smp.h>
  27 #include <asm/rtas.h>
  28 #include <asm/hvcall.h>
  29 #include <asm/machdep.h>
  30
  31 #include "xics.h"
  32 #include "plpar_wrappers.h"
  33
  34 static struct irq_host *xics_host;
  35
  36 #define XICS_IPI                2
  37 #define XICS_IRQ_SPURIOUS       0
  38
  39 /* Want a priority other than 0.  Various HW issues require this. */
  40 #define DEFAULT_PRIORITY        5
  41
  42 /*
  43  * Mark IPIs as higher priority so we can take them inside interrupts that
  44  * arent marked IRQF_DISABLED
  45  */
  46 #define IPI_PRIORITY            4
  47
  48 static unsigned int default_server = 0xFF;
  49 static unsigned int default_distrib_server = 0;
  50 static unsigned int interrupt_server_size = 8;
  51
  52 /* RTAS service tokens */
  53 static int ibm_get_xive;
  54 static int ibm_set_xive;
  55 static int ibm_int_on;
  56 static int ibm_int_off;
  57
  58
  59 /* Direct hardware low level accessors */
  60
  61 /* The part of the interrupt presentation layer that we care about */
  62 struct xics_ipl {
  63         union {
  64                 u32 word;
  65                 u8 bytes[4];
  66         } xirr_poll;
  67         union {
  68                 u32 word;
  69                 u8 bytes[4];
  70         } xirr;
  71         u32 dummy;
  72         union {
  73                 u32 word;
  74                 u8 bytes[4];
  75         } qirr;
  76 };
  77
  78 static struct xics_ipl __iomem *xics_per_cpu[NR_CPUS];
  79
  80 static inline unsigned int direct_xirr_info_get(void)
  81 {
  82         int cpu = smp_processor_id();
  83
  84         return in_be32(&xics_per_cpu[cpu]->xirr.word);
  85 }
  86
  87 static inline void direct_xirr_info_set(unsigned int value)
  88 {
  89         int cpu = smp_processor_id();
  90
  91         out_be32(&xics_per_cpu[cpu]->xirr.word, value);
  92 }
  93
  94 static inline void direct_cppr_info(u8 value)
  95 {
  96         int cpu = smp_processor_id();
  97
  98         out_8(&xics_per_cpu[cpu]->xirr.bytes[0], value);
  99 }
 100
 101 static inline void direct_qirr_info(int n_cpu, u8 value)
 102 {
 103         out_8(&xics_per_cpu[n_cpu]->qirr.bytes[0], value);
 104 }
 105
 106
 107 /* LPAR low level accessors */
 108
 109 static inline unsigned int lpar_xirr_info_get(void)
 110 {
 111         unsigned long lpar_rc;
 112         unsigned long return_value;
 113
 114         lpar_rc = plpar_xirr(&return_value);
 115         if (lpar_rc != H_SUCCESS)
 116                 panic(" bad return code xirr - rc = %lx \n", lpar_rc);
 117         return (unsigned int)return_value;
 118 }
 119
 120 static inline void lpar_xirr_info_set(unsigned int value)
 121 {
 122         unsigned long lpar_rc;
 123
 124         lpar_rc = plpar_eoi(value);
 125         if (lpar_rc != H_SUCCESS)
 126                 panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc,
 127                       value);
 128 }
 129
 130 static inline void lpar_cppr_info(u8 value)
 131 {
 132         unsigned long lpar_rc;
 133
 134         lpar_rc = plpar_cppr(value);
 135         if (lpar_rc != H_SUCCESS)
 136                 panic("bad return code cppr - rc = %lx\n", lpar_rc);
 137 }
 138
 139 static inline void lpar_qirr_info(int n_cpu , u8 value)
 140 {
 141         unsigned long lpar_rc;
 142
 143         lpar_rc = plpar_ipi(get_hard_smp_processor_id(n_cpu), value);
 144         if (lpar_rc != H_SUCCESS)
 145                 panic("bad return code qirr - rc = %lx\n", lpar_rc);
 146 }
 147
 148
 149 /* Interface to generic irq subsystem */
 150
 151 #ifdef CONFIG_SMP
 152 static int get_irq_server(unsigned int virq, unsigned int strict_check)
 153 {
 154         int server;
 155         /* For the moment only implement delivery to all cpus or one cpu */
 156         cpumask_t cpumask;
 157         cpumask_t tmp = CPU_MASK_NONE;
 158
 159         cpumask_copy(&cpumask, irq_desc[virq].affinity);
 160         if (!distribute_irqs)
 161                 return default_server;
 162
 163         if (!cpus_equal(cpumask, CPU_MASK_ALL)) {
 164                 cpus_and(tmp, cpu_online_map, cpumask);
 165
 166                 server = first_cpu(tmp);
 167
 168                 if (server < NR_CPUS)
 169                         return get_hard_smp_processor_id(server);
 170
 171                 if (strict_check)
 172                         return -1;
 173         }
 174
 175         if (cpus_equal(cpu_online_map, cpu_present_map))
 176                 return default_distrib_server;
 177
 178         return default_server;
 179 }
 180 #else
 181 static int get_irq_server(unsigned int virq, unsigned int strict_check)
 182 {
 183         return default_server;
 184 }
 185 #endif
 186
 187 static void xics_unmask_irq(unsigned int virq)
 188 {
 189         unsigned int irq;
 190         int call_status;
 191         int server;
 192
 193         pr_debug("xics: unmask virq %d\n", virq);
 194
 195         irq = (unsigned int)irq_map[virq].hwirq;
 196         pr_debug(" -> map to hwirq 0x%x\n", irq);
 197         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 198                 return;
 199
 200         server = get_irq_server(virq, 0);
 201
 202         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq, server,
 203                                 DEFAULT_PRIORITY);
 204         if (call_status != 0) {
 205                 printk(KERN_ERR
 206                         "%s: ibm_set_xive irq %u server %x returned %d\n",
 207                         __func__, irq, server, call_status);
 208                 return;
 209         }
 210
 211         /* Now unmask the interrupt (often a no-op) */
 212         call_status = rtas_call(ibm_int_on, 1, 1, NULL, irq);
 213         if (call_status != 0) {
 214                 printk(KERN_ERR "%s: ibm_int_on irq=%u returned %d\n",
 215                         __func__, irq, call_status);
 216                 return;
 217         }
 218 }
 219
 220 static unsigned int xics_startup(unsigned int virq)
 221 {
 222         /* unmask it */
 223         xics_unmask_irq(virq);
 224         return 0;
 225 }
 226
 227 static void xics_mask_real_irq(unsigned int irq)
 228 {
 229         int call_status;
 230
 231         if (irq == XICS_IPI)
 232                 return;
 233
 234         call_status = rtas_call(ibm_int_off, 1, 1, NULL, irq);
 235         if (call_status != 0) {
 236                 printk(KERN_ERR "%s: ibm_int_off irq=%u returned %d\n",
 237                         __func__, irq, call_status);
 238                 return;
 239         }
 240
 241         /* Have to set XIVE to 0xff to be able to remove a slot */
 242         call_status = rtas_call(ibm_set_xive, 3, 1, NULL, irq,
 243                                 default_server, 0xff);
 244         if (call_status != 0) {
 245                 printk(KERN_ERR "%s: ibm_set_xive(0xff) irq=%u returned %d\n",
 246                         __func__, irq, call_status);
 247                 return;
 248         }
 249 }
 250
 251 static void xics_mask_irq(unsigned int virq)
 252 {
 253         unsigned int irq;
 254
 255         pr_debug("xics: mask virq %d\n", virq);
 256
 257         irq = (unsigned int)irq_map[virq].hwirq;
 258         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 259                 return;
 260         xics_mask_real_irq(irq);
 261 }
 262
 263 static void xics_mask_unknown_vec(unsigned int vec)
 264 {
 265         printk(KERN_ERR "Interrupt %u (real) is invalid, disabling it.\n", vec);
 266         xics_mask_real_irq(vec);
 267 }
 268
 269 static inline unsigned int xics_xirr_vector(unsigned int xirr)
 270 {
 271         /*
 272          * The top byte is the old cppr, to be restored on EOI.
 273          * The remaining 24 bits are the vector.
 274          */
 275         return xirr & 0x00ffffff;
 276 }
 277
 278 static unsigned int xics_get_irq_direct(void)
 279 {
 280         unsigned int xirr = direct_xirr_info_get();
 281         unsigned int vec = xics_xirr_vector(xirr);
 282         unsigned int irq;
 283
 284         if (vec == XICS_IRQ_SPURIOUS)
 285                 return NO_IRQ;
 286
 287         irq = irq_radix_revmap_lookup(xics_host, vec);
 288         if (likely(irq != NO_IRQ))
 289                 return irq;
 290
 291         /* We don't have a linux mapping, so have rtas mask it. */
 292         xics_mask_unknown_vec(vec);
 293
 294         /* We might learn about it later, so EOI it */
 295         direct_xirr_info_set(xirr);
 296         return NO_IRQ;
 297 }
 298
 299 static unsigned int xics_get_irq_lpar(void)
 300 {
 301         unsigned int xirr = lpar_xirr_info_get();
 302         unsigned int vec = xics_xirr_vector(xirr);
 303         unsigned int irq;
 304
 305         if (vec == XICS_IRQ_SPURIOUS)
 306                 return NO_IRQ;
 307
 308         irq = irq_radix_revmap_lookup(xics_host, vec);
 309         if (likely(irq != NO_IRQ))
 310                 return irq;
 311
 312         /* We don't have a linux mapping, so have RTAS mask it. */
 313         xics_mask_unknown_vec(vec);
 314
 315         /* We might learn about it later, so EOI it */
 316         lpar_xirr_info_set(xirr);
 317         return NO_IRQ;
 318 }
 319
 320 static void xics_eoi_direct(unsigned int virq)
 321 {
 322         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 323
 324         iosync();
 325         direct_xirr_info_set((0xff << 24) | irq);
 326 }
 327
 328 static void xics_eoi_lpar(unsigned int virq)
 329 {
 330         unsigned int irq = (unsigned int)irq_map[virq].hwirq;
 331
 332         iosync();
 333         lpar_xirr_info_set((0xff << 24) | irq);
 334 }
 335
 336 static void xics_set_affinity(unsigned int virq, const struct cpumask *cpumask)
 337 {
 338         unsigned int irq;
 339         int status;
 340         int xics_status[2];
 341         int irq_server;
 342
 343         irq = (unsigned int)irq_map[virq].hwirq;
 344         if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 345                 return;
 346
 347         status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 348
 349         if (status) {
 350                 printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
 351                         __func__, irq, status);
 352                 return;
 353         }
 354
 355         /*
 356          * For the moment only implement delivery to all cpus or one cpu.
 357          * Get current irq_server for the given irq
 358          */
 359         irq_server = get_irq_server(virq, 1);
 360         if (irq_server == -1) {
 361                 char cpulist[128];
 362                 cpumask_scnprintf(cpulist, sizeof(cpulist), cpumask);
 363                 printk(KERN_WARNING
 364                         "%s: No online cpus in the mask %s for irq %d\n",
 365                         __func__, cpulist, virq);
 366                 return;
 367         }
 368
 369         status = rtas_call(ibm_set_xive, 3, 1, NULL,
 370                                 irq, irq_server, xics_status[1]);
 371
 372         if (status) {
 373                 printk(KERN_ERR "%s: ibm,set-xive irq=%u returns %d\n",
 374                         __func__, irq, status);
 375                 return;
 376         }
 377 }
 378
 379 static struct irq_chip xics_pic_direct = {
 380         .typename = " XICS     ",
 381         .startup = xics_startup,
 382         .mask = xics_mask_irq,
 383         .unmask = xics_unmask_irq,
 384         .eoi = xics_eoi_direct,
 385         .set_affinity = xics_set_affinity
 386 };
 387
 388 static struct irq_chip xics_pic_lpar = {
 389         .typename = " XICS     ",
 390         .startup = xics_startup,
 391         .mask = xics_mask_irq,
 392         .unmask = xics_unmask_irq,
 393         .eoi = xics_eoi_lpar,
 394         .set_affinity = xics_set_affinity
 395 };
 396
 397
 398 /* Interface to arch irq controller subsystem layer */
 399
 400 /* Points to the irq_chip we're actually using */
 401 static struct irq_chip *xics_irq_chip;
 402
 403 static int xics_host_match(struct irq_host *h, struct device_node *node)
 404 {
 405         /* IBM machines have interrupt parents of various funky types for things
 406          * like vdevices, events, etc... The trick we use here is to match
 407          * everything here except the legacy 8259 which is compatible "chrp,iic"
 408          */
 409         return !of_device_is_compatible(node, "chrp,iic");
 410 }
 411
 412 static int xics_host_map(struct irq_host *h, unsigned int virq,
 413                          irq_hw_number_t hw)
 414 {
 415         pr_debug("xics: map virq %d, hwirq 0x%lx\n", virq, hw);
 416
 417         /* Insert the interrupt mapping into the radix tree for fast lookup */
 418         irq_radix_revmap_insert(xics_host, virq, hw);
 419
 420         get_irq_desc(virq)->status |= IRQ_LEVEL;
 421         set_irq_chip_and_handler(virq, xics_irq_chip, handle_fasteoi_irq);
 422         return 0;
 423 }
 424
 425 static int xics_host_xlate(struct irq_host *h, struct device_node *ct,
 426                            u32 *intspec, unsigned int intsize,
 427                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
 428
 429 {
 430         /* Current xics implementation translates everything
 431          * to level. It is not technically right for MSIs but this
 432          * is irrelevant at this point. We might get smarter in the future
 433          */
 434         *out_hwirq = intspec[0];
 435         *out_flags = IRQ_TYPE_LEVEL_LOW;
 436
 437         return 0;
 438 }
 439
 440 static struct irq_host_ops xics_host_ops = {
 441         .match = xics_host_match,
 442         .map = xics_host_map,
 443         .xlate = xics_host_xlate,
 444 };
 445
 446 static void __init xics_init_host(void)
 447 {
 448         if (firmware_has_feature(FW_FEATURE_LPAR))
 449                 xics_irq_chip = &xics_pic_lpar;
 450         else
 451                 xics_irq_chip = &xics_pic_direct;
 452
 453         xics_host = irq_alloc_host(NULL, IRQ_HOST_MAP_TREE, 0, &xics_host_ops,
 454                                    XICS_IRQ_SPURIOUS);
 455         BUG_ON(xics_host == NULL);
 456         irq_set_default_host(xics_host);
 457 }
 458
 459
 460 /* Inter-processor interrupt support */
 461
 462 #ifdef CONFIG_SMP
 463 /*
 464  * XICS only has a single IPI, so encode the messages per CPU
 465  */
 466 struct xics_ipi_struct {
 467         unsigned long value;
 468         } ____cacheline_aligned;
 469
 470 static struct xics_ipi_struct xics_ipi_message[NR_CPUS] __cacheline_aligned;
 471
 472 static inline void smp_xics_do_message(int cpu, int msg)
 473 {
 474         set_bit(msg, &xics_ipi_message[cpu].value);
 475         mb();
 476         if (firmware_has_feature(FW_FEATURE_LPAR))
 477                 lpar_qirr_info(cpu, IPI_PRIORITY);
 478         else
 479                 direct_qirr_info(cpu, IPI_PRIORITY);
 480 }
 481
 482 void smp_xics_message_pass(int target, int msg)
 483 {
 484         unsigned int i;
 485
 486         if (target < NR_CPUS) {
 487                 smp_xics_do_message(target, msg);
 488         } else {
 489                 for_each_online_cpu(i) {
 490                         if (target == MSG_ALL_BUT_SELF
 491                             && i == smp_processor_id())
 492                                 continue;
 493                         smp_xics_do_message(i, msg);
 494                 }
 495         }
 496 }
 497
 498 static irqreturn_t xics_ipi_dispatch(int cpu)
 499 {
 500         WARN_ON(cpu_is_offline(cpu));
 501
 502         mb();   /* order mmio clearing qirr */
 503         while (xics_ipi_message[cpu].value) {
 504                 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION,
 505                                        &xics_ipi_message[cpu].value)) {
 506                         smp_message_recv(PPC_MSG_CALL_FUNCTION);
 507                 }
 508                 if (test_and_clear_bit(PPC_MSG_RESCHEDULE,
 509                                        &xics_ipi_message[cpu].value)) {
 510                         smp_message_recv(PPC_MSG_RESCHEDULE);
 511                 }
 512                 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE,
 513                                        &xics_ipi_message[cpu].value)) {
 514                         smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE);
 515                 }
 516 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
 517                 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK,
 518                                        &xics_ipi_message[cpu].value)) {
 519                         smp_message_recv(PPC_MSG_DEBUGGER_BREAK);
 520                 }
 521 #endif
 522         }
 523         return IRQ_HANDLED;
 524 }
 525
 526 static irqreturn_t xics_ipi_action_direct(int irq, void *dev_id)
 527 {
 528         int cpu = smp_processor_id();
 529
 530         direct_qirr_info(cpu, 0xff);
 531
 532         return xics_ipi_dispatch(cpu);
 533 }
 534
 535 static irqreturn_t xics_ipi_action_lpar(int irq, void *dev_id)
 536 {
 537         int cpu = smp_processor_id();
 538
 539         lpar_qirr_info(cpu, 0xff);
 540
 541         return xics_ipi_dispatch(cpu);
 542 }
 543
 544 static void xics_request_ipi(void)
 545 {
 546         unsigned int ipi;
 547         int rc;
 548
 549         ipi = irq_create_mapping(xics_host, XICS_IPI);
 550         BUG_ON(ipi == NO_IRQ);
 551
 552         /*
 553          * IPIs are marked IRQF_DISABLED as they must run with irqs
 554          * disabled
 555          */
 556         set_irq_handler(ipi, handle_percpu_irq);
 557         if (firmware_has_feature(FW_FEATURE_LPAR))
 558                 rc = request_irq(ipi, xics_ipi_action_lpar,
 559                                 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
 560         else
 561                 rc = request_irq(ipi, xics_ipi_action_direct,
 562                                 IRQF_DISABLED|IRQF_PERCPU, "IPI", NULL);
 563         BUG_ON(rc);
 564 }
 565
 566 int __init smp_xics_probe(void)
 567 {
 568         xics_request_ipi();
 569
 570         return cpus_weight(cpu_possible_map);
 571 }
 572
 573 #endif /* CONFIG_SMP */
 574
 575
 576 /* Initialization */
 577
 578 static void xics_update_irq_servers(void)
 579 {
 580         int i, j;
 581         struct device_node *np;
 582         u32 ilen;
 583         const u32 *ireg;
 584         u32 hcpuid;
 585
 586         /* Find the server numbers for the boot cpu. */
 587         np = of_get_cpu_node(boot_cpuid, NULL);
 588         BUG_ON(!np);
 589
 590         ireg = of_get_property(np, "ibm,ppc-interrupt-gserver#s", &ilen);
 591         if (!ireg) {
 592                 of_node_put(np);
 593                 return;
 594         }
 595
 596         i = ilen / sizeof(int);
 597         hcpuid = get_hard_smp_processor_id(boot_cpuid);
 598
 599         /* Global interrupt distribution server is specified in the last
 600          * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
 601          * entry fom this property for current boot cpu id and use it as
 602          * default distribution server
 603          */
 604         for (j = 0; j < i; j += 2) {
 605                 if (ireg[j] == hcpuid) {
 606                         default_server = hcpuid;
 607                         default_distrib_server = ireg[j+1];
 608                 }
 609         }
 610
 611         of_node_put(np);
 612 }
 613
 614 static void __init xics_map_one_cpu(int hw_id, unsigned long addr,
 615                                      unsigned long size)
 616 {
 617         int i;
 618
 619         /* This may look gross but it's good enough for now, we don't quite
 620          * have a hard -> linux processor id matching.
 621          */
 622         for_each_possible_cpu(i) {
 623                 if (!cpu_present(i))
 624                         continue;
 625                 if (hw_id == get_hard_smp_processor_id(i)) {
 626                         xics_per_cpu[i] = ioremap(addr, size);
 627                         return;
 628                 }
 629         }
 630 }
 631
 632 static void __init xics_init_one_node(struct device_node *np,
 633                                       unsigned int *indx)
 634 {
 635         unsigned int ilen;
 636         const u32 *ireg;
 637
 638         /* This code does the theorically broken assumption that the interrupt
 639          * server numbers are the same as the hard CPU numbers.
 640          * This happens to be the case so far but we are playing with fire...
 641          * should be fixed one of these days. -BenH.
 642          */
 643         ireg = of_get_property(np, "ibm,interrupt-server-ranges", NULL);
 644
 645         /* Do that ever happen ? we'll know soon enough... but even good'old
 646          * f80 does have that property ..
 647          */
 648         WARN_ON(ireg == NULL);
 649         if (ireg) {
 650                 /*
 651                  * set node starting index for this node
 652                  */
 653                 *indx = *ireg;
 654         }
 655         ireg = of_get_property(np, "reg", &ilen);
 656         if (!ireg)
 657                 panic("xics_init_IRQ: can't find interrupt reg property");
 658
 659         while (ilen >= (4 * sizeof(u32))) {
 660                 unsigned long addr, size;
 661
 662                 /* XXX Use proper OF parsing code here !!! */
 663                 addr = (unsigned long)*ireg++ << 32;
 664                 ilen -= sizeof(u32);
 665                 addr |= *ireg++;
 666                 ilen -= sizeof(u32);
 667                 size = (unsigned long)*ireg++ << 32;
 668                 ilen -= sizeof(u32);
 669                 size |= *ireg++;
 670                 ilen -= sizeof(u32);
 671                 xics_map_one_cpu(*indx, addr, size);
 672                 (*indx)++;
 673         }
 674 }
 675
 676 void __init xics_init_IRQ(void)
 677 {
 678         struct device_node *np;
 679         u32 indx = 0;
 680         int found = 0;
 681         const u32 *isize;
 682
 683         ppc64_boot_msg(0x20, "XICS Init");
 684
 685         ibm_get_xive = rtas_token("ibm,get-xive");
 686         ibm_set_xive = rtas_token("ibm,set-xive");
 687         ibm_int_on  = rtas_token("ibm,int-on");
 688         ibm_int_off = rtas_token("ibm,int-off");
 689
 690         for_each_node_by_type(np, "PowerPC-External-Interrupt-Presentation") {
 691                 found = 1;
 692                 if (firmware_has_feature(FW_FEATURE_LPAR)) {
 693                         of_node_put(np);
 694                         break;
 695                         }
 696                 xics_init_one_node(np, &indx);
 697         }
 698         if (found == 0)
 699                 return;
 700
 701         /* get the bit size of server numbers */
 702         found = 0;
 703
 704         for_each_compatible_node(np, NULL, "ibm,ppc-xics") {
 705                 isize = of_get_property(np, "ibm,interrupt-server#-size", NULL);
 706
 707                 if (!isize)
 708                         continue;
 709
 710                 if (!found) {
 711                         interrupt_server_size = *isize;
 712                         found = 1;
 713                 } else if (*isize != interrupt_server_size) {
 714                         printk(KERN_WARNING "XICS: "
 715                                "mismatched ibm,interrupt-server#-size\n");
 716                         interrupt_server_size = max(*isize,
 717                                                     interrupt_server_size);
 718                 }
 719         }
 720
 721         xics_update_irq_servers();
 722         xics_init_host();
 723
 724         if (firmware_has_feature(FW_FEATURE_LPAR))
 725                 ppc_md.get_irq = xics_get_irq_lpar;
 726         else
 727                 ppc_md.get_irq = xics_get_irq_direct;
 728
 729         xics_setup_cpu();
 730
 731         ppc64_boot_msg(0x21, "XICS Done");
 732 }
 733
 734 /* Cpu startup, shutdown, and hotplug */
 735
 736 static void xics_set_cpu_priority(unsigned char cppr)
 737 {
 738         if (firmware_has_feature(FW_FEATURE_LPAR))
 739                 lpar_cppr_info(cppr);
 740         else
 741                 direct_cppr_info(cppr);
 742         iosync();
 743 }
 744
 745 /* Have the calling processor join or leave the specified global queue */
 746 static void xics_set_cpu_giq(unsigned int gserver, unsigned int join)
 747 {
 748         int index;
 749         int status;
 750
 751         if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE, NULL))
 752                 return;
 753
 754         index = (1UL << interrupt_server_size) - 1 - gserver;
 755
 756         status = rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE, index, join);
 757
 758         WARN(status < 0, "set-indicator(%d, %d, %u) returned %d\n",
 759              GLOBAL_INTERRUPT_QUEUE, index, join, status);
 760 }
 761
 762 void xics_setup_cpu(void)
 763 {
 764         xics_set_cpu_priority(0xff);
 765
 766         xics_set_cpu_giq(default_distrib_server, 1);
 767 }
 768
 769 void xics_teardown_cpu(void)
 770 {
 771         int cpu = smp_processor_id();
 772
 773         xics_set_cpu_priority(0);
 774
 775         /* Clear any pending IPI request */
 776         if (firmware_has_feature(FW_FEATURE_LPAR))
 777                 lpar_qirr_info(cpu, 0xff);
 778         else
 779                 direct_qirr_info(cpu, 0xff);
 780 }
 781
 782 void xics_kexec_teardown_cpu(int secondary)
 783 {
 784         xics_teardown_cpu();
 785
 786         /*
 787          * we take the ipi irq but and never return so we
 788          * need to EOI the IPI, but want to leave our priority 0
 789          *
 790          * should we check all the other interrupts too?
 791          * should we be flagging idle loop instead?
 792          * or creating some task to be scheduled?
 793          */
 794
 795         if (firmware_has_feature(FW_FEATURE_LPAR))
 796                 lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
 797         else
 798                 direct_xirr_info_set((0x00 << 24) | XICS_IPI);
 799
 800         /*
 801          * Some machines need to have at least one cpu in the GIQ,
 802          * so leave the master cpu in the group.
 803          */
 804         if (secondary)
 805                 xics_set_cpu_giq(default_distrib_server, 0);
 806 }
 807
 808 #ifdef CONFIG_HOTPLUG_CPU
 809
 810 /* Interrupts are disabled. */
 811 void xics_migrate_irqs_away(void)
 812 {
 813         int cpu = smp_processor_id(), hw_cpu = hard_smp_processor_id();
 814         unsigned int irq, virq;
 815
 816         /* If we used to be the default server, move to the new "boot_cpuid" */
 817         if (hw_cpu == default_server)
 818                 xics_update_irq_servers();
 819
 820         /* Reject any interrupt that was queued to us... */
 821         xics_set_cpu_priority(0);
 822
 823         /* Remove ourselves from the global interrupt queue */
 824         xics_set_cpu_giq(default_distrib_server, 0);
 825
 826         /* Allow IPIs again... */
 827         xics_set_cpu_priority(DEFAULT_PRIORITY);
 828
 829         for_each_irq(virq) {
 830                 struct irq_desc *desc;
 831                 int xics_status[2];
 832                 int status;
 833                 unsigned long flags;
 834
 835                 /* We cant set affinity on ISA interrupts */
 836                 if (virq < NUM_ISA_INTERRUPTS)
 837                         continue;
 838                 if (irq_map[virq].host != xics_host)
 839                         continue;
 840                 irq = (unsigned int)irq_map[virq].hwirq;
 841                 /* We need to get IPIs still. */
 842                 if (irq == XICS_IPI || irq == XICS_IRQ_SPURIOUS)
 843                         continue;
 844                 desc = get_irq_desc(virq);
 845
 846                 /* We only need to migrate enabled IRQS */
 847                 if (desc == NULL || desc->chip == NULL
 848                     || desc->action == NULL
 849                     || desc->chip->set_affinity == NULL)
 850                         continue;
 851
 852                 spin_lock_irqsave(&desc->lock, flags);
 853
 854                 status = rtas_call(ibm_get_xive, 1, 3, xics_status, irq);
 855                 if (status) {
 856                         printk(KERN_ERR "%s: ibm,get-xive irq=%u returns %d\n",
 857                                         __func__, irq, status);
 858                         goto unlock;
 859                 }
 860
 861                 /*
 862                  * We only support delivery to all cpus or to one cpu.
 863                  * The irq has to be migrated only in the single cpu
 864                  * case.
 865                  */
 866                 if (xics_status[0] != hw_cpu)
 867                         goto unlock;
 868
 869                 printk(KERN_WARNING "IRQ %u affinity broken off cpu %u\n",
 870                        virq, cpu);
 871
 872                 /* Reset affinity to all cpus */
 873                 cpumask_setall(irq_desc[virq].affinity);
 874                 desc->chip->set_affinity(virq, cpu_all_mask);
 875 unlock:
 876                 spin_unlock_irqrestore(&desc->lock, flags);
 877         }
 878 }
 879 #endif