arch/arm/plat-omap/include/mach/clock.h

   1 /*
   2  *  arch/arm/plat-omap/include/mach/clock.h
   3  *
   4  *  Copyright (C) 2004 - 2005 Nokia corporation
   5  *  Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
   6  *  Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  */
  12
  13 #ifndef __ARCH_ARM_OMAP_CLOCK_H
  14 #define __ARCH_ARM_OMAP_CLOCK_H
  15
  16 struct module;
  17 struct clk;
  18 struct clockdomain;
  19
  20 struct clkops {
  21         int                     (*enable)(struct clk *);
  22         void                    (*disable)(struct clk *);
  23 };
  24
  25 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  26
  27 struct clksel_rate {
  28         u32                     val;
  29         u8                      div;
  30         u8                      flags;
  31 };
  32
  33 struct clksel {
  34         struct clk               *parent;
  35         const struct clksel_rate *rates;
  36 };
  37
  38 struct dpll_data {
  39         void __iomem            *mult_div1_reg;
  40         u32                     mult_mask;
  41         u32                     div1_mask;
  42         unsigned int            rate_tolerance;
  43         unsigned long           last_rounded_rate;
  44         u16                     last_rounded_m;
  45         u8                      last_rounded_n;
  46         u8                      min_divider;
  47         u8                      max_divider;
  48         u32                     max_tolerance;
  49         u16                     max_multiplier;
  50 #  if defined(CONFIG_ARCH_OMAP3)
  51         u8                      modes;
  52         void __iomem            *control_reg;
  53         void __iomem            *autoidle_reg;
  54         void __iomem            *idlest_reg;
  55         u32                     enable_mask;
  56         u32                     autoidle_mask;
  57         u32                     freqsel_mask;
  58         u32                     idlest_mask;
  59         u8                      auto_recal_bit;
  60         u8                      recal_en_bit;
  61         u8                      recal_st_bit;
  62 #  endif
  63 };
  64
  65 #endif
  66
  67 struct clk {
  68         struct list_head        node;
  69         const struct clkops     *ops;
  70         const char              *name;
  71         int                     id;
  72         struct clk              *parent;
  73         unsigned long           rate;
  74         __u32                   flags;
  75         void __iomem            *enable_reg;
  76         void                    (*recalc)(struct clk *);
  77         int                     (*set_rate)(struct clk *, unsigned long);
  78         long                    (*round_rate)(struct clk *, unsigned long);
  79         void                    (*init)(struct clk *);
  80         __u8                    enable_bit;
  81         __s8                    usecount;
  82 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  83         u8                      fixed_div;
  84         void __iomem            *clksel_reg;
  85         u32                     clksel_mask;
  86         const struct clksel     *clksel;
  87         struct dpll_data        *dpll_data;
  88         const char              *clkdm_name;
  89         struct clockdomain      *clkdm;
  90 #else
  91         __u8                    rate_offset;
  92         __u8                    src_offset;
  93 #endif
  94 #if defined(CONFIG_PM_DEBUG) && defined(CONFIG_DEBUG_FS)
  95         struct dentry           *dent;  /* For visible tree hierarchy */
  96 #endif
  97 };
  98
  99 struct cpufreq_frequency_table;
 100
 101 struct clk_functions {
 102         int             (*clk_enable)(struct clk *clk);
 103         void            (*clk_disable)(struct clk *clk);
 104         long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
 105         int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
 106         int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
 107         void            (*clk_allow_idle)(struct clk *clk);
 108         void            (*clk_deny_idle)(struct clk *clk);
 109         void            (*clk_disable_unused)(struct clk *clk);
 110 #ifdef CONFIG_CPU_FREQ
 111         void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **);
 112 #endif
 113 };
 114
 115 extern unsigned int mpurate;
 116
 117 extern int clk_init(struct clk_functions *custom_clocks);
 118 extern int clk_register(struct clk *clk);
 119 extern void clk_unregister(struct clk *clk);
 120 extern void propagate_rate(struct clk *clk);
 121 extern void recalculate_root_clocks(void);
 122 extern void followparent_recalc(struct clk *clk);
 123 extern int clk_get_usecount(struct clk *clk);
 124 extern void clk_enable_init_clocks(void);
 125 #ifdef CONFIG_CPU_FREQ
 126 extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 127 #endif
 128
 129 extern const struct clkops clkops_null;
 130
 131 /* Clock flags */
 132 /* bit 0 is free */
 133 #define RATE_FIXED              (1 << 1)        /* Fixed clock rate */
 134 #define RATE_PROPAGATES         (1 << 2)        /* Program children too */
 135 /* bits 3-4 are free */
 136 #define ENABLE_REG_32BIT        (1 << 5)        /* Use 32-bit access */
 137 #define VIRTUAL_IO_ADDRESS      (1 << 6)        /* Clock in virtual address */
 138 #define CLOCK_IDLE_CONTROL      (1 << 7)
 139 #define CLOCK_NO_IDLE_PARENT    (1 << 8)
 140 #define DELAYED_APP             (1 << 9)        /* Delay application of clock */
 141 #define CONFIG_PARTICIPANT      (1 << 10)       /* Fundamental clock */
 142 #define ENABLE_ON_INIT          (1 << 11)       /* Enable upon framework init */
 143 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
 144 /* bits 13-31 are currently free */
 145
 146 /* Clksel_rate flags */
 147 #define DEFAULT_RATE            (1 << 0)
 148 #define RATE_IN_242X            (1 << 1)
 149 #define RATE_IN_243X            (1 << 2)
 150 #define RATE_IN_343X            (1 << 3)        /* rates common to all 343X */
 151 #define RATE_IN_3430ES2         (1 << 4)        /* 3430ES2 rates only */
 152
 153 #define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
 154
 155
 156 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
 157 #define CORE_CLK_SRC_32K                0
 158 #define CORE_CLK_SRC_DPLL               1
 159 #define CORE_CLK_SRC_DPLL_X2            2
 160
 161 #endif