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PSP-03.00.00.03
[linux-ginger.git] / arch / arm / mach-omap2 / smartreflex.c
blob9c5a6e9de51913b0479c4755e36a4e8846f7ea4d
1 /*
2 * linux/arch/arm/mach-omap3/smartreflex.c
3 *
4 * OMAP34XX SmartReflex Voltage Control
5 *
6 * Copyright (C) 2008 Nokia Corporation
7 * Kalle Jokiniemi
8 *
9 * Copyright (C) 2007 Texas Instruments, Inc.
10 * Lesly A M <x0080970@ti.com>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
17
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/clk.h>
25 #include <linux/sysfs.h>
26 #include <linux/kobject.h>
27 #include <linux/i2c/twl4030.h>
28 #include <linux/io.h>
29
30 #include <plat/omap34xx.h>
31 #include <plat/control.h>
32 #include <plat/clock.h>
33 #include <plat/omap-pm.h>
34
35 #include "prm.h"
36 #include "smartreflex.h"
37 #include "prm-regbits-34xx.h"
38
39 #define MAX_TRIES 100
40
41 #define SWCALC_OPP6_DELTA_NNT 379
42 #define SWCALC_OPP6_DELTA_PNT 227
43
44 struct omap_sr {
45 int srid;
46 int is_sr_reset;
47 int is_autocomp_active;
48 struct clk *clk;
49 struct clk *vdd_opp_clk;
50 u32 clk_length;
51 u32 req_opp_no;
52 u32 opp1_nvalue, opp2_nvalue, opp3_nvalue, opp4_nvalue;
53 u32 opp5_nvalue, opp6_nvalue;
54 u32 senp_mod, senn_mod;
55 void __iomem *srbase_addr;
56 void __iomem *vpbase_addr;
57 };
58
59 #define SR_REGADDR(offs) (sr->srbase_addr + offset)
60
61 static inline void sr_write_reg(struct omap_sr *sr, unsigned offset, u32 value)
62 {
63 __raw_writel(value, SR_REGADDR(offset));
64 }
65
66 static inline void sr_modify_reg(struct omap_sr *sr, unsigned offset, u32 mask,
67 u32 value)
68 {
69 u32 reg_val;
70
71 reg_val = __raw_readl(SR_REGADDR(offset));
72 reg_val &= ~mask;
73 reg_val |= value;
74
75 __raw_writel(reg_val, SR_REGADDR(offset));
76 }
77
78 static inline u32 sr_read_reg(struct omap_sr *sr, unsigned offset)
79 {
80 return __raw_readl(SR_REGADDR(offset));
81 }
82
83 static int sr_clk_enable(struct omap_sr *sr)
84 {
85 if (clk_enable(sr->clk) != 0) {
86 pr_err("Could not enable %s\n", sr->clk->name);
87 return -1;
88 }
89
90 /* set fclk- active , iclk- idle */
91 sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
92 SR_CLKACTIVITY_IOFF_FON);
93
94 return 0;
95 }
96
97 static void sr_clk_disable(struct omap_sr *sr)
98 {
99 /* set fclk, iclk- idle */
100 sr_modify_reg(sr, ERRCONFIG, SR_CLKACTIVITY_MASK,
101 SR_CLKACTIVITY_IOFF_FOFF);
102
103 clk_disable(sr->clk);
104 sr->is_sr_reset = 1;
105 }
106
107 static struct omap_sr sr1 = {
108 .srid = SR1,
109 .is_sr_reset = 1,
110 .is_autocomp_active = 0,
111 .clk_length = 0,
112 .srbase_addr = OMAP2_L4_IO_ADDRESS(OMAP34XX_SR1_BASE),
113 };
114
115 static struct omap_sr sr2 = {
116 .srid = SR2,
117 .is_sr_reset = 1,
118 .is_autocomp_active = 0,
119 .clk_length = 0,
120 .srbase_addr = OMAP2_L4_IO_ADDRESS(OMAP34XX_SR2_BASE),
121 };
122
123 static void cal_reciprocal(u32 sensor, u32 *sengain, u32 *rnsen)
124 {
125 u32 gn, rn, mul;
126
127 for (gn = 0; gn < GAIN_MAXLIMIT; gn++) {
128 mul = 1 << (gn + 8);
129 rn = mul / sensor;
130 if (rn < R_MAXLIMIT) {
131 *sengain = gn;
132 *rnsen = rn;
133 }
134 }
135 }
136
137 static u32 cal_test_nvalue(u32 sennval, u32 senpval)
138 {
139 u32 senpgain, senngain;
140 u32 rnsenp, rnsenn;
141
142 /* Calculating the gain and reciprocal of the SenN and SenP values */
143 cal_reciprocal(senpval, &senpgain, &rnsenp);
144 cal_reciprocal(sennval, &senngain, &rnsenn);
145
146 return (senpgain << NVALUERECIPROCAL_SENPGAIN_SHIFT) |
147 (senngain << NVALUERECIPROCAL_SENNGAIN_SHIFT) |
148 (rnsenp << NVALUERECIPROCAL_RNSENP_SHIFT) |
149 (rnsenn << NVALUERECIPROCAL_RNSENN_SHIFT);
150 }
151
152 /* determine the current OPP from the frequency
153 * we need to give this function last element of OPP rate table
154 * and the frequency
155 */
156 static u16 get_opp(struct omap_opp *opp_freq_table,
157 unsigned long freq)
158 {
159 struct omap_opp *prcm_config;
160
161 prcm_config = opp_freq_table;
162
163 if (prcm_config->rate <= freq)
164 return prcm_config->opp_id; /* Return the Highest OPP */
165 for (; prcm_config->rate; prcm_config--)
166 if (prcm_config->rate < freq)
167 return (prcm_config+1)->opp_id;
168 else if (prcm_config->rate == freq)
169 return prcm_config->opp_id;
170 /* Return the least OPP */
171 return (prcm_config+1)->opp_id;
172 }
173
174 static u16 get_vdd1_opp(void)
175 {
176 u16 opp;
177
178 if (sr1.vdd_opp_clk == NULL || IS_ERR(sr1.vdd_opp_clk) ||
179 mpu_opps == NULL)
180 return 0;
181
182 opp = get_opp(mpu_opps + MAX_VDD1_OPP, sr1.vdd_opp_clk->rate);
183 return opp;
184 }
185
186 static u16 get_vdd2_opp(void)
187 {
188 u16 opp;
189
190 if (sr2.vdd_opp_clk == NULL || IS_ERR(sr2.vdd_opp_clk) ||
191 l3_opps == NULL)
192 return 0;
193
194 opp = get_opp(l3_opps + MAX_VDD2_OPP, sr2.vdd_opp_clk->rate);
195 return opp;
196 }
197
198
199 static void sr_set_clk_length(struct omap_sr *sr)
200 {
201 struct clk *sys_ck;
202 u32 sys_clk_speed;
203
204 sys_ck = clk_get(NULL, "sys_ck");
205 sys_clk_speed = clk_get_rate(sys_ck);
206 clk_put(sys_ck);
207
208 switch (sys_clk_speed) {
209 case 12000000:
210 sr->clk_length = SRCLKLENGTH_12MHZ_SYSCLK;
211 break;
212 case 13000000:
213 sr->clk_length = SRCLKLENGTH_13MHZ_SYSCLK;
214 break;
215 case 19200000:
216 sr->clk_length = SRCLKLENGTH_19MHZ_SYSCLK;
217 break;
218 case 26000000:
219 sr->clk_length = SRCLKLENGTH_26MHZ_SYSCLK;
220 break;
221 case 38400000:
222 sr->clk_length = SRCLKLENGTH_38MHZ_SYSCLK;
223 break;
224 default:
225 pr_err("Invalid sysclk value: %d\n", sys_clk_speed);
226 break;
227 }
228 }
229
230 static void swcalc_opp6_RG(u32 rFuse, u32 gainFuse, u32 deltaNT,
231 u32* rAdj, u32* gainAdj)
232 {
233 u32 nAdj;
234 u32 g, r;
235
236 nAdj = ((1 << (gainFuse + 8))/rFuse) + deltaNT;
237
238 for (g = 0; g < GAIN_MAXLIMIT; g++) {
239 r = (1 << (g + 8)) / nAdj;
240 if (r < 256) {
241 *rAdj = r;
242 *gainAdj = g;
243 }
244 }
245 }
246
247 static u32 swcalc_opp6_nvalue(void)
248 {
249 u32 opp5_nvalue, opp6_nvalue;
250 u32 opp5_senPgain, opp5_senNgain, opp5_senPRN, opp5_senNRN;
251 u32 opp6_senPgain, opp6_senNgain, opp6_senPRN, opp6_senNRN;
252
253 opp5_nvalue = omap_ctrl_readl(OMAP343X_CONTROL_FUSE_OPP5_VDD1);
254
255 opp5_senPgain = (opp5_nvalue & 0x00f00000) >> 0x14;
256 opp5_senNgain = (opp5_nvalue & 0x000f0000) >> 0x10;
257
258 opp5_senPRN = (opp5_nvalue & 0x0000ff00) >> 0x8;
259 opp5_senNRN = (opp5_nvalue & 0x000000ff);
260
261 swcalc_opp6_RG(opp5_senNRN, opp5_senNgain, SWCALC_OPP6_DELTA_NNT,
262 &opp6_senNRN, &opp6_senNgain);
263
264 swcalc_opp6_RG(opp5_senPRN, opp5_senPgain, SWCALC_OPP6_DELTA_PNT,
265 &opp6_senPRN, &opp6_senPgain);
266
267 opp6_nvalue = (opp6_senPgain << 0x14) | (opp6_senNgain < 0x10) |
268 (opp6_senPRN << 0x8) | opp6_senNRN;
269
270 return opp6_nvalue;
271 }
272
273 static void sr_set_efuse_nvalues(struct omap_sr *sr)
274 {
275 if (sr->srid == SR1) {
276 sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
277 OMAP343X_SR1_SENNENABLE_MASK) >>
278 OMAP343X_SR1_SENNENABLE_SHIFT;
279 sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
280 OMAP343X_SR1_SENPENABLE_MASK) >>
281 OMAP343X_SR1_SENPENABLE_SHIFT;
282
283 sr->opp6_nvalue = swcalc_opp6_nvalue();
284 sr->opp5_nvalue = omap_ctrl_readl(
285 OMAP343X_CONTROL_FUSE_OPP5_VDD1);
286 sr->opp4_nvalue = omap_ctrl_readl(
287 OMAP343X_CONTROL_FUSE_OPP4_VDD1);
288 sr->opp3_nvalue = omap_ctrl_readl(
289 OMAP343X_CONTROL_FUSE_OPP3_VDD1);
290 sr->opp2_nvalue = omap_ctrl_readl(
291 OMAP343X_CONTROL_FUSE_OPP2_VDD1);
292 sr->opp1_nvalue = omap_ctrl_readl(
293 OMAP343X_CONTROL_FUSE_OPP1_VDD1);
294 } else if (sr->srid == SR2) {
295 sr->senn_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
296 OMAP343X_SR2_SENNENABLE_MASK) >>
297 OMAP343X_SR2_SENNENABLE_SHIFT;
298
299 sr->senp_mod = (omap_ctrl_readl(OMAP343X_CONTROL_FUSE_SR) &
300 OMAP343X_SR2_SENPENABLE_MASK) >>
301 OMAP343X_SR2_SENPENABLE_SHIFT;
302
303 sr->opp3_nvalue = omap_ctrl_readl(
304 OMAP343X_CONTROL_FUSE_OPP3_VDD2);
305 sr->opp2_nvalue = omap_ctrl_readl(
306 OMAP343X_CONTROL_FUSE_OPP2_VDD2);
307 sr->opp1_nvalue = omap_ctrl_readl(
308 OMAP343X_CONTROL_FUSE_OPP1_VDD2);
309 }
310 }
311
312 /* Hard coded nvalues for testing purposes, may cause device to hang! */
313 static void sr_set_testing_nvalues(struct omap_sr *sr)
314 {
315 if (sr->srid == SR1) {
316 sr->senp_mod = 0x03; /* SenN-M5 enabled */
317 sr->senn_mod = 0x03;
318
319 /* calculate nvalues for each opp */
320 sr->opp5_nvalue = cal_test_nvalue(0xacd + 0x330, 0x848 + 0x330);
321 sr->opp4_nvalue = cal_test_nvalue(0x964 + 0x2a0, 0x727 + 0x2a0);
322 sr->opp3_nvalue = cal_test_nvalue(0x85b + 0x200, 0x655 + 0x200);
323 sr->opp2_nvalue = cal_test_nvalue(0x506 + 0x1a0, 0x3be + 0x1a0);
324 sr->opp1_nvalue = cal_test_nvalue(0x373 + 0x100, 0x28c + 0x100);
325 } else if (sr->srid == SR2) {
326 sr->senp_mod = 0x03;
327 sr->senn_mod = 0x03;
328
329 sr->opp3_nvalue = cal_test_nvalue(0x76f + 0x200, 0x579 + 0x200);
330 sr->opp2_nvalue = cal_test_nvalue(0x4f5 + 0x1c0, 0x390 + 0x1c0);
331 sr->opp1_nvalue = cal_test_nvalue(0x359, 0x25d);
332 }
333
334 }
335
336 static void sr_set_nvalues(struct omap_sr *sr)
337 {
338 if (SR_TESTING_NVALUES)
339 sr_set_testing_nvalues(sr);
340 else
341 sr_set_efuse_nvalues(sr);
342 }
343
344 static void sr_configure_vp(int srid)
345 {
346 u32 vpconfig;
347 u32 vsel;
348 u32 target_opp_no;
349
350 if (srid == SR1) {
351 target_opp_no = get_vdd1_opp();
352 if (!target_opp_no)
353 /* Assume Nominal OPP as current OPP unknown */
354 vsel = mpu_opps[VDD1_OPP3].vsel;
355 else
356 vsel = mpu_opps[target_opp_no].vsel;
357
358 vpconfig = PRM_VP1_CONFIG_ERROROFFSET |
359 PRM_VP1_CONFIG_ERRORGAIN |
360 PRM_VP1_CONFIG_TIMEOUTEN |
361 vsel << OMAP3430_INITVOLTAGE_SHIFT;
362
363 /*
364 * Update the 'ON' voltage levels based on the VSEL.
365 * (See spruf8c.pdf sec 1.5.3.1)
366 */
367 prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
368 (vsel << OMAP3430_VC_CMD_ON_SHIFT),
369 OMAP3430_GR_MOD,
370 OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
371
372 prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
373 OMAP3_PRM_VP1_CONFIG_OFFSET);
374 prm_write_mod_reg(PRM_VP1_VSTEPMIN_SMPSWAITTIMEMIN |
375 PRM_VP1_VSTEPMIN_VSTEPMIN,
376 OMAP3430_GR_MOD,
377 OMAP3_PRM_VP1_VSTEPMIN_OFFSET);
378
379 prm_write_mod_reg(PRM_VP1_VSTEPMAX_SMPSWAITTIMEMAX |
380 PRM_VP1_VSTEPMAX_VSTEPMAX,
381 OMAP3430_GR_MOD,
382 OMAP3_PRM_VP1_VSTEPMAX_OFFSET);
383
384 prm_write_mod_reg(PRM_VP1_VLIMITTO_VDDMAX |
385 PRM_VP1_VLIMITTO_VDDMIN |
386 PRM_VP1_VLIMITTO_TIMEOUT,
387 OMAP3430_GR_MOD,
388 OMAP3_PRM_VP1_VLIMITTO_OFFSET);
389
390 /* Trigger initVDD value copy to voltage processor */
391 prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
392 OMAP3_PRM_VP1_CONFIG_OFFSET);
393
394 /* Clear initVDD copy trigger bit */
395 prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
396 OMAP3_PRM_VP1_CONFIG_OFFSET);
397
398 /* Force update of voltage */
399 prm_set_mod_reg_bits(OMAP3430_FORCEUPDATE, OMAP3430_GR_MOD,
400 OMAP3_PRM_VP1_CONFIG_OFFSET);
401 /* Clear force bit */
402 prm_clear_mod_reg_bits(OMAP3430_FORCEUPDATE, OMAP3430_GR_MOD,
403 OMAP3_PRM_VP1_CONFIG_OFFSET);
404
405 } else if (srid == SR2) {
406 target_opp_no = get_vdd2_opp();
407 if (!target_opp_no)
408 /* Assume Nominal OPP */
409 vsel = l3_opps[VDD2_OPP3].vsel;
410 else
411 vsel = l3_opps[target_opp_no].vsel;
412
413 /*
414 * Update the 'ON' voltage levels based on the VSEL.
415 * (See spruf8c.pdf sec 1.5.3.1)
416 */
417 prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
418 (vsel << OMAP3430_VC_CMD_ON_SHIFT),
419 OMAP3430_GR_MOD,
420 OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
421
422 vpconfig = PRM_VP2_CONFIG_ERROROFFSET |
423 PRM_VP2_CONFIG_ERRORGAIN |
424 PRM_VP2_CONFIG_TIMEOUTEN |
425 vsel << OMAP3430_INITVOLTAGE_SHIFT;
426
427 prm_write_mod_reg(vpconfig, OMAP3430_GR_MOD,
428 OMAP3_PRM_VP2_CONFIG_OFFSET);
429 prm_write_mod_reg(PRM_VP2_VSTEPMIN_SMPSWAITTIMEMIN |
430 PRM_VP2_VSTEPMIN_VSTEPMIN,
431 OMAP3430_GR_MOD,
432 OMAP3_PRM_VP2_VSTEPMIN_OFFSET);
433
434 prm_write_mod_reg(PRM_VP2_VSTEPMAX_SMPSWAITTIMEMAX |
435 PRM_VP2_VSTEPMAX_VSTEPMAX,
436 OMAP3430_GR_MOD,
437 OMAP3_PRM_VP2_VSTEPMAX_OFFSET);
438
439 prm_write_mod_reg(PRM_VP2_VLIMITTO_VDDMAX |
440 PRM_VP2_VLIMITTO_VDDMIN |
441 PRM_VP2_VLIMITTO_TIMEOUT,
442 OMAP3430_GR_MOD,
443 OMAP3_PRM_VP2_VLIMITTO_OFFSET);
444
445 /* Trigger initVDD value copy to voltage processor */
446 prm_set_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
447 OMAP3_PRM_VP2_CONFIG_OFFSET);
448
449 /* Clear initVDD copy trigger bit */
450 prm_clear_mod_reg_bits(PRM_VP1_CONFIG_INITVDD, OMAP3430_GR_MOD,
451 OMAP3_PRM_VP2_CONFIG_OFFSET);
452
453 /* Force update of voltage */
454 prm_set_mod_reg_bits(OMAP3430_FORCEUPDATE, OMAP3430_GR_MOD,
455 OMAP3_PRM_VP2_CONFIG_OFFSET);
456 /* Clear force bit */
457 prm_clear_mod_reg_bits(OMAP3430_FORCEUPDATE, OMAP3430_GR_MOD,
458 OMAP3_PRM_VP2_CONFIG_OFFSET);
459 }
460 }
461
462 static void sr_configure(struct omap_sr *sr)
463 {
464 u32 sr_config;
465 u32 senp_en , senn_en;
466
467 if (sr->clk_length == 0)
468 sr_set_clk_length(sr);
469
470 senp_en = sr->senp_mod;
471 senn_en = sr->senn_mod;
472 if (sr->srid == SR1) {
473 sr_config = SR1_SRCONFIG_ACCUMDATA |
474 (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
475 SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
476 SRCONFIG_MINMAXAVG_EN |
477 (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
478 (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
479 SRCONFIG_DELAYCTRL;
480
481 sr_write_reg(sr, SRCONFIG, sr_config);
482 sr_write_reg(sr, AVGWEIGHT, SR1_AVGWEIGHT_SENPAVGWEIGHT |
483 SR1_AVGWEIGHT_SENNAVGWEIGHT);
484
485 sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
486 SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
487 (SR1_ERRWEIGHT | SR1_ERRMAXLIMIT | SR1_ERRMINLIMIT));
488
489 } else if (sr->srid == SR2) {
490 sr_config = SR2_SRCONFIG_ACCUMDATA |
491 (sr->clk_length << SRCONFIG_SRCLKLENGTH_SHIFT) |
492 SRCONFIG_SENENABLE | SRCONFIG_ERRGEN_EN |
493 SRCONFIG_MINMAXAVG_EN |
494 (senn_en << SRCONFIG_SENNENABLE_SHIFT) |
495 (senp_en << SRCONFIG_SENPENABLE_SHIFT) |
496 SRCONFIG_DELAYCTRL;
497
498 sr_write_reg(sr, SRCONFIG, sr_config);
499 sr_write_reg(sr, AVGWEIGHT, SR2_AVGWEIGHT_SENPAVGWEIGHT |
500 SR2_AVGWEIGHT_SENNAVGWEIGHT);
501 sr_modify_reg(sr, ERRCONFIG, (SR_ERRWEIGHT_MASK |
502 SR_ERRMAXLIMIT_MASK | SR_ERRMINLIMIT_MASK),
503 (SR2_ERRWEIGHT | SR2_ERRMAXLIMIT | SR2_ERRMINLIMIT));
504
505 }
506 sr->is_sr_reset = 0;
507 }
508
509 static int sr_reset_voltage(int srid)
510 {
511 u32 target_opp_no, vsel = 0;
512 u32 reg_addr = 0;
513 u32 loop_cnt = 0, retries_cnt = 0;
514 u32 vc_bypass_value;
515 u32 t2_smps_steps = 0;
516 u32 t2_smps_delay = 0;
517 u32 prm_vp1_voltage, prm_vp2_voltage;
518
519 if (srid == SR1) {
520 target_opp_no = get_vdd1_opp();
521
522 if (!target_opp_no) {
523 pr_info("Current OPP unknown: Cannot reset voltage\n");
524 return 1;
525 }
526 vsel = mpu_opps[target_opp_no].vsel;
527 reg_addr = R_VDD1_SR_CONTROL;
528 prm_vp1_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
529 OMAP3_PRM_VP1_VOLTAGE_OFFSET);
530 t2_smps_steps = abs(vsel - prm_vp1_voltage);
531 } else if (srid == SR2) {
532 target_opp_no = get_vdd2_opp();
533 if (!target_opp_no) {
534 pr_info("Current OPP unknown: Cannot reset voltage\n");
535 return 1;
536 }
537 vsel = l3_opps[target_opp_no].vsel;
538 reg_addr = R_VDD2_SR_CONTROL;
539 prm_vp2_voltage = prm_read_mod_reg(OMAP3430_GR_MOD,
540 OMAP3_PRM_VP2_VOLTAGE_OFFSET);
541 t2_smps_steps = abs(vsel - prm_vp2_voltage);
542 }
543
544 vc_bypass_value = (vsel << OMAP3430_DATA_SHIFT) |
545 (reg_addr << OMAP3430_REGADDR_SHIFT) |
546 (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
547
548 prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
549 OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
550
551 vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
552 OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
553
554 while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
555 loop_cnt++;
556 if (retries_cnt > 10) {
557 pr_info("Loop count exceeded in check SR I2C"
558 "write\n");
559 return 1;
560 }
561 if (loop_cnt > 50) {
562 retries_cnt++;
563 loop_cnt = 0;
564 udelay(10);
565 }
566 vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
567 OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
568 }
569
570 /*
571 * T2 SMPS slew rate (min) 4mV/uS, step size 12.5mV,
572 * 2us added as buffer.
573 */
574 t2_smps_delay = ((t2_smps_steps * 125) / 40) + 2;
575 udelay(t2_smps_delay);
576
577 return 0;
578 }
579
580 static int sr_enable(struct omap_sr *sr, u32 target_opp_no)
581 {
582 u32 nvalue_reciprocal, v;
583
584 if (!(mpu_opps && l3_opps)) {
585 pr_notice("VSEL values not found\n");
586 return false;
587 }
588
589 sr->req_opp_no = target_opp_no;
590
591 if (sr->srid == SR1) {
592 switch (target_opp_no) {
593 case 6:
594 nvalue_reciprocal = sr->opp6_nvalue;
595 break;
596 case 5:
597 nvalue_reciprocal = sr->opp5_nvalue;
598 break;
599 case 4:
600 nvalue_reciprocal = sr->opp4_nvalue;
601 break;
602 case 3:
603 nvalue_reciprocal = sr->opp3_nvalue;
604 break;
605 case 2:
606 nvalue_reciprocal = sr->opp2_nvalue;
607 break;
608 case 1:
609 nvalue_reciprocal = sr->opp1_nvalue;
610 break;
611 default:
612 nvalue_reciprocal = sr->opp3_nvalue;
613 break;
614 }
615 } else {
616 switch (target_opp_no) {
617 case 3:
618 nvalue_reciprocal = sr->opp3_nvalue;
619 break;
620 case 2:
621 nvalue_reciprocal = sr->opp2_nvalue;
622 break;
623 case 1:
624 nvalue_reciprocal = sr->opp1_nvalue;
625 break;
626 default:
627 nvalue_reciprocal = sr->opp3_nvalue;
628 break;
629 }
630 }
631
632 if (nvalue_reciprocal == 0) {
633 pr_notice("OPP%d doesn't support SmartReflex\n",
634 target_opp_no);
635 return false;
636 }
637
638 sr_write_reg(sr, NVALUERECIPROCAL, nvalue_reciprocal);
639
640 /* Enable the interrupt */
641 sr_modify_reg(sr, ERRCONFIG,
642 (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST),
643 (ERRCONFIG_VPBOUNDINTEN | ERRCONFIG_VPBOUNDINTST));
644
645 if (sr->srid == SR1) {
646 /* set/latch init voltage */
647 v = prm_read_mod_reg(OMAP3430_GR_MOD,
648 OMAP3_PRM_VP1_CONFIG_OFFSET);
649 v &= ~(OMAP3430_INITVOLTAGE_MASK | OMAP3430_INITVDD);
650 v |= mpu_opps[target_opp_no].vsel <<
651 OMAP3430_INITVOLTAGE_SHIFT;
652 prm_write_mod_reg(v, OMAP3430_GR_MOD,
653 OMAP3_PRM_VP1_CONFIG_OFFSET);
654 /* write1 to latch */
655 prm_set_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD,
656 OMAP3_PRM_VP1_CONFIG_OFFSET);
657 /* write2 clear */
658 prm_clear_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD,
659 OMAP3_PRM_VP1_CONFIG_OFFSET);
660 /* Enable VP1 */
661 prm_set_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
662 OMAP3_PRM_VP1_CONFIG_OFFSET);
663 } else if (sr->srid == SR2) {
664 /* set/latch init voltage */
665 v = prm_read_mod_reg(OMAP3430_GR_MOD,
666 OMAP3_PRM_VP2_CONFIG_OFFSET);
667 v &= ~(OMAP3430_INITVOLTAGE_MASK | OMAP3430_INITVDD);
668 v |= l3_opps[target_opp_no].vsel <<
669 OMAP3430_INITVOLTAGE_SHIFT;
670 prm_write_mod_reg(v, OMAP3430_GR_MOD,
671 OMAP3_PRM_VP2_CONFIG_OFFSET);
672 /* write1 to latch */
673 prm_set_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD,
674 OMAP3_PRM_VP2_CONFIG_OFFSET);
675 /* write2 clear */
676 prm_clear_mod_reg_bits(OMAP3430_INITVDD, OMAP3430_GR_MOD,
677 OMAP3_PRM_VP2_CONFIG_OFFSET);
678 /* Enable VP2 */
679 prm_set_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
680 OMAP3_PRM_VP2_CONFIG_OFFSET);
681 }
682
683 /* SRCONFIG - enable SR */
684 sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, SRCONFIG_SRENABLE);
685 return true;
686 }
687
688 static void sr_disable(struct omap_sr *sr)
689 {
690 u32 i = 0;
691
692 sr->is_sr_reset = 1;
693
694 /* SRCONFIG - disable SR */
695 sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE, ~SRCONFIG_SRENABLE);
696
697 if (sr->srid == SR1) {
698 /* Wait for VP idle before disabling VP */
699 while ((!prm_read_mod_reg(OMAP3430_GR_MOD,
700 OMAP3_PRM_VP1_STATUS_OFFSET))
701 && i++ < MAX_TRIES)
702 udelay(1);
703
704 if (i >= MAX_TRIES)
705 pr_warning("VP1 not idle, still going ahead with \
706 VP1 disable\n");
707
708 /* Disable VP1 */
709 prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE, OMAP3430_GR_MOD,
710 OMAP3_PRM_VP1_CONFIG_OFFSET);
711
712 } else if (sr->srid == SR2) {
713 /* Wait for VP idle before disabling VP */
714 while ((!prm_read_mod_reg(OMAP3430_GR_MOD,
715 OMAP3_PRM_VP2_STATUS_OFFSET))
716 && i++ < MAX_TRIES)
717 udelay(1);
718
719 if (i >= MAX_TRIES)
720 pr_warning("VP2 not idle, still going ahead with \
721 VP2 disable\n");
722
723 /* Disable VP2 */
724 prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE, OMAP3430_GR_MOD,
725 OMAP3_PRM_VP2_CONFIG_OFFSET);
726 }
727 }
728
729
730 void sr_start_vddautocomap(int srid, u32 target_opp_no)
731 {
732 struct omap_sr *sr = NULL;
733
734 if (srid == SR1)
735 sr = &sr1;
736 else if (srid == SR2)
737 sr = &sr2;
738 else
739 return;
740
741 if (sr->is_sr_reset == 1) {
742 sr_clk_enable(sr);
743 sr_configure(sr);
744 }
745
746 if (sr->is_autocomp_active == 1)
747 pr_warning("SR%d: VDD autocomp is already active\n",
748 srid);
749
750 sr->is_autocomp_active = 1;
751 if (!sr_enable(sr, target_opp_no)) {
752 pr_warning("SR%d: VDD autocomp not activated\n", srid);
753 sr->is_autocomp_active = 0;
754 if (sr->is_sr_reset == 1)
755 sr_clk_disable(sr);
756 }
757 }
758 EXPORT_SYMBOL(sr_start_vddautocomap);
759
760 int sr_stop_vddautocomap(int srid)
761 {
762 struct omap_sr *sr = NULL;
763
764 if (srid == SR1)
765 sr = &sr1;
766 else if (srid == SR2)
767 sr = &sr2;
768 else
769 return -EINVAL;
770
771 if (sr->is_autocomp_active == 1) {
772 sr_disable(sr);
773 sr_clk_disable(sr);
774 sr->is_autocomp_active = 0;
775 /* Reset the volatage for current OPP */
776 sr_reset_voltage(srid);
777 return true;
778 } else {
779 pr_warning("SR%d: VDD autocomp is not active\n",
780 srid);
781 return false;
782 }
783
784 }
785 EXPORT_SYMBOL(sr_stop_vddautocomap);
786
787 void enable_smartreflex(int srid)
788 {
789 u32 target_opp_no = 0;
790 struct omap_sr *sr = NULL;
791
792 if (srid == SR1)
793 sr = &sr1;
794 else if (srid == SR2)
795 sr = &sr2;
796 else
797 return;
798
799 if (sr->is_autocomp_active == 1) {
800 if (sr->is_sr_reset == 1) {
801 /* Enable SR clks */
802 sr_clk_enable(sr);
803
804 if (srid == SR1)
805 target_opp_no = get_vdd1_opp();
806 else if (srid == SR2)
807 target_opp_no = get_vdd2_opp();
808
809 if (!target_opp_no) {
810 pr_info("Current OPP unknown \
811 Cannot configure SR\n");
812 }
813
814 sr_configure(sr);
815
816 if (!sr_enable(sr, target_opp_no))
817 sr_clk_disable(sr);
818 }
819 }
820 }
821
822 void disable_smartreflex(int srid)
823 {
824 u32 i = 0;
825
826 struct omap_sr *sr = NULL;
827
828 if (srid == SR1)
829 sr = &sr1;
830 else if (srid == SR2)
831 sr = &sr2;
832 else
833 return;
834
835 if (sr->is_autocomp_active == 1) {
836 if (sr->is_sr_reset == 0) {
837
838 sr->is_sr_reset = 1;
839 /* SRCONFIG - disable SR */
840 sr_modify_reg(sr, SRCONFIG, SRCONFIG_SRENABLE,
841 ~SRCONFIG_SRENABLE);
842
843 /* Disable SR clk */
844 sr_clk_disable(sr);
845 if (sr->srid == SR1) {
846 /* Wait for VP idle before disabling VP */
847 while ((!prm_read_mod_reg(OMAP3430_GR_MOD,
848 OMAP3_PRM_VP1_STATUS_OFFSET))
849 && i++ < MAX_TRIES)
850 udelay(1);
851
852 if (i >= MAX_TRIES)
853 pr_warning("VP1 not idle, still going \
854 ahead with VP1 disable\n");
855
856 /* Disable VP1 */
857 prm_clear_mod_reg_bits(PRM_VP1_CONFIG_VPENABLE,
858 OMAP3430_GR_MOD,
859 OMAP3_PRM_VP1_CONFIG_OFFSET);
860 } else if (sr->srid == SR2) {
861 /* Wait for VP idle before disabling VP */
862 while ((!prm_read_mod_reg(OMAP3430_GR_MOD,
863 OMAP3_PRM_VP2_STATUS_OFFSET))
864 && i++ < MAX_TRIES)
865 udelay(1);
866
867 if (i >= MAX_TRIES)
868 pr_warning("VP2 not idle, still going \
869 ahead with VP2 disable\n");
870
871 /* Disable VP2 */
872 prm_clear_mod_reg_bits(PRM_VP2_CONFIG_VPENABLE,
873 OMAP3430_GR_MOD,
874 OMAP3_PRM_VP2_CONFIG_OFFSET);
875 }
876 /* Reset the volatage for current OPP */
877 sr_reset_voltage(srid);
878 }
879 }
880 }
881
882 /* Voltage Scaling using SR VCBYPASS */
883 int sr_voltagescale_vcbypass(u32 target_opp, u32 current_opp,
884 u8 target_vsel, u8 current_vsel)
885 {
886 int sr_status = 0;
887 u32 vdd, target_opp_no, current_opp_no;
888 u32 vc_bypass_value;
889 u32 reg_addr = 0;
890 u32 loop_cnt = 0, retries_cnt = 0;
891 u32 t2_smps_steps = 0;
892 u32 t2_smps_delay = 0;
893
894 vdd = get_vdd(target_opp);
895 target_opp_no = get_opp_no(target_opp);
896 current_opp_no = get_opp_no(current_opp);
897
898 if (vdd == VDD1_OPP) {
899 sr_status = sr_stop_vddautocomap(SR1);
900 t2_smps_steps = abs(target_vsel - current_vsel);
901
902 prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
903 (target_vsel << OMAP3430_VC_CMD_ON_SHIFT),
904 OMAP3430_GR_MOD,
905 OMAP3_PRM_VC_CMD_VAL_0_OFFSET);
906 reg_addr = R_VDD1_SR_CONTROL;
907
908 } else if (vdd == VDD2_OPP) {
909 sr_status = sr_stop_vddautocomap(SR2);
910 t2_smps_steps = abs(target_vsel - current_vsel);
911
912 prm_rmw_mod_reg_bits(OMAP3430_VC_CMD_ON_MASK,
913 (target_vsel << OMAP3430_VC_CMD_ON_SHIFT),
914 OMAP3430_GR_MOD,
915 OMAP3_PRM_VC_CMD_VAL_1_OFFSET);
916 reg_addr = R_VDD2_SR_CONTROL;
917 }
918
919 vc_bypass_value = (target_vsel << OMAP3430_DATA_SHIFT) |
920 (reg_addr << OMAP3430_REGADDR_SHIFT) |
921 (R_SRI2C_SLAVE_ADDR << OMAP3430_SLAVEADDR_SHIFT);
922
923 prm_write_mod_reg(vc_bypass_value, OMAP3430_GR_MOD,
924 OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
925
926 vc_bypass_value = prm_set_mod_reg_bits(OMAP3430_VALID, OMAP3430_GR_MOD,
927 OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
928
929 while ((vc_bypass_value & OMAP3430_VALID) != 0x0) {
930 loop_cnt++;
931 if (retries_cnt > 10) {
932 pr_info("Loop count exceeded in check SR I2C"
933 "write\n");
934 return 1;
935 }
936 if (loop_cnt > 50) {
937 retries_cnt++;
938 loop_cnt = 0;
939 udelay(10);
940 }
941 vc_bypass_value = prm_read_mod_reg(OMAP3430_GR_MOD,
942 OMAP3_PRM_VC_BYPASS_VAL_OFFSET);
943 }
944
945 /*
946 * T2 SMPS slew rate (min) 4mV/uS, step size 12.5mV,
947 * 2us added as buffer.
948 */
949 t2_smps_delay = ((t2_smps_steps * 125) / 40) + 2;
950 udelay(t2_smps_delay);
951
952 if (sr_status) {
953 if (vdd == VDD1_OPP)
954 sr_start_vddautocomap(SR1, target_opp_no);
955 else if (vdd == VDD2_OPP)
956 sr_start_vddautocomap(SR2, target_opp_no);
957 }
958
959 return 0;
960 }
961
962 /* Sysfs interface to select SR VDD1 auto compensation */
963 static ssize_t omap_sr_vdd1_autocomp_show(struct kobject *kobj,
964 struct kobj_attribute *attr, char *buf)
965 {
966 return sprintf(buf, "%d\n", sr1.is_autocomp_active);
967 }
968
969 static ssize_t omap_sr_vdd1_autocomp_store(struct kobject *kobj,
970 struct kobj_attribute *attr,
971 const char *buf, size_t n)
972 {
973 unsigned short value;
974
975 if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
976 pr_err("sr_vdd1_autocomp: Invalid value\n");
977 return -EINVAL;
978 }
979
980 if (value == 0) {
981 sr_stop_vddautocomap(SR1);
982 } else {
983 u32 current_vdd1opp_no = get_vdd1_opp();
984 if (!current_vdd1opp_no) {
985 pr_err("sr_vdd1_autocomp: Current VDD1 opp unknown\n");
986 return -EINVAL;
987 }
988 sr_start_vddautocomap(SR1, current_vdd1opp_no);
989 }
990 return n;
991 }
992
993 static struct kobj_attribute sr_vdd1_autocomp = {
994 .attr = {
995 .name = __stringify(sr_vdd1_autocomp),
996 .mode = 0644,
997 },
998 .show = omap_sr_vdd1_autocomp_show,
999 .store = omap_sr_vdd1_autocomp_store,
1000 };
1001
1002 /* Sysfs interface to select SR VDD2 auto compensation */
1003 static ssize_t omap_sr_vdd2_autocomp_show(struct kobject *kobj,
1004 struct kobj_attribute *attr, char *buf)
1005 {
1006 return sprintf(buf, "%d\n", sr2.is_autocomp_active);
1007 }
1008
1009 static ssize_t omap_sr_vdd2_autocomp_store(struct kobject *kobj,
1010 struct kobj_attribute *attr,
1011 const char *buf, size_t n)
1012 {
1013 unsigned short value;
1014
1015 if (sscanf(buf, "%hu", &value) != 1 || (value > 1)) {
1016 pr_err("sr_vdd2_autocomp: Invalid value\n");
1017 return -EINVAL;
1018 }
1019
1020 if (value == 0) {
1021 sr_stop_vddautocomap(SR2);
1022 } else {
1023 u32 current_vdd2opp_no = get_vdd2_opp();
1024 if (!current_vdd2opp_no) {
1025 pr_err("sr_vdd2_autocomp: Current VDD2 opp unknown\n");
1026 return -EINVAL;
1027 }
1028 sr_start_vddautocomap(SR2, current_vdd2opp_no);
1029 }
1030 return n;
1031 }
1032
1033 static struct kobj_attribute sr_vdd2_autocomp = {
1034 .attr = {
1035 .name = __stringify(sr_vdd2_autocomp),
1036 .mode = 0644,
1037 },
1038 .show = omap_sr_vdd2_autocomp_show,
1039 .store = omap_sr_vdd2_autocomp_store,
1040 };
1041
1042
1043
1044 static int __init omap3_sr_init(void)
1045 {
1046 int ret = 0;
1047 u8 RdReg;
1048
1049 /* Exit if OPP tables are not defined */
1050 if (!(mpu_opps && l3_opps)) {
1051 pr_err("SR: OPP rate tables not defined for platform, not enabling SmartReflex\n");
1052 return -ENODEV;
1053 }
1054
1055 /* Enable SR on T2 */
1056 ret = twl4030_i2c_read_u8(TWL4030_MODULE_PM_RECEIVER, &RdReg,
1057 R_DCDC_GLOBAL_CFG);
1058
1059 RdReg |= DCDC_GLOBAL_CFG_ENABLE_SRFLX;
1060 ret |= twl4030_i2c_write_u8(TWL4030_MODULE_PM_RECEIVER, RdReg,
1061 R_DCDC_GLOBAL_CFG);
1062
1063 if (cpu_is_omap34xx()) {
1064 sr1.clk = clk_get(NULL, "sr1_fck");
1065 sr2.clk = clk_get(NULL, "sr2_fck");
1066 }
1067 sr1.vdd_opp_clk = clk_get(NULL, "dpll1_ck");
1068 sr2.vdd_opp_clk = clk_get(NULL, "l3_ick");
1069 sr_set_clk_length(&sr1);
1070 sr_set_clk_length(&sr2);
1071
1072 /* Call the VPConfig, VCConfig, set N Values. */
1073 sr_set_nvalues(&sr1);
1074 sr_configure_vp(SR1);
1075
1076 sr_set_nvalues(&sr2);
1077 sr_configure_vp(SR2);
1078
1079 pr_info("SmartReflex driver initialized\n");
1080
1081 ret = sysfs_create_file(power_kobj, &sr_vdd1_autocomp.attr);
1082 if (ret)
1083 pr_err("sysfs_create_file failed: %d\n", ret);
1084
1085 ret = sysfs_create_file(power_kobj, &sr_vdd2_autocomp.attr);
1086 if (ret)
1087 pr_err("sysfs_create_file failed: %d\n", ret);
1088
1089 return 0;
1090 }
1091
1092 late_initcall(omap3_sr_init);
Linux for Ginger Game Console